KR20090061233A - Plasma display panel device and the operating method of the same - Google Patents

Abstract

A plasma display panel device and an operating method of the same are provided to reduce a black brightness and erroneous discharge by driving on cell and off cell on a first quadrant. In a plasma display panel device and an operating method of the same, a plurality of scanning electrodes (Y1-Yn) and a sustain electrode (Z) are arranged on the plasma display panel. A sustain driving unit(34) operates the sustain electrode, and a scan driver(33) supplies a pulse to the scanning electrode. The pulse supplied to a scan electrode is used for driving an on-cell and an off-cell for an initialization period.

Description

Plasma display panel device and its driving method {Plasma display panel device and the operating method of the same}

The present invention relates to a plasma display panel, and more particularly, to an apparatus for driving a plasma display panel and a driving method thereof.

Plasma Display Panels (hereinafter referred to as "PDPs") are characterized by emitting phosphors by 147 nm ultraviolet rays generated during discharge of an inert mixed gas such as He + Xe, Ne + Xe or He + Xe + Ne. An image containing graphics is displayed. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode Y and a sustain electrode Z formed on the upper substrate 10, and an address electrode formed on the lower substrate 18. X). Each of the scan electrode Y and the sustain electrode Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z and is formed at one edge of the transparent electrode 13Y. , 13Z).

The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode Y and the sustain electrode Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode X is formed in a direction crossing the scan electrode Y and the sustain electrode Z. FIG.

The partition wall 24 is formed in parallel with the address electrode X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert mixed gas is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges.

Here, the initialization period is divided into a setup period in which the rising ramp waveform is supplied and a set down period in which the falling lamp waveform is supplied. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period is increased at a rate of 2n (n = 0, 1, 2, 3, 4, 5, 6, 7) in each subfield.

3 shows driving waveforms of a PDP supplied to two subfields.

Referring to FIG. 3, the PDP is divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y simultaneously. This rising ramp waveform (Ramp-up) causes a slight discharge in the cells of the full screen to generate wall charges in the cells. During the set down period, after the rising ramp waveform Ramp-up is supplied, the falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes Y. Applied simultaneously. Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing the wall charges required for address discharges in the cells of the full screen. Will remain.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive electrode DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs. Finally, after the sustain discharge is completed, an erase ramp waveform (erase) having a small pulse width is supplied to the sustain electrode Z to erase wall charges in the cell.

Here, the discharge generation principle of the sustain period and the wall charge initialization principle of the initialization period will be described in detail using a hexagonal voltage curve as shown in FIG. 4. Here, the Vt close curve is used as a method for measuring the discharge generation principle and the voltage margin of the PDP.

In FIG. 4, the hexagonal area inside the voltage curve is an area where the cell voltage inside the discharge cell is moved, and no discharge occurs when the cell voltage is located in the hexagonal area. In addition, Y (−) represents a direction in which the cell voltage moves when a negative voltage is applied to the scan electrode Y. FIG. Similarly, each of Y (+), X (+), X (-), Z (+), and Z (-) is a negative electrode or a positive electrode for the scan electrode Y, the address electrode X, and the sustain electrode Z. It indicates the direction in which the cell voltage moves when the voltage of the castle is applied.

The Vtxy displayed in the first quadrant opposite discharge region of the voltage curve graph represents the voltage at which discharge is started between the address electrode X and the scan electrode Y. FIG. In other words, the straight line representing the first quadrant opposite discharge region of the voltage curve graph is set to a length equal to the voltage at which the discharge between the address electrode X and the scan electrode Y is started. The Vtzy displayed in the quadrant surface discharge region of the voltage curve graph represents the voltage at which discharge starts between the sustain electrode Z and the scan electrode Y. FIG. Similarly, Vtxz, Vtzx, Vtyz, and Vtyx each represent a discharge start voltage between the electrodes.

Referring to the operation of the sustain period, the wall charges in the discharge cells in which the address discharge is generated are located in the third quadrant of the graph as shown in FIG. Subsequently, when the positive sustain pulse is applied to the scan electrode Y as shown in FIG. 3, the voltage values of the wall charges positioned in the third quadrant and the voltage values of the positive sustain pulse are added to the cell voltage. It is moved via the surface discharge area located at. In this case, sustain discharge is generated between the scan electrode Y and the sustain electrode Z in the discharge cells.

After the sustain discharge is generated, the wall charges are located in the first quadrant of the graph as shown in FIG. Subsequently, when the positive sustain pulse is applied to the sustain electrode Z, the voltage values of the wall charges positioned in the first quadrant and the voltage values of the positive sustain pulse are added together, so that the cell voltage is located in the first quadrant of the graph as shown in FIG. 6. It is moved via the discharge area (i.e., moved to the Z (+) side). At this time, sustain discharge is generated between the sustain electrode Z and the scan electrode Y in the discharge cells. In fact, in the sustain period, the same procedure as in FIGS. 5 and 6 is repeated to generate a predetermined number of sustain discharges.

After the sustain discharge is completed, the wall charges are located in the first quadrant of the graph as shown in FIG. 7. Thereafter, an erase ramp waveform (erase) is supplied to the sustain electrode (Z). When the erase ramp waveform (erase) is supplied to the sustain electrode (Z), the cell voltage is moved through the surface discharge region of the first quadrant of the graph (that is, moved to the Z (+) side) as shown in FIG. In this case, when the cell voltage passes through the quadrant surface discharge region of the graph, the wall charges move at a slope of 1/2. In other words, as shown in FIG. 7, the wall charges are moved to the position of A1 while moving at an inclination of 1/2 by the erasure discharge generated by the erasing ramp waveform (erase).

That is, after the erase discharge is completed, the wall charges are moved to the position of A1 as shown in FIG. 8. The wall charges of the cells in which the sustain discharge is not generated in the sustain period maintain the position of A2 in FIG. 8.

Thereafter, the rising ramp waveform Ramp-up is supplied to the scan electrodes Y. When the rising ramp waveform Ramp-up is supplied to the scan electrodes Y, the cell voltages of the discharge cells in which the discharge is generated in the sustain period of the previous subfield are moved from the point A1 through the surface discharge region of the three quadrants. Here, when the cell voltage passes through the surface discharge region of the third quadrant of the graph, the wall charges move with a slope of 1/2. Therefore, the wall charges located at the point of A1 are moved to the position of A3. And, since the cell voltage must be located within the voltage curve, it is dropped to the point C of the graph. Here, when the cell voltage is located at the vertex of the third quadrant (ie, point C), the wall charges move with a slope of one. Thus, the wall charges located at the point of A3 are moved to the point B with a slope of one.

On the other hand, when the rising ramp waveform Ramp-up is supplied to the scan electrodes Y, the cell voltages of the discharge cells in which the sustain discharge is not generated in the previous subfield are passed through the surface discharge region of the third quadrant from the point of A2 (that is, , Move to the Y (+) side). In this case, when the cell voltage passes through the surface discharge region of the third quadrant of the graph, the wall charges move with a slope of 1/2. Thus, the wall charges located at the point of A2 are moved to the position of A4. And, since the cell voltage must be located within the voltage curve, it is dropped to the point C of the graph. Here, when the cell voltage is located at the vertex of the third quadrant (ie, point C), the wall charges move with a slope of one. Thus, the wall charges located at the point of A4 are moved to the point B with a slope of one.

In fact, when the rising ramp waveform (Ramp-up) is supplied during the initialization period, the wall charges (area of 100) located in a straight line extending from the B curve to the slope and 1/2 of the voltage curve at point B as shown in FIG. It is gathered at B point. The wall charges 110 located on a straight line extending at a half slope from the point B to the voltage curve are collected in a line of L1 extending from the point B to the + Y axis. In addition, the wall charges 120 located below the straight line extending from the point B to the voltage curve 2 are collected in a line of L2 extending from the point B to the + X axis. That is, the wall charges of all the discharge cells converge to the point B, L1 and L2 due to the rising ramp waveform Ramp-up.

Thereafter, a falling ramp waveform Ramp-down falling from the rising ramp waveform Ramp-up is supplied to the scan electrodes Y. When the falling ramp waveform Ramp-down is supplied to the scan electrodes Y, the cell voltage positioned at the point C is moved to the point C1 as shown in FIG. Then, a positive voltage is applied to the sustain electrode Z when the falling ramp waveform Ramp-down falls with a slope. Then, the cell voltage located at the point C1 is moved to the point of C2. Then, since the ramp ramp down continues, the cell voltage is moved from the point of C2 through the surface discharge region of the first quadrant. Here, when the cell voltage passes through the surface discharge region of the first quadrant, the wall charges move at a slope of 1/2. Thus, the wall charges that were located at point B are moved to the position of A2. That is, when the ramp ramp down is supplied in the initialization period, the wall charges located at the point B are moved to the point A2 to initialize the discharge cells.

In fact, when the falling ramp waveform is supplied during the initialization period, the wall charges located in a straight line extending at a half slope and a slope of 2 from the point of A2 to the opposite discharge region of the first quadrant as shown in FIG. Are gathered to the point of. Thus, the wall charges located on the straight lines of point B and L1 converge to the point of A2. That is, when the falling ramp waveform (Ramp-down) is supplied, the wall charges located in the straight line of the point B and L1 are collected at the point of A2 to initialize the discharge cells.

However, in this conventional driving method, wall charges located in the straight line of L2 do not converge to the point of A2. Therefore, in the case of the discharge cells in which the wall charges are located in the region of 120 due to the process deviation (or the abnormal voltage) of the PDP, the wall charges are not initialized, and thus there is a problem in that the false discharge occurs.

In addition, since the conventional wall charges converge to the point of A2 via many movement paths as shown in FIG. 10, a high voltage must be applied during the initialization period. As such, when a high voltage is applied during the initialization period, a strong discharge is generated during the initialization period, and thus a lot of light is emitted to the outside.

Here, the light generated during the initialization period is to reduce the contrast to the light that does not contribute to the brightness. In addition, when a high voltage is applied during the initialization period, a lot of power consumption is consumed.

An object of the present invention, in order to solve the problem that the set-up voltage of the scan electrode is increased and the contrast is lowered as all light is driven in the existing three quadrants, the on-cell discharged during the initialization period is not discharged. SUMMARY OF THE INVENTION An object of the present invention is to provide a driving apparatus for a plasma display panel and a method of driving the same, which drive a non-off cell in a quadrant, thereby reducing black luminance and reducing an incidence of erroneous discharge.

The driving apparatus of the plasma display panel according to the present invention for achieving the above object comprises a plurality of scan electrodes and sustain electrodes; A sustain driver for driving the sustain electrode; And a scan driver configured to apply a pulse to the scan electrode to drive the discharged on cell and the non-discharged off cell to one quadrant during the initialization period.

The scan driver applies a negative first ramp pulse during the initialization period, applies a positive second ramp pulse subsequent to the first ramp pulse, and then applies a third ramp pulse subsequent to the negative ramp pulse. Characterized in that the application.

In this case, the first and third ramp pulses have a slope that falls from -230V to -240V at the base voltage.

In addition, the second ramp pulse is characterized by having a slope rising from the base voltage to 40V to 60V.

The scan driver may apply the fourth ramp pulse of positive polarity during the erase period before the initialization period, and apply the fifth ramp pulse of negative polarity following the fourth ramp pulse during the erase period.

At this time, the fifth ramp pulse is characterized in that it has a slope falling from the base voltage to -230V to -240V.

In addition, the present invention provides a method of driving an address electrode, a plasma display panel on which a scan electrode and a sustain electrode are formed by dividing an initialization period, an address period, a sustain period, and an erase period, respectively. And applying a pulse to the scan electrode to drive an on cell and an undischarged off cell in one quadrant.

The plasma display panel and the driving method thereof according to the present invention drive the discharged on-cell and the non-discharged off-cell in one quadrant during the initialization period, thereby reducing black luminance and reducing false discharge rates. It has a reducing effect.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention, in which the above object can be specifically realized, are described with reference to the accompanying drawings.

In the accompanying drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity.

On the other hand, when a part such as a layer, film, region, plate, etc. is formed or positioned on another part, it is formed directly on the other part and not only in direct contact but also when another part exists in the middle thereof. It should also be understood to include.

12 is a block diagram schematically illustrating an apparatus for driving a plasma display panel according to the present invention.

13 is a waveform diagram illustrating an exemplary driving waveform of the plasma display panel according to the present invention.

12 and 13, a driving apparatus of a plasma display panel (PDP) according to the present invention may include a data driver for supplying data to address electrodes X1 to Xm of a PDP. 32, a scan driver 33 for driving the scan electrodes Y1 to Yn, a sustain driver 34 for driving the sustain electrode Z which is a common electrode, and each driver 32, 33, 34 ) And a driving voltage generator 35 for supplying a driving voltage to each of the driving units 32, 33, and 34.

In addition, the PDP according to the present invention has an erase period for stabilizing the wall charge distribution, and for driving the discharged on cell and the non-discharged off cell in one quadrant after the erase period. The driving period is divided into an initialization period, an address period for performing cell selection after the initialization period, and a sustain period for initializing all cells in the second half, while maintaining the discharge of the cell after the address period.

The data driver 32 is supplied with data mapped to a subfield pattern preset by the subfield mapping circuit after inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like which are not shown.

The data driver 32 samples and latches data under the control of the timing controller 31, and then supplies the data to the address electrodes X1 to Xm.

The scan driver 33 has a positive polarity which rises from the base voltage GND to the sustain voltage Vs during the erase period on the scan electrode in order to more stabilize the wall charge distribution before the initialization period under the control of the timing controller 31. A ramp pulse Ramp1 is supplied, and a negative ramp pulse Ramp2 falling from the base voltage GND to the setdown voltage Vsetdown is supplied to the scan electrode following the ramp pulse Ramp1.

In this case, the negative ramp pulse Ramp2 has a slope falling from -230V to -240V at the base voltage.

In addition, the scan driver 33 drives the on-cell and the non-discharged off-cell that are discharged during the initialization period in one quadrant according to the present invention. A negative ramp pulse Ramp3 falling down to Vsetdown is applied to the scan electrode.

In this case, the ramp pulse Ramp3 has a slope that falls from -230 V to -240 V at the base voltage in the same manner as the ramp pulse Ramp2.

The scan driver 33 supplies the scan electrode with a positive ramp pulse Ramp4 rising from a base voltage to a setup voltage following the ramp pulse Ramp3.

At this time, the ramp pulse Ramp4 has a slope rising from the base voltage to 40V to 60V. In addition, the ramp pulse Ramp4 rises from the initial base voltage to the sustain voltage Vs, and then maintains the ramp pulse Ramp4 again to the setup voltage Vsetup.

In addition, the scan driver 33 applies a negative ramp pulse Ramp5 falling from the base voltage to the setdown voltage Vsetdown following the ramp pulse Ramp4 to the scan electrode.

In this case, the ramp pulse Ramp5 has a slope that falls from -230 V to -240 V at the base voltage in the same manner as the ramp pulse Ramp3.

The sustain driver 34 applies a base voltage to the sustain electrode while the scan driver 33 applies the Ramp1 pulse under the control of the timing controller 31, and while the scan driver 33 applies the Ramp2 pulse. The sustain voltage Vs is maintained.

The sustain driver 34 applies a positive DC voltage Vdc to the sustain electrode while the scan driver 33 applies the Ramp3 pulse, and a base voltage while the scan driver 33 applies the Ramp4 and Ramp5 pulses. Keep it.

The timing controller 31 receives a vertical / horizontal synchronization signal, generates a timing control signal required for each driver 32, 33, 34, and supplies the timing control signal to the corresponding driver 32, 33, 34. The driving units 32, 33, and 34 are controlled.

The timing control signal supplied to the data driver 32 includes a sampling clock for sampling data, a latch control signal, a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element.

The timing control signal applied from the timing controller 31 to the scan driver 33 includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the scan driver 33.

The timing control signal applied from the timing controller 31 to the sustain driver 34 includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the sustain driver 34.

The driving voltage generator 35 supplies a voltage corresponding to a pulse applied by each of the driving units 32, 33, and 34.

Hereinafter, the present invention will be described in detail with reference to FIGS. 14 to 20.

14 is a diagram showing the wall charge positions of the on-cell and off-cell during the sustain period.

FIG. 15 is a diagram illustrating a process of moving wall charges by Ramp3 shown in FIG. 13.

FIG. 16 is a diagram illustrating a process of converging wall charges by Ramp3 shown in FIG. 13.

17 is a diagram illustrating a process of moving wall charges by Ramp 4 shown in FIG. 13.

FIG. 18 is a diagram illustrating a process of converging wall charges by Ramp 4 shown in FIG. 13.

FIG. 19 is a diagram illustrating a process of moving wall charges by Ramp 5 shown in FIG. 13.

20 is a diagram illustrating a process of converging wall charges by Ramp 5 shown in FIG. 18.

Referring to FIGS. 14 to 20, referring to FIG. 18, the PDP according to the present invention includes an erase period for stabilizing wall charge distribution, an initialization period for initializing a full screen, an address period for selecting a cell, The driving is divided into a sustain period for maintaining the discharge of the selected cell.

Here, the driving waveform is only applied to the scan electrodes Y during the initialization period, and the driving waveform is not applied to the other electrodes Z and X. First, a negative Ramp3 is applied to all of the scan electrodes Y in the initialization period. Due to this Ramp3, minute discharge occurs in the discharge cells to move wall charges in the cell.

A process of generating a discharge when the Ramp3 is applied will be described in detail using a voltage curve Vt close curve.

First, after the sustain discharge is completed, the wall charges of the on-cells are located at the point E2, which is one quadrant of the voltage curve as shown in FIG. 14. (In this case, the erase pulse is applied in the previous subfield period so that the wall charges of the on-cells can be located at the E2 point. Not authorized)

The wall charges of the off-cells in which sustain discharge has not been generated in the previous subfield period are located at the point E1, which is the center region. )

Thereafter, Ramp3 is applied to the scan electrodes Y in the initialization period. When Ramp3 is applied to the scan electrodes Y, the cell voltages of the discharge cells in which the sustain discharge is not generated in the previous subfield are positioned in the voltage curve as shown in FIG. 15.

Therefore, even when Ramp3 is applied, the wall charges of the discharge cells in which the sustain discharge is not generated in the previous subfield maintain the position of E1.

On the other hand, when the Ramp3 is applied to the scan electrodes Y, the cell voltages of the discharge cells in which the sustain discharge is generated in the previous subfield are moved from the point E2 via the opposite discharge region of the first quadrant of the voltage curve.

Here, the wall charges move at a slope of 2 when they are moved through the opposite discharge region of the first quadrant of the cell voltage. Thus, the wall charges located at the point of E2 are moved to the point of E3 (the time when the cell voltage is moved to the vertex of the first quadrant) and when the cell voltage is located at the vertex of the first quadrant, the wall charges are at a slope of one. Move. Thus, the wall charges located at the point of E3 are moved to the position of E1 at a slope of one.

In fact, when the negative Ramp3 is supplied during the initialization period, the wall charges (area of the region 140) located in a straight line extending at a half slope and a slope of 2 from the point of E1 to the first quadrant of the voltage curve as shown in FIG. Converges to the point at E1.

The wall charges 144 located below the straight line extending at half the slope at the point of E1 converge to the straight line of L2 extending in the -Y axis from the point of E1.

Further, the wall charges 142 located on a straight line extending at a slope of 2 at the point of E1 converge to a straight line of L1 extending along the -X axis from the point of E1. That is, when negative electrode Ramp3 is supplied to the scan electrodes Y, the wall charges of the discharge cells converge to the point E1, the straight line of L1 and the straight line of L2.

On the other hand, after Ramp3 is applied to the scan electrodes Y, the voltage value is raised to the ground potential. Then, a positive Ramp4 that gradually rises from the base potential is applied to the scan electrodes (Y).

When Ramp 4 is applied to the scan electrodes Y, the cell voltage is shifted from the vertex of the first quadrant to the vertex of the third quadrant as shown in FIG. 17 (ie, the voltage rising to the ground potential GND + V5).

Here, when the cell voltage is moved to the vertex of the third quadrant, the wall charges move with the slope of one. Thus, the wall charges located at the point of E1 are moved to the position of E4.

In fact, when the positive Ramp4 is supplied during the initialization period, the wall charges located in the straight line extending from the point of E4 to the third quadrant of the voltage curve and the slope of 2 converge to the point of E4 as shown in FIG.

Then, the wall charges 152 located on the straight line extending to the half slope at the point of E4 converge to the straight line of L3 extending in the + Y axis from the point of E4.

In addition, the wall charges 154 located below the straight line extending at the slope of 2 at the point of E4 converge to the straight line of L4 extending from the point of E4 to the + X axis. That is, when the positive Ramp4 is supplied to the scan electrodes Y, the wall charges of the discharge cells converge to the point E4, the straight line of L3 and the straight line of L4.

After Ramp4 is applied to the scan electrodes Y, the voltage value drops to the base voltage.

After the voltage values of the scan electrodes Y are lowered to the base voltage, the negative electrode Ramp5 is applied to the scan electrodes Y.

When Ramp 5 is applied to the scan electrodes Y, the cell voltage is moved from the vertex of the third quadrant to the vertex of the first quadrant as shown in FIG. Here, when the cell voltage is moved to the vertex of the third quadrant, the wall charges move with the slope of one.

Thus, wall charges located at the point of E4 are moved to the position of E1.

In fact, when negative polarity Ramp5 is supplied during the initialization period, wall charges located in a straight line devoted to the first quadrant of the voltage curve at the point of E1 and the slope of 2 are converged to the point of E1 as shown in FIG. .

Therefore, the wall charges collected at the straight line of L3, the straight line of L4 and the point of E4 by Ramp4 all converge to the point of E1.

In the address period after the initialization period, the negative scan pulses are sequentially applied to the scan electrodes Y and the positive data pulses are applied to the address electrodes X.

As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, during the address period, the sustain electrodes Z are supplied with the positive DC voltage of the sustain voltage level Vs.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG.

Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs.

In the present invention, as shown in FIGS. 16, 18 and 20, all wall charges located in the voltage curve converge to the point of E1.

Therefore, in the present invention, by driving the on-cell and off-cell on one quadrant, erroneous discharge can be prevented and contrast can be improved.

It will be apparent to those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit and essential features of the present invention. For example, it will be very easy for those skilled in the art to use the above-described embodiments in combination with each other. Accordingly, the above detailed description should not be construed as limiting in all aspects and should be considered as illustrative. The scope of the invention should be determined by reasonable interpretation of the appended claims, and all changes within the equivalent scope of the invention are included in the scope of the invention.

1 is a perspective view illustrating a discharge cell structure of a conventional plasma display panel.

2 is a diagram illustrating an example of a luminance weight value of a subfield included in one frame.

3 is a waveform diagram showing a driving waveform applied to electrodes during a period of a subfield.

4 is a diagram showing the position of wall charges in a discharge cell in which address discharge has occurred.

FIG. 5 is a diagram illustrating a process in which a sustain discharge is generated when a sustain pulse is supplied to the wall charge shown in FIG. 4.

FIG. 6 is a diagram illustrating positions of wall charges formed by the sustain discharge of FIG. 5.

7 is a diagram illustrating a process of moving wall charges by erasing pulses.

FIG. 8 is a diagram illustrating a process in which wall charges are moved by the rising ramp waveform shown in FIG. 3.

FIG. 9 is a diagram illustrating a process in which wall charges converge by the rising ramp waveform shown in FIG. 3.

FIG. 10 is a view illustrating a process of moving wall charges by the falling ramp waveform shown in FIG. 3.

FIG. 11 is a diagram illustrating a process of converging wall charges by the falling ramp waveform shown in FIG. 3.

12 is a block diagram schematically illustrating an apparatus for driving a plasma display panel according to the present invention.

13 is a waveform diagram illustrating an exemplary driving waveform of the plasma display panel according to the present invention.

14 is a diagram showing the wall charge positions of the on-cell and off-cell during the sustain period.

FIG. 15 is a diagram illustrating a process of moving wall charges by Ramp3 shown in FIG. 13.

FIG. 16 is a diagram illustrating a process of converging wall charges by Ramp3 shown in FIG. 13.

17 is a diagram illustrating a process of moving wall charges by Ramp 4 shown in FIG. 13.

FIG. 18 is a diagram illustrating a process of converging wall charges by Ramp 4 shown in FIG. 13.

FIG. 19 is a diagram illustrating a process of moving wall charges by Ramp 5 shown in FIG. 13.

20 is a diagram illustrating a process of converging wall charges by Ramp 5 shown in FIG. 18.

Claims (12)

A plurality of scan electrodes and sustain electrodes; A sustain driver driving the sustain electrode; And And a scan driver configured to apply a pulse to the scan electrode to drive a discharged on cell and an undischarged off cell to one quadrant during an initialization period. The method of claim 1, wherein the scan driver, Applying a negative first ramp pulse during the initialization period, applying a second ramp pulse of positive polarity following the first ramp pulse, and applying a third ramp pulse of negative polarity following the second ramp pulse. A drive device for a plasma display panel. The method of claim 2, wherein the first and third ramp pulses, A driving device of a plasma display panel having a slope falling from -230V to -240V at a base voltage. The method of claim 2, wherein the second ramp pulse, And a slope rising from the base voltage to 40V to 60V. The method of claim 1, wherein the scan driver, And applying a fourth ramp pulse of positive polarity during the erasing period before the initialization period, and applying a fifth ramp pulse of negative polarity following the fourth ramp pulse during the erasing period. The method of claim 5, wherein the fifth ramp pulse, A driving device of a plasma display panel having a slope falling from -230V to -240V at a base voltage. In the method of driving the plasma display panel in which the address electrode, the scan electrode and the sustain electrode are formed, divided into an initialization period, an address period, a sustain period, and an erase period, respectively, And applying a pulse to the scan electrode for driving a discharged on cell and an undischarged off cell in one quadrant during the initialization period. The method of claim 7, wherein the applying step, Applying a negative first ramp pulse during the initialization period; Applying a second ramp pulse of positive polarity following the first ramp pulse; And And applying a third ramp pulse having a negative polarity following the second ramp pulse. The method of claim 8, wherein the first and third ramp pulses, And a slope falling from -230V to -240V at a base voltage. The method of claim 8, wherein the second ramp pulse, And a slope rising from 40V to 60V at the base voltage. The method of claim 7, wherein Applying a positive fourth ramp pulse to the scan electrode during an erase period prior to the initialization period; And And applying a fifth ramp pulse of negative polarity to the scan electrode after the fourth ramp pulse during the erasing period. The method of claim 11, wherein the fifth ramp pulse, And a slope falling from -230V to -240V at a base voltage.

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