KR20090059782A - Plasma display apparatus - Google Patents

Abstract

A plasma display apparatus is provided to increase the efficiency of an energy recovery circuit by oscillating before charge/discharge to/from a display panel. A first and a second electrode are formed on a top plate, and a third electrode is formed on a bottom plate. A driving unit supplies a driving signal to a plurality of electrodes, and the driving unit comprises an energy recovery circuit supplying a sustain signal to the first electrode. An energy recovery circuit comprises a source capacitor and an inductor, and source capacitor(C1,C2) recoveries energy from a first electrode and stores it. The inductor (L1,L2) comprises a resonance circuit with a source capacitor.

Description

Plasma display apparatus

The present invention relates to a plasma display device, and more particularly, to an energy recovery circuit for supplying a driving signal to a plasma display panel.

The plasma display panel (hereinafter referred to as PDP) displays an image by excitation and emitting phosphors by vacuum ultraviolet rays (VUV) generated when the inert gas is discharged.

Such a PDP is not only large in size and thin in thickness, but also has a simple structure and is easy to manufacture, and has a high luminance and high luminous efficiency compared to other flat display devices. In particular, the AC surface-discharge type 3-electrode plasma display panel has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge to protect the electrodes from sputtering caused by the discharge.

The plasma display panel is time-division driven by a reset period for initializing all cells, an address period for selecting cells, and a sustain period for causing display discharge in the selected cells in order to realize gray levels of an image. do.

In order for the driving circuit to supply driving signals to the plasma display panel, a large number of switching elements and clamping diodes are required, thereby increasing the cost and increasing the size due to the increase in the number of components, and in addition, the panel driving circuit due to the large number of circuit components. There is a problem that consumes a lot of power consumption.

The technical problem to be achieved by the present invention is to solve the above problems in the energy recovery circuit provided in the plasma display device, plasma with a highly reliable driving circuit that can reduce the manufacturing cost and increase the energy efficiency It is an object to provide a display device.

According to an aspect of the present invention, there is provided a plasma display apparatus comprising: a plasma display panel including first and second electrodes formed on an upper substrate, and a third electrode formed on a lower substrate; And a driving unit supplying driving signals to the plurality of electrodes, wherein the first energy recovery circuit for supplying a sustain signal to the first electrode comprises: a source capacitor for recovering and storing energy from the first electrode; And an inductor constituting a resonant circuit together with the source capacitor, wherein the current flowing through the inductor is changed while the voltage of the sustain signal supplied to the first electrode is maintained at a constant voltage.

According to the present invention configured as described above, when the driving signal is to be supplied to the plasma display panel using the energy recovery circuit, the efficiency of the energy recovery circuit is improved by generating resonance before charging and discharging the energy to the panel. At the same time, it is possible to improve the discharge characteristics of the panel, and to reduce the loss due to switching, thereby reducing the power consumed to drive the panel.

Hereinafter, an energy recovery circuit and a plasma display apparatus using the same will be described in detail with reference to the accompanying drawings. 1 is a perspective view illustrating an embodiment of a structure of a plasma display panel.

As shown in FIG. 1, the plasma display panel includes a scan electrode 11, a sustain electrode 12, a sustain electrode pair formed on the upper substrate 10, and an address electrode 22 formed on the lower substrate 20. It includes.

The sustain electrode pairs 11 and 12 generally include transparent electrodes 11a and 12a and bus electrodes 11b and 12b formed of indium tin oxide (ITO), and the bus electrodes 11b and 12b. 12b) may be formed of a metal such as silver (Ag) or chromium (Cr) or a stack of chromium / copper / chromium (Cr / Cu / Cr) or a stack of chromium / aluminum / chromium (Cr / Al / Cr). . The bus electrodes 11b and 12b are formed on the transparent electrodes 11a and 12a to serve to reduce voltage drop caused by the transparent electrodes 11a and 12a having high resistance.

Meanwhile, according to the exemplary embodiment of the present invention, the sustain electrode pairs 11 and 12 may not only have a structure in which the transparent electrodes 11a 12a and the bus electrodes 11b and 12b are stacked, but also the buses without the transparent electrodes 11a and 12a. Only the electrodes 11b and 12b may be configured. This structure does not use the transparent electrodes (11a, 12a), there is an advantage that can lower the cost of manufacturing the panel. The bus electrodes 11b and 12b used in this structure may be various materials such as photosensitive materials in addition to the materials listed above.

Light between the scan electrodes 11 and the sustain electrodes 12 between the transparent electrodes 11a and 12a and the bus electrodes 11b and 11c to absorb external light generated outside the upper substrate 10 to reduce reflection. A black matrix (BM, 15) is arranged that functions to block and to improve the purity and contrast of the upper substrate 10.

The black matrix 15 according to the exemplary embodiment of the present invention is formed on the upper substrate 10, the first black matrix 15 and the transparent electrodes 11a and 12a formed at positions overlapping the partition wall 21. And the second black matrices 11c and 12c formed between the bus electrodes 11b and 12b. Here, the first black matrix 15 and the second black matrices 11c and 12c, also referred to as black layers or black electrode layers, may be simultaneously formed and physically connected in the formation process, or may not be simultaneously formed and thus not physically connected. .

In addition, when physically connected and formed, the first black matrix 15 and the second black matrix 11c and 12c may be formed of the same material, but may be formed of different materials when they are formed separately.

The upper dielectric layer 13 and the passivation layer 14 are stacked on the upper substrate 10 having the scan electrode 11 and the sustain electrode 12 side by side. Charged particles generated by the discharge are accumulated in the upper dielectric layer 13, and the protective electrode pairs 11 and 12 may be protected. The protective film 14 protects the upper dielectric layer 13 from sputtering of charged particles generated during gas discharge, and increases emission efficiency of secondary electrons.

In addition, the address electrode 22 is formed in a direction crossing the scan electrode 11 and the sustain electrode 12. In addition, a lower dielectric layer 24 and a partition wall 21 are formed on the lower substrate 20 on which the address electrode 22 is formed.

In addition, the phosphor layer 23 is formed on the surfaces of the lower dielectric layer 24 and the partition wall 21. The partition wall 21 has a vertical partition wall 21a and a horizontal partition wall 21b formed in a closed shape, and physically distinguishes discharge cells, and prevents ultraviolet rays and visible light generated by the discharge from leaking into adjacent discharge cells.

In an embodiment of the present invention, not only the structure of the partition wall 21 illustrated in FIG. 1, but also the structure of the partition wall 21 having various shapes may be possible. For example, a channel in which a channel usable as an exhaust passage is formed in at least one of the differential partition structure, the vertical partition 21a, or the horizontal partition 21b having different heights of the vertical partition 21a and the horizontal partition 21b. A grooved partition structure having a groove formed in at least one of the type partition wall structure, the vertical partition wall 21a, or the horizontal partition wall 21b may be possible.

Here, in the case of the differential partition wall structure, the height of the horizontal partition wall 21b is more preferable, and in the case of the channel partition wall structure or the groove partition wall structure, it is preferable that a channel is formed or the groove is formed in the horizontal partition wall 21b. something to do.

Meanwhile, in one embodiment of the present invention, although the R, G and B discharge cells are shown and described as being arranged on the same line, it may be arranged in other shapes. For example, a Delta type arrangement in which R, G, and B discharge cells are arranged in a triangular shape may be possible. In addition, the shape of the discharge cell may be not only rectangular, but also various polygonal shapes such as a pentagon and a hexagon.

In addition, the phosphor layer 23 emits light by ultraviolet rays generated during gas discharge to generate visible light of any one of red (R), green (G), and blue (B). Here, an inert mixed gas such as He + Xe, Ne + Xe and He + Ne + Xe for discharging is injected into the discharge space provided between the upper / lower substrates 10 and 20 and the partition wall 21.

FIG. 2 illustrates an embodiment of an electrode arrangement of a plasma display panel, and a plurality of discharge cells constituting the plasma display panel are preferably arranged in a matrix form as shown in FIG. 2. The plurality of discharge cells are provided at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the address electrode lines X1 to Xn, respectively. The scan electrode lines Y1 to Ym may be driven sequentially or simultaneously, and the sustain electrode lines Z1 to Zm may be driven simultaneously. The address electrode lines X1 to Xn may be driven by being divided into odd-numbered lines and even-numbered lines, or sequentially driven.

Since the electrode arrangement shown in FIG. 2 is only an embodiment of the electrode arrangement of the plasma panel according to the present invention, the present invention is not limited to the electrode arrangement and driving method of the plasma display panel shown in FIG. 2. For example, a dual scan method in which two scan electrode lines among the scan electrode lines Y1 to Ym are simultaneously scanned is possible. In addition, the address electrode lines X1 to Xn may be driven by being divided up and down in the center portion of the panel.

3 is a timing diagram illustrating an embodiment of a time division driving method by dividing a frame into a plurality of subfields. The unit frame may be divided into a predetermined number, for example, eight subfields SF1, ..., SF8 to realize time division gray scale display. Each subfield SF1, ... SF8 is divided into a reset section (not shown), an address section A1, ..., A8 and a sustain section S1, ..., S8.

Here, according to an embodiment of the present invention, the reset period may be omitted in at least one of the plurality of subfields. For example, the reset period may exist only in the first subfield or may exist only in a subfield about halfway between the first subfield and all the subfields.

In each address section A1, ..., A8, a display data signal is applied to the address electrode X, and scan pulses corresponding to each scan electrode Y are sequentially applied.

In each of the sustain periods S1, ..., S8, a sustain pulse is alternately applied to the scan electrode Y and the sustain electrode Z to form wall charges in the address periods A1, ..., A8. Sustain discharge occurs in the discharge cells.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge periods S1, ..., S8 occupied in the unit frame. When one frame forming one image is represented by eight subfields and 256 gradations, each subfield in turn has different sustains at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128. The number of pulses can be assigned. In order to obtain luminance of 133 gradations, cells may be sustained by addressing the cells during the subfield 1 section, the subfield 3 section, and the subfield 8 section.

The number of sustain discharges allocated to each subfield may be variably determined according to weights of the subfields according to the APC (Automatic Power Control) step. That is, in FIG. 3, a case in which one frame is divided into eight subfields has been described as an example. However, the present invention is not limited thereto, and the number of subfields forming one frame may be variously modified according to design specifications. Do. For example, a plasma display panel may be driven by dividing one frame into eight or more subfields, such as 12 or 16 subfields.

The number of sustain discharges allocated to each subfield can be variously modified in consideration of gamma characteristics and panel characteristics. For example, the gray level assigned to subfield 4 may be lowered from 8 to 6, and the gray level assigned to subfield 6 may be increased from 32 to 34.

4 is a timing diagram illustrating an embodiment of driving signals for driving a plasma display panel with respect to the divided subfield.

The subfield is a wall formed by a pre-reset section and a pre-reset section for forming positive wall charges on the scan electrodes Y and negative wall charges on the sustain electrodes Z. A reset section for initializing the discharge cells of the entire screen using the charge distribution, an address section for selecting the discharge cells, and a sustain section for maintaining the discharge of the selected discharge cells.

The reset section includes a setup section and a setdown section. In the setup section, rising ramp waveforms (Ramp-up) are simultaneously applied to all scan electrodes to generate fine discharges in all discharge cells. Thus, wall charges are generated. In the set-down period, a falling ramp waveform (Ramp-down) falling at a positive voltage lower than the peak voltage of the rising ramp waveform (Ramp-up) is simultaneously applied to all scan electrodes (Y), thereby erasing discharge in all discharge cells. Is generated, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges.

In the address period, the negative scan signal scan is sequentially applied to the scan electrode, and at the same time, the data signal data having the positive voltage Va is applied to the address electrode X. The address discharge is generated by the voltage difference between the scan signal and the data signal and the wall voltage generated during the reset period, thereby selecting the cell. Meanwhile, a signal for maintaining a sustain voltage is applied to the sustain electrode during the set down period and the address period.

In the sustain period, a sustain pulse having a sustain voltage Vs is alternately applied to the scan electrode and the sustain electrode to generate sustain discharge in the form of surface discharge between the scan electrode and the sustain electrode.

The driving waveforms shown in FIG. 4 are exemplary embodiments of signals for driving the plasma display panel according to the present invention, and the present invention is not limited to the waveforms shown in FIG. 4. For example, the pre-reset period may be omitted, and the polarity and the voltage level of the driving signals illustrated in FIG. 4 may be changed as necessary. After the sustain discharge is completed, an erase signal for erasing wall charge may be applied to the sustain electrode. May be authorized. In addition, the single sustain driving may be performed by applying the sustain signal to only one of the scan electrode (Y) and the sustain (Z) electrode to generate a sustain discharge.

5 is a circuit diagram showing the configuration of an energy recovery circuit for supplying a sustain signal to the scan electrode and the sustain electrode of the plasma display panel.

Referring to FIG. 5, the energy recovery circuit includes source capacitors C ₁ and C ₂ , inductors L ₁ and L ₂ , suspension switches S ₁ and S ₂ , and susdown switches S ₃ and S ₄ . , Energy supply switches S ₅ and S ₆ and energy recovery switches S ₇ and S ₈ .

The source capacitors C ₁ and C ₂ recover energy from the panel Cp and store the energy. The inductors L ₁ and L ₂ are resonant with the capacitor Cp and the source capacitors C ₁ and C ₂ of the panel. And a energy supply / recovery switch (S ₅ , S _6, S ₇ , S ₈ ) is connected between the source capacitor (C ₁ , C ₂ ) and the inductor (L ₁ , L ₂ ) to supply energy and Each number is controlled. The source capacitors C ₁ and C ₂ recover and store the voltage charged in the panel during the sustain discharge, and re-supply the stored voltage to the panel when the sustain signal is supplied to the panel.

The panel capacitor Cp equivalently represents the capacitance formed between the scan electrode Y and the sustain electrode Z. FIG.

Suspend switches S ₁ and S ₂ are connected to a sustain voltage source Vs and turned on to supply a sustain voltage to the panel. Suspend switches S ₃ and S ₄ are connected to a reference voltage source to provide voltage to the panel. Turned on to lower to the reference voltage. As shown in FIG. 5, the reference voltage may be a ground voltage GND, and the reference voltage source to which the susdown switches S ₃ and S ₄ are connected may be ground.

An operation of the energy recovery circuit will be described in more detail with reference to the embodiment of the waveform of the sustain signal shown in FIG. 6.

Hereinafter, a case where the sustain signal is supplied to the scan electrode Y will be described as an example.

When the power of the entire plasma display device is turned on and a plurality of discharges are continuously generated in the panel, the discharge current of the panel is charged in the source capacitor C ₁ through the inductor L ₁ .

When the energy supply switch S ₅ is turned on in the energy supply section ER_up, the voltage charged in the source capacitor C ₁ is supplied to the scan electrode Y and thus is supplied to the scan electrode Y. The voltage of the sustain signal gradually rises.

Thereafter, when the sustain switch S ₁ is turned on in the sustain voltage sustain period SUS_up, the sustain signal supplied to the scan electrode Y maintains the sustain voltage Vs.

When the energy recovery switch S ₇ is turned on in the energy recovery section ER_dn, the energy charged in the scan electrode Y is recovered and charged to the source capacitor C ₁ through the inductor L ₁ . As a result, the voltage of the sustain signal supplied to the scan electrode Y gradually decreases.

Thereafter, when the susdown switch S ₃ is turned on in the reference voltage holding period SUS_dn, the voltage of the sustain signal supplied to the scan electrode Y is rapidly lowered and maintained to a reference voltage, for example, a ground voltage.

That is, in the energy supply step ER_up and the energy recovery step ER_dn, a resonance circuit formed by the source capacitor C ₁ , the capacitance Cp of the panel, and the inductor L ₁ is formed, and the source capacitor is formed by the resonance. Energy that has been charged in C ₁ is supplied to the scan electrode Y through the inductor L ₁ , or energy that has been charged in the scan electrode Y is recovered to the source capacitor C ₁ .

The energy recovery circuit supplies the sustain signal to the scan electrode Y while repeating the energy supply step ER_up to the reference voltage sustain step SUS_dn.

The sustain signal Z can also be supplied to the sustain electrode Z by the operation as described with reference to FIG. 6, and for this purpose, an energy recovery circuit for supplying the sustain signal to the scan electrode Y as shown in FIG. 5. And an energy recovery circuit for supplying a sustain signal to the sustain electrode Z are configured symmetrically with each other.

Hereinafter, the operation of the energy recovery circuit as shown in FIG. 5 will be described in more detail with reference to FIG. 7.

As shown in FIG. 7, a section in which energy is charged and discharged from the source capacitors C ₁ and C ₂ to the panel, that is, an energy supply / recovery section of the sustain signal supplied to the scan electrode Y and the sustain electrode Z. Resonance may occur only at (ER_up, ER_dn), and currents i _L1 and i _L2 flowing in the inductors L ₁ and L ₂ may change.

As described above, in order for the sustain signal to rise to the sustain voltage or fall to the reference voltage due to resonance occurring only in the energy supply / recovery periods ER_up and ER_dn, the energy supply / recovery periods ER_up and ER_dn must be sufficiently long. In such a case, the sustain voltage sustain period SUS_up is relatively short, and thus the sustain discharge efficiency of the panel may be reduced.

In addition, the switches S ₁ , S ₂ , S ₃ , The switch may be turned on in a state where the voltage between S ₄ , S ₅ , S ₆ , S ₇ , and S ₈ is not 0V, and power loss may occur due to switching.

The energy recovery circuit provided in the plasma display apparatus according to the present invention preferably generates resonance before the energy supply / recovery periods ER_up and ER_dn to change the current flowing through the inductor.

That is, by charging the inductor by increasing the current flowing through the inductor before the energy supply / recovery period (ER_up, ER_dn), the panel is used in the energy supply / recovery period (ER_up, ER_dn) by using the energy sufficiently charged in the inductor. Can improve the energy charging and discharging efficiency.

Hereinafter, an embodiment of an energy recovery circuit provided in the plasma display device according to the present invention will be described with reference to FIGS. 8 to 10.

FIG. 8 is a circuit diagram showing an embodiment of the configuration of the energy recovery circuit according to the present invention. The configuration of the energy recovery circuit shown in FIG. 8 is the same as that described with reference to FIGS. 5 to 7. It will be omitted.

Referring to FIG. 8, an energy recovery circuit according to an embodiment of the present invention may include source capacitors C ₁ and C ₂ , inductors L ₁ and L ₂ , suspension switches S ₁ and S ₂ , and susdown. And an ER switch (S ₅ , S ₆ ) that controls the recovery and supply of energy from the switches (S ₃ , S ₄ ) and the source capacitors (C ₁ , C ₂ ) to the panel.

As shown in FIG. 8, in the energy recovery circuit, a circuit unit for supplying a sustain signal to the scan electrode Y and a circuit unit for supplying the sustain signal to the sustain electrode Z are each provided with one ER switch S ₅ and S. ₆ ), the ER switches S ₅ and S ₆ may control energy supply and recovery from the source capacitors C ₁ and C ₂ to each electrode.

In addition, the ER switch (S ₅ , S ₆ ) may be connected in series with the suspend switch (S ₁ , S ₂ ), more preferably as shown in Figure 8 and the suspend switch (S ₁ , S ₂ ) It can be connected between the sustain voltage source (Vs), respectively.

Accordingly, the protection diode may be removed to prevent damage to the ER switches S ₅ and S ₆ generated by the parasitic resonance in the transient state as shown in FIG. 5.

The source capacitors C ₁ and C ₂ and the inductors L ₁ and L ₂ may be connected in series between both ends of the suspension switch S ₁ and S ₂ .

In addition, although the source capacitors C ₁ and C ₂ are connected to the connection nodes of the ER switches S ₅ and S ₆ and the suspend switches S ₁ and S _{2 in} FIG. 8, the connection nodes are connected to the nodes. Inductors L ₁ and L ₂ may be connected.

9 and 10 are timing diagrams for describing an operation of the energy recovery circuit shown in FIG. 8.

Referring to FIG. 9, the current i _L2 flowing in the inductor L ₂ is generated by generating resonance in the previous period t0 to t1 of the period ER_up and t1 to t2 for supplying energy to the sustain electrode Z. Can be increased. Accordingly, energy may be charged to the inductor L ₂ at the start of the periods ER_up and t1 to t2 for supplying energy to the sustain electrode Z, and the speed of energy charging to the sustain electrode Z may be increased. Can be improved.

As described above, the sustain voltage holding time of the sustain signal supplied to the sustain electrode Z can be increased by improving the energy charging speed to the sustain electrode Z, thereby stabilizing the sustain discharge of the panel and simultaneously discharging the sustain voltage. The efficiency can be increased.

In addition, in the previous sections t2 to t6 of the sections ER_dn and t6 to t7 for recovering energy from the sustain electrode Z, the current i _L2 flowing in the inductor L ₂ is decreased to reduce the energy recovery section ER_dn. , t6 to t7) can be reduced.

As described above, by reducing the energy recovery rate from the sustain electrode Z, the discharge characteristics of the panel can be improved and the energy recovery efficiency can be increased.

Similarly, the current i _L1 flowing in the inductor L ₁ is increased in the previous sections t9 to t10 of the sections ER_up and t10 to t11 for supplying energy to the scan electrode Z, thereby increasing the scan electrode Y. Can improve the rate of energy charging.

In addition, in the previous section (~ t3) of the sections ER_dn and t3 to t4 for recovering energy from the scan electrode Y, the current i _L1 flowing in the inductor L ₁ is decreased to reduce the energy recovery section (ER_dn, It is possible to reduce the energy charge rate at t3 ~ t4).

As shown in FIG. 9, the energy recovery periods ER_dn and t3 to t4 of the sustain signals supplied to the scan electrodes Z are supplied with energy supply sections ER_up and t1 to t2 of the sustain signals supplied to the sustain electrodes Z. ) Accordingly, the sustain voltage sustain period SUS_up of the two sustain signals may overlap in some periods t2 to t3, and the voltage Vp applied to the panel may be 0V during the partial periods t2 to t3. .

In addition, the energy recovery sections ER_dn and t6 to t7 of the sustain signal supplied to the sustain electrode Z may precede the energy supply sections ER_up and t10 to t11 of the sustain signal supplied to the scan electrode Z. Accordingly, the reference voltage sustain period SUS_dn of the two sustain signals may overlap in some periods t7 to t10, and the voltage Vp applied to the panel may be 0 V during the partial periods t7 to t10. .

As described above, the switches S ₁ , S ₂ , S ₃ , S ₄ , S ₅ , and S ₆ are turned on or off in the periods t2 to t3 and t7 to t10 where the voltage Vp applied to the panel is 0V. Thus, power loss due to switching can be reduced.

In addition, in order to effectively control the energy charge / discharge time to the scan electrode Y and the sustain electrode Z, respectively, as shown in FIG. The length and the length of the energy supply sections ER_up and t1 to t2 of the sustain electrode Z may be different, and the lengths of the energy recovery sections ER_dn and t3 to t4 of the scan electrode Z and the energy of the sustain electrode Z. The recovery periods ER_dn and t6 to t7 may be different in length.

To this end, the inductance of the inductor L ₁ on the scan electrode Y side and the inductance of the inductor L ₂ on the sustain electrode Z side are different, or the switching timing of the ER switches S ₅ , S ₆ is different. Can be adjusted differently.

Hereinafter, the operation of the energy recovery circuit shown in FIG. 8 will be described in more detail with reference to FIG. 10.

Before t0, the switches S1, S4 and S5 are turned on, so that the sustain voltage Vs is supplied to the scan electrode Y to the panel, and the current flowing through the inductor L1 decreases.

At time t0, the switch S6 is turned on so that the voltage difference between the sustain voltage Vs and the capacitor C2 is applied to the inductor L2, thereby increasing the current i _L2 flowing in the inductor L2.

At time t1, when the switch S4 is turned off, the voltage supplied to the sustain electrode Z increases to the sustain voltage Vs due to the resonance of the inductor L2 and the panel capacitance Cp, and accordingly the voltage Vp applied to the panel. And the voltage across the switch S2 is reduced to 0V. As a result, the switch S2 can be turned on while the voltage at both ends thereof is 0V.

At time t2, when the switch S2 is turned on, a negative voltage (-V ₂ ) is applied to the inductor L2 to reduce the current i _L2 flowing in the inductor L2.

When the switches S1 and S5 are turned off at the time t3, resonance occurs due to the inductor L1 and the panel capacitance Cp through the internal diode of the switch S5, and the voltage supplied to the scan electrode Y decreases, reaching the time t4. The voltage supplied to the scan electrode Y becomes 0V. Accordingly, at time t4, the switch S3 may be turned on while the voltage at both ends thereof is 0V.

In the period t4 to t6, the switches S2 and S6 are turned on, the current i _L2 flowing in the inductor L2 is decreased, and the voltage Vp applied to the panel can maintain -Vs.

At the time t6, when the switches S2 and S6 are turned off, resonance of the inductor L2 and the panel capacitance Cp occurs through the internal diode of the switch S6, so that the voltage supplied to the sustain electrode Z decreases, thereby t7 time. The voltage across the panel (Vp) increases to 0V. Therefore, at time t7, the switch S4 can be turned on with the voltage at both ends being 0V.

In the period t7 to t9, the current i _L2 flowing in the inductor L2 increases, and the voltage Vp applied to the panel may maintain 0V.

At time t9, when the switch S5 is turned on, the voltage difference between the sustain voltage Vs and the capacitor C1 is applied to the inductor L1 to increase the current i _L1 flowing in the inductor L1.

When the switch S3 is turned off at the time t10, resonance of the inductor L1 and the panel capacitance Cp occurs, and the voltage supplied to the scan electrode Y rises, and the voltage supplied to the scan electrode Y reaches t11 time. The voltage rises to the sustain voltage Vs.

At the time t11, since the voltage across the switch S1 becomes the zero voltage, the switch S1 can be turned on while the voltage between the both ends is 0V.

In the above, the energy recovery circuit according to the present invention has been described as an example. However, the present invention is not limited thereto, and the present invention is not limited thereto and may be used to generate driving signals supplied to various display panels such as LCD and OLED. Can be.

Although a preferred embodiment of the present invention has been described in detail above, those skilled in the art to which the present invention pertains can make various changes without departing from the spirit and scope of the invention as defined in the appended claims. It will be appreciated that modifications or variations may be made to the branches. Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

1 is a perspective view illustrating an embodiment of a structure of a plasma display panel.

2 is a cross-sectional view illustrating an embodiment of an electrode arrangement of a plasma display panel.

FIG. 3 is a timing diagram illustrating an embodiment of a method of time-divisionally driving a plasma display panel by dividing one frame into a plurality of subfields.

4 is a timing diagram illustrating an embodiment of driving signals for driving a plasma display panel.

5 is a circuit diagram showing a configuration of an energy recovery circuit for supplying a drive signal to a scan electrode or a sustain electrode of the plasma display panel.

6 and 7 are timing diagrams for describing an operation of the energy recovery circuit shown in FIG. 5.

8 is a circuit diagram showing an embodiment of the configuration of the energy recovery circuit according to the present invention.

9 and 10 are timing diagrams for describing an operation of the energy recovery circuit shown in FIG. 8.

Claims (17)

A plasma display panel including first and second electrodes formed on the upper substrate and third electrodes formed on the lower substrate; And a driving unit supplying a driving signal to the plurality of electrodes. The driving unit includes a first energy recovery circuit for supplying a sustain signal to the first electrode, the first energy recovery circuit includes a source capacitor for recovering and storing energy from the first electrode; And an inductor constituting a resonant circuit together with the source capacitor, And a current flowing through the inductor changes while the voltage of the sustain signal supplied to the first electrode is maintained at a constant voltage. The method of claim 1, The sustain signal may include a first section rising to a first voltage, a second section maintaining the first voltage, a third section falling from the first voltage to a second voltage, and a fourth section maintaining the second voltage. Plasma display device comprising a. The method of claim 2, And at least a portion of the second period of the current flowing through the inductor decreases. The method of claim 2, And a current flowing through the inductor increases in at least a portion of the fourth section. The method of claim 2, And a current flowing in the inductor at a start time of at least one of the first and third sections is greater than zero. The method of claim 1, wherein the first energy recovery circuit is A first switch turned on to supply a sustain voltage to the first electrode; A second switch turned on to supply a reference voltage to the first electrode; And And an ER switch connected in series with the first switch to control energy supply and recovery from the source capacitor to the first electrode. The method of claim 6, And the ER switch is connected between the first switch and a sustain voltage source. The method of claim 6, And the inductor or the source capacitor is connected to a node to which the first switch and the ER switch are connected. The method of claim 6, And the source capacitor and the inductor connected in series are connected between both ends of the first switch. The method of claim 6, And the first switch and the third switch are turned on simultaneously in at least a portion of the section in which the sustain signal maintains the sustain voltage. The method of claim 6, And at least a portion of the period in which the sustain signal maintains the reference voltage, wherein the second switch and the third switch are turned on at the same time. The method of claim 6, And the first and second switches are turned on when the voltages supplied to the first and second electrodes are substantially the same. The method of claim 1, The driving unit further includes a second energy recovery circuit for supplying a sustain signal to the second electrode, And inductance values of the inductors included in the first and second energy recovery circuits are different from each other. The method of claim 1, The first and second sustain signals supplied to the first and second electrodes, respectively, may include a first section rising up to a first voltage, a second section maintaining the first voltage, and a first drop down from the first voltage to a second voltage. A third section and a fourth section maintaining the second voltage, And the first section of the first sustain signal precedes the fourth section of the second sustain signal. The method of claim 1, The first and second sustain signals supplied to the first and second electrodes, respectively, may include a first section rising to a first voltage, a second section maintaining the first voltage, and a first dropping from the first voltage to a second voltage. A third section and a fourth section maintaining the second voltage, And at least a portion of the second section of the first and second sustain signals overlap each other. The method of claim 1, The first and second sustain signals supplied to the first and second electrodes, respectively, may include a first section rising to a first voltage, a second section maintaining the first voltage, and a first dropping from the first voltage to a second voltage. A third section and a fourth section maintaining the second voltage, And at least a portion of the fourth section of the first and second sustain signals overlapping each other. The method of claim 1, The first and second sustain signals supplied to the first and second electrodes, respectively, may include a first section rising to a first voltage, a second section maintaining the first voltage, and a first dropping from the first voltage to a second voltage. A third section and a fourth section maintaining the second voltage, The plasma display apparatus of claim 1, wherein the lengths of at least one of the first and third sections are different from each other.

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