KR20090058235A - Test pattern for semiconductor device, method for facturing the pattern, and method for testing the device - Google Patents

Abstract

A test pattern for as semiconductor device, a method for manufacturing the pattern and testing the device are provided to cut down the time to be required to test by testing the fault of the contact connected to the gate, the source and drain region, and metal wiring simultaneously. A first contact is connected to source and drain region(380) formed in the active region. A second contact(332) is connected to the gate and is formed near the first contact. The first contact and the second contact form an alternative chain. A gate pattern(310) is formed between the source/drain pattern formed in active region. The first contact(330) and the second contact belonging to gate patterns(312) are arranged as the neighboring chain type belongs to active areas(382,384). The first contact and the second contact(322) are connected through the metal wiring(350).

Description

Test pattern for semiconductor device, method for facturing the pattern, and method for testing the device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices such as various transistors, CMOS (Complementary Metal Oxide Semiconductor) image sensors, or memories, and more particularly, to a test pattern of a semiconductor device, a method of forming the same, and a test method thereof.

When problems arise in the current semiconductor device chip, various test (or monitoring) patterns are added to determine whether the problem is the unit device constituting the chip or the metal wiring connecting them. use. Since the problem in the chip is mainly a metal wiring problem, each of the contacts connected to the metal wiring is tested through a test pattern.

However, in order to implement more chips in a smaller area, the gate length and the area of the source and drain regions are getting smaller, and as a result, the area of the contact connected to the gate, the source and the drain regions is also smaller. Whether the problem in the chip is the contact connected to the gate or the contact connected to the source and drain regions is tested separately. This general test pattern and its test method will be described with reference to the accompanying drawings as follows.

1A and 1B show a plan view and a cross-sectional view for explaining an example of a test pattern of a general semiconductor device, respectively. FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. 1A. 2A and 2B show a plan view and a cross-sectional view, respectively, for explaining another example of a test pattern of a general semiconductor device. FIG. 2B is a cross-sectional view taken along line BB ′ in FIG. 2A.

1A and 1B, the semiconductor substrate 120 is defined as an active area (AA) and an isolation region, and includes source and drain regions and contacts 102 formed in the active area 100. ) Is connected and formed. An isolation layer 108 is formed in the isolation region. Here, each active region 100 is provided with two contacts 102, and the contacts of neighboring active regions 100 are connected to each other by metal wires 104.

When the test pattern is to be tested using the test pattern illustrated in FIGS. 1A and 1B, the current 110 flowing through the contacts 104 and the metal wiring 104 is measured, and the measured current is analyzed to determine the contact 102. And defects of the metal wiring 104 can be tested.

2A and 2B, the semiconductor substrate 220 is defined as an active region 216 and an isolation region, and the contact 202 of the gate pattern 200 is connected to the gate 210 in the active region 216. Connected. A gate insulating layer 214 may be provided between the gate 210 and the semiconductor substrate 220, and spacers 212 may be formed on both sides of the gate 210. Here, each gate pattern 200 The two contacts 202 are provided, and the contacts of the neighboring gate pattern 200 are connected to each other by the metal wiring 204.

When the test pattern is to be tested using the test patterns illustrated in FIGS. 2A and 2B, the current 230 flowing through the contacts 202 and the metal wires 204 is measured, and the measured currents are analyzed to determine the contacts 202. And defects of the metal wiring 204 can be tested.

In the general test pattern and the test method described above, the pattern for testing the contact 202 connected to the gate 202 and the metal wiring 204 connected to the contact 202 and the source and drain regions 130 Since the pattern for testing the contact 102 and the metal wiring 104 connected to the contacts 102 exists separately, the total area occupied by the test pattern is large. In addition, since these are separately tested, there is a problem that it takes a long time to determine the failure of the semiconductor device from the test results.

SUMMARY OF THE INVENTION The present invention provides a test pattern of a semiconductor device capable of simultaneously testing a defect of a contact connected to a source and a drain region, a defect of a contact connected to a gate, and a defect of a metal wiring connecting the contacts, and the like. To provide a test method.

Another object of the present invention is to provide a test forming method of a semiconductor device for forming the test pattern.

The test pattern of the semiconductor device according to the present invention for achieving the above object is connected to the first contact and the gate connected to the source and drain regions formed in the active region on the semiconductor substrate defined by the active region and the device isolation region, It is preferable that the second contact is formed adjacent to the first contact and the metal wiring connecting the first contact and the second contact.

Alternatively, on a semiconductor substrate defined as an active region and an isolation region, a first contact connected to a source and a drain region formed in the active region, a second contact connected to a gate and formed adjacent to the first contact, and the first contact According to an exemplary embodiment of the present invention, a test method of a semiconductor device using a test pattern having a metal wiring connecting a second contact with the second contact includes: measuring a current flowing between the first contact and the second contact connected through the metal wiring; Preferably, the measured current is used to test at least one of a failure of the first or second contact itself and a connection failure of the metal wire.

According to another aspect of the present invention, there is provided a test forming method of a semiconductor device, the method including: forming a first contact connected to a source and a drain region formed in the active region on a semiconductor substrate defined as an active region and an isolation region; And forming a second contact adjacent to the first contact and forming a metal wire connecting the first contact and the second contact to the gate.

According to the present invention, a test pattern of a semiconductor device, a method of forming the same, and a test method thereof may be performed by testing a defect of a contact connected to a gate, a defect of a contact connected to a source and a drain region, and a defect of a metal wiring connected between the contacts in a separate pattern. Compared to the general method of increasing the test time and increasing the area occupied by the test pattern, it is possible to simultaneously test the defect of the contact connected to the gate, the defect of the contact connected to the source and drain regions, and the defect of the metal wiring. It saves time, reduces the number of test patterns, reduces the area occupied by the test patterns, so that other test patterns can be added, and various gates to which a contact is connected can be formed on the device isolation region or the active region. The part used as a dummy area can be utilized. By reducing the area occupied by the test pattern, the area of the gate pattern and the active area (or the source / drain pattern) can be variously implemented to allow margin evaluation of contact processing. Have

Hereinafter, embodiments of a test pattern of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

3A and 3B show a plan view and a cross-sectional view, respectively, of a test pattern according to an embodiment of the present invention. 3B is a cross-sectional view taken along line C-C 'shown in FIG. 3A.

4A and 4B show a plan view and a cross-sectional view, respectively, of a test pattern according to another embodiment of the present invention. 4B is a cross-sectional view taken along line D-D 'of FIG. 4A.

3B and 4B, the semiconductor substrates 360 and 460 are defined as active regions and device isolation regions. As in the structure of a general semiconductor device, a gate insulating film 370 or 470, a gate 372 or 472, and a spacer 374 or 474 are formed. The device isolation layer 320 or 480 is formed in the device isolation region. In the exemplary embodiment illustrated in FIGS. 3A and 3B, the gate insulating layer 370, the gate 372, and the spacer 374 are formed on the device isolation layer 320. However, as in the embodiment shown in FIGS. 4A and 4B, the gate insulating film 470, the gate 472, and the device isolation film 474 may be formed in the active region.

The first contact 330 or 430 is connected to the source and drain regions 380 or 420 formed in the active region. The second contact 332 or 432 is connected to the gate 372 or 472 and is formed adjacent to the first contact 330 or 430. In this case, as shown in FIGS. 3A to 4B, the plurality of first contacts 330 or 430 may be alternately formed with a plurality of second contacts 332 or 432 in the form of a chain. Can be. That is, referring to FIGS. 3A and 3B, the gate pattern 310 is formed between the source / drain patterns 380 and 382 formed in the active regions, and the gate is formed between the source / drain patterns 382 and 384. The pattern 312 is formed, and it can be seen that the source / drain pattern and the gate pattern are alternately arranged in a chain shape alternately. Therefore, the first contact 330 belonging to the active regions 380, 382, and 384 and the second contact 332 belonging to the gate patterns 310 and 312 are arranged in a neighboring chain shape. 4A and 4B, a gate pattern 410 is formed between the source / drain patterns 420 and 422 formed in the active region, and a gate is formed between the source / drain patterns 422 and 424. The pattern 412 is formed, and it can be seen that the source / drain pattern and the gate pattern are alternately arranged in a chain shape. Accordingly, the first contact 430 belonging to the source / drain patterns 420, 422, and 424 and the second contact 432 belonging to the gate patterns 410 and 412 are arranged in a neighboring chain shape.

According to an embodiment of the present invention, the test pattern may have only one source / drain pattern 380 or 420 and one gate pattern 310 or 410.

According to another embodiment of the present invention, as shown in Figures 3a and 3b, the test pattern is a plurality of source / drain patterns 380, 382 and 384 and a plurality of gate patterns 310 staggered in a chain form with each other And 312). In addition, as illustrated in FIGS. 4A and 4B, the test pattern may have a plurality of source / drain patterns 420, 422, and 424 and a plurality of gate patterns 410 and 412 that are alternately formed in a chain form.

Meanwhile, as shown in FIGS. 3A to 4B, the metal wires 350 or 450 are formed to connect adjacent contacts with each other.

Hereinafter, a test method of a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

5 is a flowchart for explaining a test method of a semiconductor device according to the present invention.

First, referring to FIG. 3A, the current 340 flowing between the first contact 330 and the second contact 322 connected through the metal wire 350 is measured (operation 500).

After operation 500, the measured current is used to test at least one of a failure of the first or second contact 330 or 332 itself and a connection failure between the metal wire 350 and the contact 330 or 332 (operation 510). step). For example, the measured current may be converted into a resistance value of a path in which the first and second contacts and the metal wire are connected, and the defect may be tested using the converted resistance value. That is, from the upper first contact of the two first contacts belonging to the source / drain pattern 380 shown in FIG. 3A, the lower first of the two first contacts belonging to the source / drain pattern 384. The resistance of the path to the contact may be used to test the failure of all the first and second contacts 330 and 332 and all the metal wires 350 shown in FIG. 3A.

Alternatively, referring to FIG. 4A, a current 440 flowing between the first contact 430 and the second contact 432 connected through the metal wire 450 is measured (operation 500).

After the 500 th step, at least one of the failure of the first or second contact 430 or 432 itself, the connection between the metal wire 450 and the contact, and the failure of the metal wire 450 itself are measured using the measured current. Test (step 510). For example, the measured current may be converted into a resistance value of a path in which the first and second contacts and the metal wire are connected, and the defect may be tested using the converted resistance value. That is, the first contact below one of the two first contacts belonging to the source / drain pattern 424 from the upper first contact among the two first contacts belonging to the source / drain pattern 420 illustrated in FIG. 4A. By using the resistance value of the path up to the failure of all the first and second contacts 430 and 432 and all metal wiring 450 shown in Figure 4a can be tested.

According to the present invention, various areas of the gate patterns 310, 312, 410, and 412 and the source / drain patterns 380, 382, 384, 420, 422, and 424 shown in FIGS. 3A through 4B may be realized. have. For this reason, this invention can also evaluate margin for contact processing.

In addition, the test pattern may be implemented in the same manner as an element configured in an array form. That is, at least one layer may be stacked in an array form on the top of the cross-section illustrated in FIG. 3B or 4B, in which case each layer is formed in an interlayer insulating film (not shown) and contact sequentially from the bottom to the top. (Not shown) and metal wiring (not shown).

This makes it easier to find the point of vulnerability and problems when it occurs. For example, first, a test of the cross section shown in FIG. 3B or 4B is used to test whether the cross section is defective. If it is determined through the test results that the cross section is a defect, it is possible to determine the failure of the semiconductor device without having to test whether the other layer stacked on top of the cross section.

Hereinafter, a test pattern forming method of a semiconductor device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

6 is a flowchart illustrating a test pattern forming method of a semiconductor device according to an embodiment of the present invention.

First, a gate 372 or 472 is formed (step 600). That is, as shown in FIG. 3B, a trench is formed in the semiconductor substrate 360, an insulating material is embedded in the trench to form the device isolation layer 320, and then the gate insulating layer 370 is formed on the device isolation layer 320. The gate 372 and the spacer 374 are sequentially formed. Thereafter, the source and drain regions 380 are formed by implanting impurity ions into the active regions between the device isolation layers 320. In addition, as shown in FIG. 4B, a trench is formed in the semiconductor substrate 460, an insulating material is embedded in the trench to form the device isolation film 480, and then a gate insulating film is formed in the active region between the device isolation films 480. 474, the gate 472, and the spacer 474 are sequentially formed. Thereafter, before or after forming the spacer 474, impurity ions are implanted into the active region by using the gate 472 and / or the spacer 474 as an ion implantation mask to form the source and drain regions 420, 422, and 424. To form. Since the process of forming the gate insulating film 370 or 470, the gate 372 or 472, and the spacer 374 or 474 is general, detailed description is abbreviate | omitted.

3A and 3B, on a semiconductor substrate defined as an active region and an isolation region, source / drain patterns 380, 382, and 384 corresponding to source and drain regions formed in the active region may be described. In operation 610, the first contact 330 is formed. 4A and 4B, on a semiconductor substrate defined as an active region and an isolation region, a first contact 430 may be formed on source / drain patterns 420, 422, and 424 corresponding to source and drain regions formed in the active region. ) (Step 610).

After operation 610, the gate 372 or 472 is connected to form a second contact 332 or 432 adjacent to the first contact 330 or 430 (operation 620). According to the present invention, as illustrated in FIGS. 3A to 4B, a plurality of first contacts 330 or 430 are formed, and the second contacts 332 or 332 are alternately formed in a chain form with the first contacts 330 or 430. A plurality of 432 is formed.

After operation 620, the metal wire 350 or 450 connecting the neighboring first contact 330 or 430 and the second contact 332 or 432 is formed (operation 630).

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1A and 1B show a plan view and a cross-sectional view for explaining an example of a test pattern of a general semiconductor device, respectively.

2A and 2B show a plan view and a cross-sectional view, respectively, for explaining another example of a test pattern of a general semiconductor device.

3A and 3B show a plan view and a cross-sectional view, respectively, of a test pattern according to an embodiment of the present invention.

4A and 4B show a plan view and a cross-sectional view, respectively, of a test pattern according to another embodiment of the present invention.

5 is a flowchart for explaining a test method of a semiconductor device according to the present invention.

6 is a flowchart illustrating a test pattern forming method of a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

360, 460: semiconductor substrate 320, 420: device isolation film

330, 430: first contact 332, 432: second contact

350, 450: metal wiring

Claims (9)

A first contact connected to a source and a drain region formed in the active region on a semiconductor substrate defined as an active region and an isolation region; A second contact connected to the gate and formed adjacent to the first contact; And And a metal wiring connecting the first contact and the second contact. The test pattern of a semiconductor device according to claim 1, wherein said gate is formed in said active region. The test pattern of a semiconductor device according to claim 1, wherein the gate is formed in the device isolation region. The test pattern of claim 1, wherein the plurality of first contacts are alternately formed in a chain form with the plurality of second contacts, and the metal wires connect neighboring contacts to each other. On a semiconductor substrate defined as an active region and an isolation region, a first contact connected to a source and a drain region formed in the active region, a second contact connected to a gate and formed adjacent to the first contact, and the first contact and the In the test method of a semiconductor device using a test pattern having a metal wiring for connecting the second contact, Measuring a current flowing between the first contact and the second contact connected through the metal wire; And And testing at least one of a failure of the first or second contact itself and a failure of a connection of the metal wiring by using the measured current. Forming a first contact on a semiconductor substrate defined by an active region and an isolation region, the first contact being connected to a source and a drain region formed in the active region; Forming a second contact coupled to the gate and adjacent to the first contact; And And forming a metal line connecting the first contact and the second contact. The method of claim 6, wherein the test pattern forming method is And forming the gate in the active region. The method of claim 6, wherein the test pattern forming method is And forming the gate in the device isolation region. The metal wire of claim 6, wherein the first contact is formed in plural, the second contact is formed in plural alternately with the first contact, and the metal wiring is formed to connect the adjacent contacts to each other. The test pattern formation method of a semiconductor device characterized by the above-mentioned.

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