KR20090051944A - Method of fabricating array substrate for liquid crystal display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a liquid crystal display (COT) structure, in which a color filter is formed on the same substrate as a thin film transistor (TFT). It is about.

According to the present invention, an island-shaped semiconductor layer (particularly an active layer) is formed on the gate electrode without increasing the mask process compared with the conventional method for manufacturing an array substrate for a COT structure liquid crystal display device. By eliminating the semiconductor layer, it is possible to solve problems such as leakage current and wave noise, and to increase the width of the black matrix to cover the semiconductor layer protruding from the data wiring. It is possible to provide a substrate.

In addition, the source and drain electrodes may be configured as a double layer to improve ohmic contact characteristics with a lower semiconductor layer.

COT, wave noise, leakage current

Description

Manufacturing Method of Array Substrate for Liquid Crystal Display Device {Method of Fabricating Array Substrate for Liquid Crystal Display Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a liquid crystal display (COT) structure, in which a color filter is formed on the same substrate as a thin film transistor (TFT). It is about.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, an active matrix liquid crystal display device (AM-LCD: below Active Matrix LCD, abbreviated as liquid crystal table market value), in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner, has the best resolution and video performance. It is attracting attention.

The liquid crystal display includes an upper substrate on which color filters, a common electrode, etc. are formed, a lower substrate on which switching elements, pixel electrodes, etc. are formed, and a liquid crystal interposed between the two substrates. It is excellent in characteristics such as transmittance and aperture ratio in such a manner that the liquid crystal is driven by an electric field applied up and down.

In addition, a technique for forming a color filter and a switching element formed on each of the upper and lower substrates on the same substrate has been proposed. This is a so-called COT (Color filter On TFT) structure, in which a color filter is formed on the lower substrate on which the switching element is formed. This aims to improve the aperture ratio by reducing the bonding margin considered in the process of bonding the upper and lower substrates.

A conventional COT structure liquid crystal display device will be described with reference to FIGS. 1 and 2 below.

1 is a plan view illustrating an array substrate of a COT structure hierarchical liquid crystal display device according to the related art.

As illustrated, the array substrate 10 of the COT structure liquid crystal display device is formed on the transparent substrate 12 while the gate wiring 14 and the data wiring 30 cross each other to define the pixel region P. The thin film transistor T is formed at the intersection of the gate wiring 14 and the data wiring 30. The thin film transistor T includes a gate electrode 16 semiconductor layer 24, and a source electrode 32 and a drain electrode 34 spaced apart from each other. The semiconductor layer 24 is formed under the source and drain electrodes 32 and 34 and the data line 30, and an active layer (not shown) of the semiconductor layer 24 is a source and drain electrode 32 due to the manufacturing process. 34 and the data line 30 protrude from each other. That is, the active layer (not shown) has a width wider than the widths of the source and drain electrodes 32 and 34 and the data line 30, which causes problems such as leakage current, wave noise, and aperture ratio reduction. The detailed reason is explained with reference to FIGS. 2A to 2G, which illustrate the manufacturing process.

In the pixel region P, a pixel electrode 50 connected to the drain electrode 34 of the thin film transistor T and the first contact hole CH1 is formed. The pixel electrode 50 overlaps the gate wiring 14 of the front end, and has an arrangement in which an island-shaped metal pattern 36 formed below the second electrode hole 36 is connected to the pixel electrode 36. Capacitor Cst is configured. Color filters R, G, and B having any one of red, green, and blue colors are formed in each pixel area P, thereby forming a COT structure liquid crystal display array substrate 10.

As described above, since the color filter, which is usually formed on the upper substrate, is formed on the lower substrate together with the thin film transistor, which is a switching element, due to the characteristics of the COT structure, the upper substrate generally includes a black matrix to cover a non-display area such as a thin film transistor and a pixel electrode. Only the common electrode forming the electric field together with 50 is formed.

2A to 2G are cross-sectional views of manufacturing processes of portions cut along the line II-II of FIG. 1.

In the case of the COT structure in which the color filter is formed on the lower substrate, the number of mask processes is inevitably increased due to the process for forming the color filter. It is formed by the mask process of, which is shown in Figures 2a to 2g.

2A shows a first mask process. As shown, the gate wiring 14 is formed on the substrate 12 by forming a first metal layer (not shown) on the substrate 12 and patterning the first metal layer (not shown) by the first mask process. And a gate electrode 16 connected thereto. The pixel region P on which the pixel electrode is positioned and becomes an image display area on the substrate 12 is defined, the switching region S on which a thin film transistor serving as a switching element is to be formed, and the capacitor region C on which a storage capacitor is to be defined. It is. Therefore, the gate electrode 16 is formed in the switching region S, and the gate wiring 14 is formed in the capacitor region C along the boundary of the pixel region P. As shown in FIG. The gate insulating film 18 is formed on the entire surface of the substrate 12, covering the gate electrode 16 and the like.

2B-2D show a second mask process.

As shown in FIG. 2B, the pure amorphous silicon layer 20, the impurity amorphous silicon layer 21, and the second metal layer 22 are sequentially stacked on the gate insulating film 18, and a photoresist layer is formed on the gate insulating film 18. The material is applied to form a photoresist layer (not shown). The mask M having the transmissive part TA, the transflective part HTA, and the blocking part BA is positioned on the photoresist layer (not shown). Here, the transflective portion HTA is smaller than the transmissive portion HT and has a transmittance larger than the cutoff portion BA. By exposing and developing the photoresist layer (not shown) using the mask M including the transflective portion HTA as described above, the first and second thicknesses t1 and t2 are respectively provided, and the blocking portions BA are respectively. ) And the first and second photoresist patterns 72a and 72b at positions corresponding to the transflective portion HTA. The first photoresist pattern 72a is formed in the switching region S and the capacitor region C, and has a second thickness t2 smaller than the first thickness t1 of the first photoresist pattern 72a. The two photoresist pattern 72b is formed corresponding to the center portion of the switching region S, that is, the gate electrode 16. Outside of the first and second photoresist patterns 72a and 72b, all of the photoresist layers (not shown) are removed to correspond to the transmission portion TA of the mask M to expose the second metal layer 22.

Next, as shown in FIG. 2C, the second metal layer (22 of FIG. 2B) exposed to the outside of the first and second photoresist patterns (72a and 72b of FIG. 2B) and the impurity amorphous silicon layer below it (FIG. 2B). 21) and the pure amorphous silicon layer (20 of FIG. 2B) are sequentially removed, thereby sequentially depositing the first pure amorphous silicon pattern 20a, the first impurity amorphous silicon pattern 21a, and the first One metal pattern 22a is formed on the gate insulating film 18. At the same time, the second pure amorphous silicon pattern 20b, the second impurity amorphous silicon pattern 21b, and the second metal pattern 22b sequentially stacked on the capacitor region C are formed on the gate insulating film 18. Therefore, the gate insulating film 18 is exposed to the outside in the region where the first and second photoresist patterns 72a and 72b of FIG. 2B are not formed.

Then, the ashing process is performed on the first and second photoresist patterns (72a and 72b of FIG. 2B), and the second photoresist pattern (72b of FIG. 2B) having the second thickness is removed to remove the gate electrode. The first metal pattern 22a corresponding to (16) is exposed. At the same time, the first photoresist pattern 72b of FIG. 2B is also ashed to form a third photoresist pattern 72c having a third thickness t3. At this time, since the ashing process is also performed at the end of the first photoresist pattern 72b of FIG. 2B, the first and second metal patterns 22a and 22b are exposed around the third photoresist pattern 72c. .

Next, as illustrated in FIG. 2D, the source metals 32 spaced apart from each other by removing the exposed first metal pattern 22a of FIG. 2C corresponding to the gate electrode 16 in the switching region S. Referring to FIG. And forming the drain electrode 34 and removing the first impurity amorphous silicon pattern (21a in FIG. 2C) using the source and drain electrodes 32 and 34 as masks, thereby removing the first pure amorphous silicon pattern (Fig. 2c of 20a) is exposed. Here, the first impurity amorphous silicon pattern (21a of FIG. 2C) is removed to form an ohmic contact layer 24b spaced apart from each other under the source and drain electrodes 32 and 34, and the first pure amorphous silicon pattern (FIG. 20c of 2c is exposed between the ohmic contact layer 24b to become the active layer 24a in which the channel region is defined. The ohmic contact layer 24b and the active layer 24a constitute a semiconductor layer 24. That is, in the switching region S, the semiconductor layer 24 including the gate electrode 16, the gate insulating film 18, the active layer 24a and the ohmic contact layer 24b, the source electrode 32 and the drain electrode ( 34) is laminated, which constitutes a thin film transistor (T) which is a switching element.

Meanwhile, also in the capacitor region C, the second metal pattern (22b of FIG. 2C) and the second impurity amorphous silicon pattern (21b of FIG. 2C) exposed around the third photoresist pattern (72c of FIG. 2C) are removed. By exposing the bottom end of the second pure amorphous silicon pattern (20b in FIG. 2C), the gate insulating film 18, the first semiconductor pattern 26a and the second semiconductor correspond to the gate wiring 14. The semiconductor pattern 26 and the metal pattern 36 which consist of the pattern 26b are laminated | stacked.

Although not shown, data lines are formed at the boundary of the pixel region P to cross the gate wiring 14 to define the pixel region P and extend from the source electrode 32. As described above, since the data line extends from the source electrode 32, the data line has the same stacked structure as the portion where the source electrode 32 is formed. That is, a third semiconductor pattern extending from the active layer 24a and a fourth semiconductor pattern extending from the ohmic contact layer 24b are formed under the data line. Next, the third photoresist pattern 72c is removed.

2E shows a third mask process. As shown, an inorganic insulating material including silicon nitride or silicon oxide is used on the source and drain electrodes 32 and 34 and the data line (not shown) and the metal pattern 36 before forming the color filter. Thus, the first protective layer 38 is formed. If the color filter is formed without forming the first protective layer 38, the exposed active layer 24a, which determines the characteristics of the thin film transistor T, is contaminated during the formation of the color filter. This results in deterioration of the transistor T. Therefore, formation of the first protective layer 38 is an essential process.

Next, a color filter G corresponding to the pixel region P is applied by applying a pigment having a color of red, green, or blue to the upper portion of the first protective layer 38 and patterning the same by a third mask process. To form. Although not shown, red and blue color filters are formed in the adjacent pixel areas P by using the fourth and fifth mask processes.

2F shows a sixth mask process. As shown, the second protective layer 42 is formed on the first color filter G by using an inorganic insulating material, and the drain electrode 34 of the switching region S is formed by a sixth mask process. First and second contact holes CH1 and CH2 are formed to expose the metal pattern 36 of the capacitor region C, respectively. The second protective layer 42 serves to prevent a problem that the pigment material is eluted from the color filter G to contaminate the liquid crystal.

Next, as shown in FIG. 2G illustrating the seventh mask process, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on top of the second protective layer 42. The deposition and the seventh mask process are performed to form the pixel electrode 50 in the pixel region P. The pixel electrode P is connected to the thin film transistor T by contacting the drain electrode 34 through the first contact hole CH1 and the metal pattern 36 through the second contact hole CH2. Here, the gate wiring 16 and the metal pattern 36 overlap each other vertically to form a storage capacitor Cst.

By the above process, an array substrate for a liquid crystal display device having a COT structure is completed. As described above, the semiconductor layer, the source, and the drain electrode are formed as one mask in order to reduce the burden of the manufacturing process by the mask process, which is inevitably increased according to the CTO structure, which causes some problems. .

That is, in FIG. 2G showing the completed array substrate, around the source electrode 32, the drain electrode 34, an active layer 24 made of pure amorphous silicon, referred to as a so-called active tail, is exposed. This is caused by the exposure of the light supplied from the backlight unit (not shown) located below the substrate 12 and the external light to generate a leakage current (Ioff), resulting in the deterioration of the characteristics of the thin film transistor (T). In addition, even around the data line (not shown), pure semiconductor is made of pure silicon, and the semiconductor pattern extending to the active layer protrudes to be exposed to light, which is a wavy noise between the pixel electrodes 50. ) Will cause a problem, resulting in degradation of image quality. In addition, in order to cover the semiconductor pattern exposed around the data line (not shown), a larger black matrix must be present in the upper electrode, thereby causing a problem of reducing the aperture ratio.

An object of the present invention is to provide an array substrate for a COT structure liquid crystal display device having improved quality without increasing the number of mask processes in the manufacturing process of the array substrate for the COT structure liquid crystal display device.

That is, a COT structure liquid crystal display device capable of providing excellent quality images by preventing leakage currents, wave noise, and reduction of aperture ratio caused by amorphous silicon materials protruding around the source electrode, drain electrode, and data wiring. To propose a method of preparation.

In order to solve the above problems, the present invention comprises the steps of forming a gate wiring extending in one direction on the substrate, a gate electrode connected to the gate wiring, and a common wiring spaced in parallel with the gate wiring Wow; Forming a gate insulating film on a substrate on which the gate wiring, the gate electrode and the common wiring are formed; Forming a pure amorphous silicon pattern and an impurity amorphous silicon pattern having a flat top surface corresponding to the gate electrode on the gate insulating layer; Forming a color filter pattern on the substrate on which the impurity amorphous silicon pattern is formed; Forming a first passivation layer covering the color filter pattern and exposing the impurity amorphous silicon pattern; A source electrode and a drain electrode spaced apart from each other on the exposed impurity amorphous silicon pattern, a data line connected to the source electrode and defining a pixel area crossing the gate line, and connected to the drain electrode and the pixel area A method of manufacturing an array substrate for a liquid crystal display (COT) structure, the method comprising: forming a pixel electrode extending to the first electrode; and a first common electrode connected to the common wiring and alternately arranged in parallel with the pixel electrode.

In addition, the present invention provides a method for manufacturing a semiconductor device comprising: forming a gate wiring extending in one direction on a substrate, and a gate electrode connected to the gate wiring; Forming a gate insulating film on a substrate on which the gate wiring and the gate electrode are formed; Forming a pure amorphous silicon pattern and an impurity amorphous silicon pattern on the gate insulating layer, corresponding to the gate electrode; Forming a color filter pattern on the substrate on which the impurity amorphous silicon pattern is formed; Forming a first passivation layer covering the color filter pattern and exposing the impurity amorphous silicon pattern; A source electrode and a drain electrode spaced apart from each other on the exposed impurity amorphous silicon pattern, a data line connected to the source electrode and defining a pixel region crossing the gate line, and connected to the drain electrode and the pixel region. Forming an extended pixel electrode, and removing the impurity amorphous silicon pattern and exposing the pure amorphous silicon pattern by using the spaced source and drain electrodes as masks. Provided is a method of manufacturing an array substrate.

The present invention solves the problem of leakage current and wave noise without increasing the number of masks, and has a COT structure liquid crystal display device having an improved aperture ratio, compared to the conventional technique of simultaneously forming a semiconductor layer, a source, and a drain electrode. It is possible to provide an array substrate.

That is, by forming a semiconductor layer having an island shape on the gate electrode and the source and drain electrodes thereon by different mask processes, the semiconductor layer, particularly the active layer, is generated by protruding from the source and drain electrodes and the data wiring. This has the effect of solving problems such as leakage current and wave noise. On the other hand, by forming the source and drain electrodes and the pixel electrode (and the common electrode) by one mask process, it is possible to prevent the increase of the mask process.

The present invention solves the problems of reducing leakage current, wave noise, and aperture ratio by providing an island-shaped semiconductor layer, and also omits a protective layer for protecting a channel of a thin film transistor in a color filter forming process. Provided are a manufacturing process of an array substrate for a liquid crystal display device.

3 is a schematic plan view of an array substrate for a COT structure liquid crystal display according to an exemplary embodiment of the present invention.

As illustrated, the array substrate 100 of the COT structure liquid crystal display device is formed by crossing the gate line 112 and the data line 140 on the transparent substrate 110 to define the pixel area P. The thin film transistor T is formed at an intersection point of the gate line 112 and the data line 140. The data line 140 has a shape bent in the middle portion of the pixel region P, thereby enabling a multi-domain structure. However, the shape of the data line 140 is not limited thereto and may be a straight line having no bent portion. The thin film transistor T includes a gate electrode 114 connected to the gate line 112, a semiconductor layer 124 over the gate electrode 114, and a data line 140 over the semiconductor layer 124. ) And a drain electrode 144 spaced apart from the source electrode 142. Here, the source electrode 142 is shown as having a U shape, the drain electrode 144 is shown as having a bar shape that is inserted into the opening of the U shape. However, the shape of the source and drain electrodes is not limited thereto, and any shape may be used as long as the source and drain electrodes have a structure spaced apart from each other while overlapping the semiconductor layer.

Here, in the array substrate 100 for the COT structure liquid crystal display device according to the present invention, unlike the conventional array substrate illustrated in FIG. 1, the semiconductor layer 124 including the active layer (not shown) may include the gate electrode 114. ) It is made of island shape only at the top. That is, the semiconductor layer 124 is not formed under the source and drain electrodes 142 and 144 extending outside the gate electrode 114 and under the data line 140.

As described above, since the semiconductor layer 124 is configured so that only the gate electrode 114 has an island shape having the same or smaller cross-sectional area as the gate electrode 114 and overlaps completely, leakage of the T in the thin film transistor as in the prior art. Since there is no possibility of a problem of deterioration due to the current and no semiconductor pattern is protruded around the data line 140, the problem of wavy noise is solved and the width of the black matrix is not required to cover the problem, thereby reducing the aperture ratio. It can also be solved.

In the pixel region P, the drain electrode 144 and the pixel electrode 150 of the thin film transistor T are formed. Although not shown, the source and drain electrodes 142 and 144 and the data line 140 have a double layer structure, and the pixel electrode 150 has a structure extending from a lower layer of the drain electrode 144. In addition, the pixel electrode 150 is configured to overlap the gate wiring 112 of the front end. Here, an overlapping portion of the gate wiring 112 is used as the first electrode, an overlapping portion of the pixel electrode 150 is used as the second electrode, and an insulating layer (not shown) interposed between the first and second electrodes is disposed. The storage layer Cst is formed as the dielectric layer.

Further, color filters R, G, and B having any one of red, green, and blue colors are formed in each pixel region P. FIG. That is, due to the characteristics of the COT structure, the color filters R, G, and B are formed on the same substrate 110 as the thin film transistor T.

In addition, a gate pad 118 for applying a signal to the gate wire 112 is formed at one end of the gate wire 112, and a gate connected to the gate pad 118 through the first contact hole CH1. The pad terminal 152 is formed. In addition, a data pad 119 for applying a signal to the data line 140 is formed at one end of the data line 140, and data connected to the data pad 119 through the second contact hole CH2. The pad terminal 154 is formed.

The biggest feature of the embodiment of the present invention relates to a manufacturing method capable of forming an island-shaped semiconductor layer without increasing the mask process, which is illustrated in FIGS. 4A to 4K, 5A to 5K, and 6A to 6A. It demonstrates with reference to FIG. 6K.

4A to 4K are cross-sectional views of manufacturing parts cut along the line IV-IV of FIG. 3, and FIGS. 5A to 5K are cross-sectional views of manufacturing parts of the cutting parts taken along VV of FIG. 3, and FIGS. 6A to 4K. 6k is a cross-sectional view of the manufacturing process of the portion cut along the line VI-VI of FIG. 3. For convenience of description, a pixel region P including a switching region S in which a thin film transistor is formed, a capacitor region C in which a storage capacitor is formed, and a gate in which a gate pad and a data pad are formed on a substrate, respectively. The pad part GP and the data pad part DP are defined.

4A, 5A, and 6A show a first mask process. As illustrated, a first metal layer (not shown) is formed and patterned on the substrate 110 to extend in one direction along the boundary of the pixel region P, and to form a gate wiring 112 and the switching region S. FIG. A gate electrode 114 is formed on the gate line 112. The gate line 112 is positioned corresponding to the capacitor region C. The first metal layer (not shown) is made of at least one material of aluminum, aluminum alloy, tungsten, chromium and molybdenum.

In addition, a gate pad 118 is formed in the gate pad part GP and connected to one end of the gate line 112, and a data pad 119 is formed in the data pad part DP.

Next, a gate insulating film is deposited by depositing an inorganic insulating material such as silicon nitride or silicon oxide on the entire surface of the substrate 110 on which the gate wiring 112, the gate electrode 114, the gate and the data pads 118 and 119 are formed. Form 120.

4B-4D, 5B-5D, and 6B-6D show a second mask process.

As shown in FIGS. 4B, 5B, and 6B, pure amorphous silicon layer 121 and impurity amorphous silicon layer 122 are successively deposited on the gate insulating layer 120, and a photoresist as a photosensitive material is deposited thereon. To form a photoresist layer (not shown). Next, a mask M having a transmissive part TA, a transflective part HTA, and a blocking part BA is positioned on the photoresist layer (not shown). Here, the transmission part TA, the transflective part HTA, and the blocking part BA are areas where the light transmittances are different. The transmissive part HTA transmits light so that the photoresist layer (not shown) is completely chemically changed, that is, completely exposed by light, and the blocking part BA functions to completely block light. In addition, the semi-transmissive part HTA forms a slit shape or a semi-transparent film on the mask M, thereby lowering the intensity of light or lowering the amount of light transmitted, thereby incompletely exposing the photoresist layer (not shown). Function

By exposing and developing the photoresist layer (not shown) using the mask M including the transflective portion HTA as described above, the first and second thicknesses t1 and t2 are respectively provided, and the blocking portions BA are respectively. ) And the first and second photoresist patterns 182a and 182b at positions corresponding to the transflective portion HTA. The first photoresist pattern 182a corresponding to the blocking part BA is formed in the switching area S, and is formed in the center of the gate pad 118 and the data pad part DP in the gate pad part GP. The photoresist layer (not shown) is removed from the central portion of the data pad 119 to correspond to the transmissive portion TA of the mask M to expose the impurity amorphous silicon layer 122. A second photoresist pattern 182b having a second thickness t2 smaller than the first thickness t1 of the first photoresist pattern 182a is formed in the remaining regions.

Next, as shown in FIGS. 4C, 5C, and 6C, the exposed impurity amorphous silicon layer 122, the pure amorphous silicon layer 121, and the gate insulating layer 120 below the exposed impurity are removed to remove the gate pad 118. First and second contact holes CH1 and CH2 are formed to expose the data pad 119, respectively. Then, the ashing process is performed on the first and second photoresist patterns (182a and 182b of FIGS. 4B, 5B and 6B), and the second photoresist patterns having small thicknesses (FIGS. 4B, 5B and 6B). By removing 182b), the impurity amorphous silicon layer 122 beneath it is exposed. In addition, the ashing process reduces the thickness of the first photoresist pattern 182a of FIGS. 4B, 5B, and 6B, and thus forms a third photoresist pattern 182c having a third thickness t3 in the switching region S. FIG. .

Next, as shown in FIGS. 4D, 5D, and 6D, the impurity amorphous silicon pattern (122 of FIG. 4C) exposed to the outside of the third photoresist pattern (182c of FIG. 4C) and the pure amorphous silicon pattern underneath thereof ( 121 in FIGS. 4C, 5C, and 6C are removed to expose the lower gate insulating film 120. Since the third photoresist pattern 182c of FIG. 4C is positioned to correspond to the central portion of the gate electrode 114 in the switching region S, the gate insulating layer 120 corresponds to the gate electrode 114. ) Is formed on the pure amorphous silicon pattern 121a and the impurity amorphous silicon pattern 122a. More specifically, the third photoresist pattern 182c of FIG. 4C may be the same as the gate electrode 114. Because of the small cross-sectional area, the pure amorphous silicon pattern 121a and the impurity amorphous silicon pattern 122a also have a cross-sectional area equal to or smaller than that of the gate electrode 114, and as a result, a semiconductor layer that also constitutes a thin film transistor also includes the gate. It is formed in an island shape while having the same or smaller cross-sectional area as the electrode 214.

Next, FIGS. 4E, 5E and 6E show a third mask process. As illustrated, the green pigment is coated on the gate insulating layer 120 on which the pure amorphous silicon pattern 121a and the impurity amorphous silicon pattern 122a are formed and patterned by a third mask process to thereby form the pixel region P. FIG. To form a green color filter (G). Next, although not shown, red and blue color filters are formed in the adjacent pixel areas P through fourth and fifth mask processes. Here, the order of forming the red, green, and blue color filters is not determined. In this case, the gate and the data pads 118 and 119 are continuously exposed through the first and second contact holes CH1 and CH2.

In the manufacture of a conventional COT structure array substrate, the formation of a protective layer is required before the formation of the color filter for protecting the channel, but in the present embodiment, the channel is not opened before the formation of the color filter and thus protecting the channel. It does not require the formation of a protective layer.

4F and 4G, 5F and 5G, 6F and 6G show a sixth mask process.

First, as shown in FIGS. 4F, 5F, and 6F, an inorganic insulating material such as silicon nitride or silicon oxide is deposited to form a first protective layer 132, and a fourth layer having a fourth thickness t4 thereon. 4 Photoresist pattern 184 is formed. In the present embodiment, the first protective layer 132 is formed using silicon nitride as an example. The fourth photoresist pattern 184 is formed while exposing the switching region S, the gate pad 118, and the data pad part 119.

Next, as illustrated in FIGS. 4G, 5G and 6G, the first protective layer 132 exposed between the fourth photoresist patterns 184 (FIGS. 4F, 5F and 6F) is removed by dry etching. . In this case, the dry etching is performed using a gas including SF ₆ (sulfur hexafluoride) and O ₂ , and the silicon nitride forming the first protective layer 132 in the presence of such a gas and impurities below it. The etching ratio of silane (SiH4) constituting the amorphous silicon pattern 122a is about 30 to 50: 1. Therefore, even when the first passivation layer 132 is slightly overetched in the switching region S, since the etching ratio of the impurity amorphous silicon pattern 122a at the bottom thereof is relatively low, the pure amorphous silicon pattern 121a at the bottom thereof is relatively low. ) There is no fear of damage.

By the dry etching process as described above, all of the first protective layer 132 of the switching region S is removed to expose the pure amorphous silicon pattern 122a, and the gate and data pad portions GP and DP are exposed. In each case, the gate pad 118 and the data pad 119 are exposed through the first and second contact holes CH1 and CH2.

Here, without forming the first and second contact holes CH1 and CH2 through FIGS. 4C, 5C and 6C, the gate insulating layer 120 together with the first protective layer 132 in the processes of FIGS. 4G, 5G and 6G. Although it may be considered to form contact holes by simultaneously removing the same, in this case, there is a possibility that the color filter G, which was enclosed while the first protective layer 132 is overetched, is damaged. Therefore, as in the present exemplary embodiment, it is preferable to form the first and second contact holes CH1 and CH2 by etching the gate insulating layer 120 before the etching process of the first protective layer 132.

After the etching process of the first protective layer 132, the fourth photoresist pattern 184 is removed.

Next, FIGS. 4H-4K, 5H-5K, and 6H-6K show a seventh mask process.

First, as shown in FIGS. 4H, 5H, and 6H, the second metal layer 134 and the third metal layer 136 are successively deposited, and a photoresist layer (not shown) is formed thereon, and then the transflective portion is formed. A fifth photoresist pattern 186a having a fifth thickness t5 and a sixth thickness t6 smaller than the fifth thickness t5 by patterning by a seventh mask process using a mask (not shown) having a 6 Photoresist pattern 186b is formed. Here, the second metal layer 134 is made of any one material of molybdenum-titanium alloy, molybdenum, chromium, titanium, and has transparency having a thickness of about 400-500 mm 3. The second metal layer 134 may form a pixel electrode later, since the material such as indium tin oxide (ITO) is not used because the material such as ITO has poor ohmic contact properties with the ohmic contact layer. In addition, the third metal layer 136 is made of copper. The fifth photoresist pattern 186a is positioned to correspond to the pixel region P, the gate pad portion GP, and the data pad portion DP, and the sixth photoresist pattern 186b is the switching region S. It is located at both edges of the. That is, in the switching region S, the third metal layer 136 corresponding to the impurity amorphous silicon pattern 122a is exposed between the sixth photoresist pattern 186b.

Next, as shown in FIGS. 4i, 5i and 6i, the exposed third metal layer (136 in FIGS. 4h, 5h and 6h) and the second metal layer (134 in FIGS. 4h, 5h and 6h) below are subjected to wet etching. And the second and third metal layers (134, 136 of FIGS. 4H, 5H, 6H) are removed in the switching region S to remove the exposed impurity amorphous silicon pattern (122a of FIG. 4H). The pure amorphous silicon pattern (121a in FIG. 4H) is exposed.

In the switching region S, the pure amorphous silicon pattern (121a of FIG. 4H) becomes the active layer 124a, and the impurity amorphous silicon pattern (122a of FIG. 4H) in the etched state thereon is the ohmic contact layer 124b. The exposed area of the active layer 124a is defined as a channel area. In addition, a source electrode 142 and a drain electrode 144 having a double layer structure and spaced apart from each other are formed on the ohmic contact layer 124b. Here, the source and drain electrodes 142 and 144 are formed from the lower layers 142a and 144a and the third metal layers 136 and 136 formed in the second metal layers 134 of FIGS. 4H, 5H and 6H, respectively. Upper layers 142b and 144b formed. At the same time, a data line (not shown) connected to the source electrode 142 and having the same double layer structure and crossing the gate line 112 to define the pixel region P is formed. The gate and data pad portions GP and DP may include first metal patterns 134b and 134c contacting the gate and data pads 118 and 119 through the first and second contact holes CH1 and CH2, respectively. Second metal patterns 136b and 136c are formed. In the pixel region P, first and second metal patterns 134a and 136a are formed on the green color filter G.

Next, as the ashing process proceeds, the sixth photoresist pattern (186b of FIGS. 4H, 5H and 6H) is removed, and the thickness of the fifth photoresist pattern (186a of FIGS. 4H, 5H and 6H) decreases to a thickness. A seventh photoresist pattern 186c having a thickness t7 is formed. The second protective layer 138 is formed by stacking an inorganic insulating material such as silicon nitride or silicon oxide on the seventh photoresist pattern 186c by using a sputter. Generally, the inorganic insulating material is by chemical vapor deposition (CVD), but the chemical vapor deposition is usually performed at a high temperature of 350 ° C. or higher, and the high temperature condition is that of the seventh photoresist pattern 186c having a melting point of about 200 ° C. The shape may be damaged and the desired pattern may not be obtained. Therefore, in the present embodiment, since the formation of the second protective layer 138 proceeds to a relatively low temperature process of about 150 ° C. or less using sputtering, a desired pattern can be obtained without damaging the photoresist pattern.

In this case, as shown in part A, due to the wet etching process of the first and second metal layers (134, 136 of FIGS. 4H, 5H, and 6H of FIG. 4H, 5H, and 6H), the seventh photoresist pattern 186c may be formed. The first and second metal patterns 134a and 136a are engraved inwardly, so that the second protective layer 138 is discontinuous at the boundary between the seventh photoresist pattern 186c and the second metal pattern 136a. You have a part. Similarly, in the gate and data pad portions GP and DP, the second protective layer 138 has a discontinuous portion even at the boundary between the seventh photoresist pattern 186c and the second metal patterns 136b and 136c. . In addition, although the second protective layer 138 is seen as continuous at the boundary between the drain electrode 144 and the seventh photoresist pattern 186c, the side surface of the drain electrode 144, which is not shown in the drawing, is formed by wet etching. Since it is in the removed state, the second protective layer 138 also has discontinuous portions at the boundary between the drain electrode 144 and the seventh photoresist pattern 186c. In the structure described above, an etchant for removing the seventh photoresist pattern 186c penetrates into a discontinuous portion of the second protective layer 138, and the seventh photoresist pattern 186c is formed of the second metal pattern 136a. The second protective layer 138 is also removed from the upper portion of the upper portion 136b and 136c at the same time, which is commonly referred to as a lift off process.

As shown in FIGS. 4J, 5J, and 6J, the second protective layer 138 is also removed thereon by removing the seventh photoresist pattern (186c in FIGS. 4I, 5i, and 6i) by a lift off process. The second metal patterns 136a, 136b, and 136c are exposed in the pixel region P, the capacitor region C, and the gate and data pad portions GP and DP. On the other hand, since the seventh photoresist pattern (186c of FIGS. 4I, 5I and 6I) does not exist in the switching region P, the source and drain electrodes 142 and the second protective layer 138 protect the channel region. 144 is a structure covering.

Next, as shown in 4k, 5k, 6k, the second metal pattern (136a, 136b, 136c in FIGS. 4j, 5j, 6j) not covered by the second protective layer 138 is removed and the lower portion thereof is removed. The first metal patterns 134a, 134b and 134c of FIGS. 4J, 5J and 6J are exposed. At this time, the removal of the second metal pattern (136a, 136b, 136c of Figures 4j, 5j, 6j) is made using a mixed acid solution of phosphoric acid-acetic acid-nitric acid (PAN). As described above, the second metal patterns 136a, 136b, and 136c (or the third metal layer 136 of FIG. 4h) of FIGS. 4j, 5j and 6j (or 136 of FIG. 4h) are made of copper, and the first metal patterns (FIGS. 4j and 5j). , 6j 134a, 134b, 134c (or the second metal layer (134 in FIG. 4H)) consists of molybdenum-titanium, molybdenum, chromium, titanium, and the like, phosphoric acid-acetic acid-nitric acid This is because the mixed acid solution of PAN) selectively etches copper material, and molybdenum-titanium, molybdenum, chromium, and titanium do not etch.

The exposed first metal pattern 134a of the pixel region P becomes the pixel electrode 150 connected to the lower layer 144a of the drain electrode 144 and the gate wiring 112 of the capacitor region C. It is extended to overlap with). The exposed first metal pattern 134b of the gate pad part GP becomes the gate pad terminal 152 that contacts the gate pad 118 through the first contact hole CH1, and the data pad. The exposed first metal pattern 134c of the part DP becomes the data pad terminal 154 in contact with the data pad 119 through the second contact hole CH2. In the capacitor region C, an overlapping portion of the gate wiring 112 is used as the first electrode, and an overlapping portion of the pixel electrode 150 is used as the second electrode, and the gate insulating layer 132 and the gap therebetween are formed. The storage capacitor Cst which uses the one protective layer 132 as a dielectric layer is comprised.

As a result, the data line (not shown), the source electrode and the drain electrodes 142 and 144 have a double layer structure of a lower layer made of a material such as molybdenum-titanium and an upper layer made of copper as a low resistance material. Meanwhile, the pixel electrode 150, the gate electrode pad terminal 152, and the data electrode pad terminal 154 are transparent because they have a single layer structure in which a material such as molybdenum-titanium forms a thin film (a thickness of about 300 to 500 μm). It has strong corrosion resistance.

By the above process, the array substrate for the COT structure liquid crystal display device according to the exemplary embodiment of the present invention is completed. The lower substrate, which is an array substrate, is bonded to the upper substrate on which the black matrix and the common electrode are formed and the liquid crystal layer is interposed therebetween to form a liquid crystal display device. The black matrix serves to block a non-display area such as a thin film transistor of a lower substrate, and unlike the prior art of FIG. 1, since the semiconductor layer protruding from the data line does not exist, the width of the black matrix can be narrowed. Therefore, the opening ratio is increased. In addition, the common electrode serves to form an electric field driving the pixel electrode of the lower substrate and the liquid crystal layer. Here, in order to maintain the thickness (cell gap) of the liquid crystal layer uniformly before bonding of the upper and lower substrates, a step of forming columnar column spacers on any one of the upper and lower substrates is included.

The above liquid crystal display device has a narrow viewing angle because the liquid crystal layer is driven using an electric field formed vertically between the pixel electrode and the common electrode, and the pixel electrode and the common electrode are disposed on the same substrate to solve the problem. An in-plane switching type liquid crystal display device using a horizontal electric field therebetween has been proposed.

7 is a schematic plan view of an array substrate for a COT structure transverse field type liquid crystal display according to an exemplary embodiment of the present invention.

As shown, the array substrate 200 of the COT structure transverse field type liquid crystal display device is formed on the transparent substrate 210 while the gate wiring 212 and the data wiring 240 cross each other to define the pixel region P. The thin film transistor T is formed at an intersection point of the gate line 212 and the data line 240. The data line 240 has a shape bent in the middle portion of the pixel region P, thereby enabling a multi-domain structure. However, the shape of the data line 240 is not limited thereto and may be a straight line having no bent portion. The thin film transistor T includes a gate electrode 214 connected to the gate wire 212, a semiconductor layer 224 over the gate electrode 214, and a data wire 240 over the semiconductor layer 224. Source electrode 242 extending from the first electrode 242 and the drain electrode 244 spaced apart from the source electrode 242. Here, the source electrode 242 is shown as having a U shape, the drain electrode 244 is shown as having a bar shape that is inserted into the opening of the U shape. However, the shape of the source and drain electrodes is not limited thereto, and any shape may be used as long as the source and drain electrodes have a structure spaced apart from each other while overlapping the semiconductor layer.

Like the array substrate 100 of the present invention described with reference to FIG. 3, the semiconductor layer 224 including an active layer (not shown) has an island shape only on the gate electrode 214. That is, since the semiconductor layer 224 has the same or smaller cross-sectional area as that of the gate electrode 214 and is completely overlapped, the semiconductor layer 224 has lower portions of the source and drain electrodes 242 and 244 extending outside the gate electrode 214, and data. The semiconductor layer 224 is not formed below the wiring 240. As described above, since the semiconductor layer 224 having an island shape is formed only in the gate electrode 214, there is no problem of deterioration of characteristics due to leakage current in the thin film transistor as in the prior art, and also around the data wiring 240. As the semiconductor pattern does not protrude, the problem of the wavy noise is solved, and the width of the black matrix is not required to cover it, thereby reducing the aperture ratio.

In addition, the common wiring 216 is formed to be spaced apart in parallel to the gate wiring 212, and the first and second common electrodes (parallel to the data wiring 240 from both ends of the common wiring 216). 217a and 217b are comprised. That is, the first and second common electrodes 217a and 217b have a shape in which a central portion thereof is bent. In addition, the common electrode connection wiring 217c is formed in parallel with the common wiring 216 while connecting the ends of the first and second common electrodes 217a and 217b. That is, the common wiring 216, the first and second common electrodes 217a and 217b, and the common electrode connection wiring 217c have a structure surrounding the pixel area P. In addition, a third common electrode 250 is connected to a central portion of the common electrode connection wiring 217c through a first contact hole CH1 and parallel to the first and second common electrodes 217a and 217b. Formed.

In the pixel region P, a pixel electrode 260 connected to the thin film transistor T is disposed between the first and third common electrodes 217a and 250 and the second and third common electrodes 17b and 250). That is, the common electrodes 217a, 217b, and 250 and the pixel electrodes 260 are spaced apart in parallel to each other, and a liquid crystal layer (not shown) is driven by forming a parallel electric field therebetween by applying a voltage. do.

The pixel electrode 260 is connected to the drain electrode 244 of the thin film transistor T. To this end, the pixel electrode 260 extends from the drain electrode 244 and overlaps the common wiring 216. ) Is configured. That is, the pixel electrode 260 is connected to the drain electrode 244 of the thin film transistor T through the pixel electrode connection wiring 262. Although not shown, the source and drain electrodes 242 and 244 and the data line 240 have a double layer structure, and the pixel electrode 260 has a structure extending from a lower layer of the drain electrode 244. As described above, the pixel electrode connection wiring 262 overlaps the common wiring 216, and the overlapping portion of the common wiring 216 is the first electrode, and the overlapping portion of the pixel electrode connection wiring 262. Is the second electrode, and the storage capacitor Cst is formed using the insulating layer (not shown) between the first and second electrodes as the dielectric layer.

In addition, a green color filter G is formed in the pixel region P, and red or blue color filters R and B are formed in each of the adjacent pixel regions P. FIG. That is, due to the characteristics of the COT structure, the color filters R, G, and B are formed on the same substrate 210 as the thin film transistor T.

In addition, a gate pad 218 for applying a signal to the gate wire 212 is formed at one end of the gate wire 212, and a gate connected to the gate pad 218 through the second contact hole CH2. The pad terminal 252 is formed. In addition, a data pad 219 for applying a signal to the data wire 240 is formed at one end of the data wire 240, and data connected to the data pad 219 through the third contact hole CH3. The pad terminal 254 is formed.

Next, a manufacturing process for the array substrate of the COT structure transverse electric field type liquid crystal display device having the above configuration will be described.

8A to 8K are cross-sectional views of manufacturing parts taken along the line VIII-VIII of FIG. 7, and FIGS. 9A to 9K are cross-sectional views of manufacturing processes taken along the line IX-IX of FIG. 7, respectively. For convenience of description, the pixel region P including the switching region S in which the thin film transistor is formed and the capacitor region C in which the storage capacitor is formed are defined on the substrate. In addition, since the manufacturing method for the gate and data pad unit in which the gate pad 218 of FIG. 7 and the data pad 219 of FIG. 7 are formed is the same as that described with reference to FIGS. 5A to 5K and FIGS. Omit it. In addition, since it is similar to the manufacturing process described above except for the process of forming the common wiring and the common electrode will be described briefly.

8A and 9A show a first mask process. As illustrated, a first metal layer (not shown) is formed and patterned on the substrate 210 to extend in one direction along the boundary of the pixel region P, and to form a gate wiring (not shown) and the switching region S. A gate electrode 214 connected to the gate line (not shown) is formed. In addition, a common wiring 216 spaced apart in parallel with the gate wiring (not shown) and first and second common electrodes (not shown) extending from the common wiring 216 are formed. Two common electrodes (not shown) are connected to both ends and a common electrode connection wiring 217c parallel to the common wiring 216 is formed. In this case, the common wiring 216 is also formed in the capacitor region C. The first metal layer (not shown) is made of at least one material of aluminum, aluminum alloy, tungsten, chromium and molybdenum.

Next, an inorganic insulating material such as silicon nitride or silicon oxide on the entire surface of the substrate 210 on which the gate wiring (not shown), the gate electrode 214, the common wiring 216, and the common electrode connection wiring 217c are formed. Deposited to form a gate insulating film 220.

8B-8D and 9B-9D show a second mask process.

As shown in FIGS. 8B and 9B, a pure amorphous silicon layer 221 and an impurity amorphous silicon layer 222 are successively deposited on the gate insulating layer 220, and a photoresist layer (not shown) is disposed thereon. Form. Next, a mask M having a transmissive part TA, a transflective part HTA, and a blocking part BA is positioned on the photoresist layer (not shown).

By exposing and developing the photoresist layer (not shown) using the mask M including the transflective portion HTA as described above, the first and second thicknesses t1 and t2 are respectively provided, and the blocking portions BA are respectively. ) And the first and second photoresist patterns 282a and 282b at positions corresponding to the transflective portion HTA. The first photoresist pattern 282a corresponding to the blocking part BA is formed in the switching area S, and corresponding to the transmission part TA of the mask M with respect to the central portion of the common electrode connection wiring 217c. As the photoresist layer is completely removed, the impurity amorphous silicon layer 222 is exposed. A second photoresist pattern 282b having a second thickness t2 smaller than the first thickness t1 of the first photoresist pattern 282a is formed in the remaining regions.

Next, as shown in FIGS. 8C and 9C, the common electrode connection wiring 217c is removed by removing the exposed impurity amorphous silicon layer 222, the pure amorphous silicon layer 221 and the gate insulating layer 220 below. The first contact hole CH1 exposing is formed. Then, the ashing process is performed on the first and second photoresist patterns 282a and 282b of FIGS. 8B and 9B to remove the second photoresist patterns 282b of FIGS. 8B and 9B. The impurity amorphous silicon layer 222 is exposed. In addition, by the ashing process, the thickness of the first photoresist pattern 282a of FIG. 8B is reduced so that a third photoresist pattern 282c having a third thickness t3 is formed in the switching region S. FIG.

Next, as shown in FIGS. 8D and 9D, the impurity amorphous silicon pattern 222c of FIGS. 8B and 9B exposed to the outside of the third photoresist pattern 282c of FIG. 8B, and the pure amorphous silicon pattern below it 8B and 9B are removed to expose the lower gate insulating film 220. As a result, a pure amorphous silicon pattern 221a and an impurity amorphous silicon pattern 222a are formed on the gate insulating layer 220 corresponding to the gate electrode 214. More specifically, since the third photoresist pattern 282c of FIG. 8B has the same or smaller cross-sectional area as the gate electrode 214, the pure amorphous silicon pattern 221a and the impurity amorphous silicon pattern 222a may also be used. The semiconductor layer having the same or smaller cross-sectional area as the gate electrode 214, and consequently forming the thin film transistor, is also formed in an island shape with the same or smaller cross-sectional area as the gate electrode 214.

8E and 9E show a third mask process. As illustrated, a green color filter corresponding to the pixel region P may be formed on the gate insulating layer 220 on which the pure amorphous silicon pattern 221a and the impurity amorphous silicon pattern 222a are formed. Form G). Next, although not shown, red and blue color filters are formed in the adjacent pixel areas P through fourth and fifth mask processes. In this case, the common electrode connection wiring 217c is continuously exposed through the first contact hole CH1.

In the manufacture of a conventional COT structure array substrate, the formation of a protective layer is required before the formation of the color filter for protecting the channel, but in the present embodiment, the channel is not opened before the formation of the color filter and thus protecting the channel. It does not require the formation of a protective layer.

8F and 8G, 9F and 9G show a sixth mask process.

First, as shown in FIGS. 8F and 9F, an inorganic insulating material such as silicon nitride or silicon oxide is deposited to form a first passivation layer 232, and a fourth photo having a fourth thickness t4 thereon. A resist pattern 284 is formed. In this embodiment, the first protective layer 232 is formed using silicon nitride as an example. The fourth photoresist pattern 284 is formed while exposing a part of the common wiring 216 of the switching region S and the capacitor region C, and a central portion of the common electrode connection wiring 217c.

Next, as shown in FIGS. 8G and 9G, the first protective layer 232 exposed between the fourth photoresist patterns 284 of FIGS. 8G and 9G may be removed by dry etching. In this case, dry etching is performed using a gas including SF ₆ (sulfur hexafluoride) and O ₂ , and the silicon nitride forming the first protective layer 232 in the presence of such a gas and impurities below it. The etching ratio of the silane (SiH4) constituting the amorphous silicon pattern 222a is about 30 to 50: 1. Therefore, even when the first passivation layer 232 is slightly overetched in the switching region S, since the etching ratio of the impurity amorphous silicon pattern 222a at the bottom thereof is relatively low, the pure amorphous silicon pattern 221a at the bottom thereof is relatively low. ) There is no fear of damage.

By the dry etching process as described above, all of the first protective layer 232 of the switching region S is removed so that the pure amorphous silicon pattern 222a is exposed, and the common electrode connection wiring 217c is disposed on the upper portion thereof. The first protective layer 232 is also removed to maintain the exposed state through the first contact hole CH1.

After the etching process of the first protective layer 232, the fourth photoresist pattern 284 is removed.

Next, FIGS. 8H-8K and 9H-9K show a seventh mask process.

First, as shown in FIGS. 8H and 9H, the second metal layer 234 and the third metal layer 236 are successively deposited, and a photoresist layer (not shown) is formed thereon, followed by a mask having a transflective portion. The fifth photoresist pattern 286a having the fifth thickness t5 and the sixth photo having a sixth thickness t6 smaller than the fifth thickness t5 by patterning by a seventh mask process using (not shown). A resist pattern 286b is formed. Here, the second metal layer 234 is made of a material of any one of molybdenum-titanium alloy, molybdenum, chromium, titanium and has a transparency of about 400-500 mm 3. In addition, the third metal layer 236 is made of copper. The fifth photoresist pattern 286a is positioned in the pixel region P to correspond to a region where a pixel electrode and a third common electrode are to be formed later, and the first contact hole CH1 of the common electrode connection wiring 217c. The sixth photoresist pattern 286b is positioned at both edges of the switching region S. As shown in FIG. That is, in the switching region S, the third metal layer 236 corresponding to the impurity amorphous silicon pattern 222a is exposed between the sixth photoresist pattern 286b.

Next, as shown in FIGS. 8I and 9I, the exposed third metal layer (236 in FIGS. 8H and 9H) and the second metal layer (234 in FIGS. 8H and 9H) underneath are removed by wet etching, and the switching region is removed. In (S), the second and third metal layers (234 and 236 of FIGS. 8H and 9H) are removed to remove the exposed impurity amorphous silicon pattern (222a of FIG. 8H), thereby removing the pure amorphous silicon pattern (FIG. 8H of the bottom). 221a) is exposed.

In the switching region S, the pure amorphous silicon pattern (221a in FIG. 8H) becomes the active layer 224a, and the impurity amorphous silicon pattern (222a in FIG. 8H) in the etched state thereon is the ohmic contact layer 224b. ), And the exposed region of the active layer 224a is defined as a channel region. In addition, a source electrode 242 and a drain electrode 244 are formed on the ohmic contact layer 224b to have a double layer structure of the lower layers 242a and 244b and the upper layers 242b and 244b, respectively. At the same time, a data line (not shown) connected to the source electrode 242 and having the same double layer structure and defining the pixel region P is formed to cross the gate line (not shown). In the pixel region P, first and second metal patterns 234a and 236a are formed on the drain electrode 244 and are connected to the upper and lower layers 244a and 244b and extend above the color filter G. do. In addition, first and second metal patterns 234b and 236b connected to the common electrode connection wiring 217c are connected to each other through the first contact hole CH1.

Next, as a result of the ashing process, the sixth photoresist pattern 286b of FIG. 8H is removed and a seventh photoresist pattern 286c having a seventh thickness t7 is formed. The second protective layer 238 is formed by stacking an inorganic insulating material such as silicon nitride or silicon oxide on the seventh photoresist pattern 286c by using a sputter. As described above, since the second protective layer 238 is formed in the state where the seventh photoresist pattern 286c is formed, the second protective layer (not sputtered under high temperature) is sputtered at a low temperature. 238).

At this time, as shown in part B, the wet etching process of the first and second metal layers (234 and 236 of FIGS. 8H and 9H) causes the first and second metal patterns to be inward of the seventh photoresist pattern 286c. 234a and 236a are indented, and thus, the second protective layer 238 has a discontinuous portion at the boundary between the seventh photoresist pattern 286c and the second metal pattern 236a. In the above structure, an etchant for removing the seventh photoresist pattern 286c penetrates into a discontinuous portion of the second passivation layer 238, and the seventh photoresist pattern 286c forms the second metal pattern 236a. And 236b, the second protective layer 238 on top thereof is also removed, which is commonly referred to as a lift off process.

As shown in FIGS. 8J and 9J, the second protective layer 238 is also removed thereon by removing the third photoresist pattern (286c in FIGS. 8I and 9I) by the lift-off process, thereby removing the pixel region. In P, the second metal patterns 236a and 236b are exposed. On the other hand, since the seventh photoresist pattern (286c in FIGS. 8I and 9I) does not exist in the switching region P, the source and drain electrodes 242 and 244 are protected while the second protective layer 238 protects the channel region. It becomes the structure covering.

Next, as shown in 8k and 9k, the second metal pattern (236a and 236b of FIGS. 8j and 9j) not covered by the second protective layer 238 is phosphoric acid -acetic acid. By removing using a mixed acid solution of -nitric acid (PAN), the first metal patterns (234a and 234b of FIGS. 8j and 9j) below are exposed. As described above, a mixed acid solution of phosphoric acid-acetic acid-nitric acid (PAN) selectively etches only copper material, and molybdenum-titanium, molybdenum, chromium and titanium do not etch. Therefore, only the second metal patterns 236a and 236b in FIGS. 8J and 9J can be selectively removed.

Here, the portion of the exposed first metal pattern 234a overlapping with the common wiring 216 is connected to the lower layer 244a of the drain electrode 244 to form the pixel electrode connection wiring 262. In addition, the pixel electrode 260 extends to the pixel region P to form the pixel electrode 260. Here, the overlapping portion of the common wiring 216 is the first electrode, the overlapping portion of the pixel electrode connection wiring 262 is the second electrode, and the gate insulating layer 262 interposed therebetween is used as the dielectric layer. The storage capacitor Cst is thus constructed. In addition, the exposed second metal pattern 234b of FIG. 9J contacts the common electrode connection wiring 217c and the first contact hole CH1 and is alternately arranged with the pixel electrode 260. ). That is, the pixel region P has a structure in which the first and second common electrodes (not shown), the third common electrode 250 and the pixel electrode 260 therebetween are alternately arranged in parallel while being spaced apart from each other in parallel. The liquid crystal layer (not shown) is driven by a horizontal electric field formed between them by the application of a voltage, thereby realizing an image having an improved viewing angle.

Although not shown, a gate pad is formed of the same material as the gate line (not shown) at one end of the gate line (not shown), and a gate pad terminal formed of the same material as the pixel electrode 260 is formed thereon. To form a gate pad portion. In addition, a data pad is formed at one end of the data line (not shown) and made of the same material as the gate line (not shown), and a data pad terminal made of the same material as the pixel electrode 260 is formed thereon. It forms a pad part. That is, the gate pad portion and the data pad portion have the same stacked structure.

By the above process, the array substrate for the COT structure transverse electric field type liquid crystal display device according to the exemplary embodiment of the present invention is completed. The lower substrate, which is an array substrate, is bonded to the upper substrate on which the black matrix is formed and the liquid crystal layer therebetween to form a liquid crystal display device. The black matrix serves to block a non-display area such as a thin film transistor of a lower substrate, and unlike the prior art of FIG. 1, since the semiconductor layer protruding from the data line does not exist, the width of the black matrix can be narrowed. Therefore, the opening ratio is increased.

Here, in order to maintain the thickness (cell gap) of the liquid crystal layer uniformly before bonding of the upper and lower substrates, a step of forming columnar column spacers on any one of the upper and lower substrates is included.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art various modifications and changes of the present invention without departing from the spirit and scope of the present invention described in the claims below I can understand that you can.

1 is a plan view illustrating an array substrate of a COT structure hierarchical liquid crystal display device according to the related art.

2A to 2G are cross-sectional views of manufacturing processes of portions cut along the line II-II of FIG. 1.

3 is a schematic plan view of an array substrate for a COT structure liquid crystal display according to an exemplary embodiment of the present invention.

4A to 4K are cross-sectional views of manufacturing processes taken along the line IV-IV of FIG. 3.

5A to 5K are cross-sectional views of manufacturing processes taken along the line V-V of FIG. 3.

6A through 6K are cross-sectional views of manufacturing processes taken along the line VI-VI of FIG. 3.

7 is a schematic plan view of an array substrate for a COT structure transverse field type liquid crystal display according to an exemplary embodiment of the present invention.

8A to 8K are cross-sectional views of manufacturing processes taken along the line VIII-VIII of FIG. 7.

9A to 9K are cross-sectional views of manufacturing processes of portions cut along the line IX-IX of FIG. 7, respectively.

<Description of the symbols for the main parts of the drawings>

114 and 214: gate electrodes 124 and 224: semiconductor layer

142, 242: source electrode 144, 244: drain electrode

Claims (25)

Forming a gate wiring extending in one direction on the substrate, a gate electrode connected to the gate wiring, and a common wiring spaced apart in parallel with the gate wiring; Forming a gate insulating film on a substrate on which the gate wiring, the gate electrode and the common wiring are formed; Forming a pure amorphous silicon pattern and an impurity amorphous silicon pattern having a flat top surface corresponding to the gate electrode on the gate insulating layer; Forming a color filter pattern on the substrate on which the impurity amorphous silicon pattern is formed; Forming a first passivation layer covering the color filter pattern and exposing the impurity amorphous silicon pattern; A source electrode and a drain electrode spaced apart from each other on the exposed impurity amorphous silicon pattern, a data line connected to the source electrode and defining a pixel region crossing the gate line, and connected to the drain electrode and the pixel region. Forming an extended pixel electrode and a first common electrode connected to the common wiring and arranged alternately in parallel with the pixel electrode; Method of manufacturing an array substrate for a COT structure liquid crystal display device comprising a. The method of claim 1, The forming of the gate wiring, the gate electrode and the common wiring may include: Forming second and third common electrodes extending from both ends of the common wiring and parallel to the data lines, and a common electrode connecting wiring connecting the second and third common electrodes; And the first common electrode is connected to the common electrode connection wiring. The method of claim 2, Forming the pure amorphous silicon pattern and the impurity amorphous silicon pattern, Forming a pure amorphous silicon layer, an impurity amorphous silicon layer, and a photoresist layer on the gate insulating film; By partially removing the photoresist layer, a first photoresist pattern having a first thickness and corresponding to the gate electrode and a second photoresist pattern having a second thickness smaller than the first thickness are formed, and the common Exposing the impurity amorphous silicon layer on the electrode connection wiring; Exposing the common electrode connection wiring by removing the exposed impurity amorphous silicon layer, the pure amorphous silicon layer and the gate insulating layer below the exposed impurity amorphous silicon layer; A third photoresist pattern having a third thickness smaller than the first thickness from the first photoresist pattern corresponding to the gate electrode by ashing the first and second photoresist patterns to remove the second photoresist pattern Forming a; Forming a contact hole exposing the common electrode connection wiring by removing the impurity amorphous silicon layer exposed to the outside of the third photoresist pattern, the pure amorphous silicon layer and the gate insulating layer thereunder. Method for manufacturing array substrate for COT structure liquid crystal display device. The method of claim 3, wherein Forming the first protective layer, And removing the first protective layer corresponding to the contact hole to expose the common electrode connection wiring, wherein the first common electrode is connected to the common electrode connection wiring through the contact hole. A method of manufacturing an array substrate for a structure liquid crystal display device. The method of claim 2, The first common electrode is positioned between the second and third common electrodes, and the pixel electrode is positioned between the first and second common electrodes and between the first and third common electrodes. A method of manufacturing an array substrate for a structure liquid crystal display device. The method of claim 1, Forming the first protective layer, Stacking an insulating layer using silicon nitride on the substrate on which the color filter pattern is formed; Coating and patterning a photoresist on the insulating layer to form a photoresist pattern covering the color filter; Dry etching the insulating layer exposed to the outside of the photoresist pattern using a gas containing SF6 (sulfur hexafluoride) and O2; Removing the photoresist pattern; and manufacturing the array substrate for the liquid crystal display device of the COT structure. The method of claim 1, Forming the source and drain electrodes, the data line, the pixel electrode, and the first common electrode may include: Stacking a first metal layer and a second metal layer on the first protective layer; Removing the first and second metal layers corresponding to the central portion of the impurity amorphous silicon pattern to form the source and drain electrodes and the data line on the impurity amorphous silicon pattern, and between the pixel electrode and the first common electrode. Correspondingly removing the first and second metal layers; Removing the impurity amorphous silicon pattern exposed between the source and drain electrodes to expose the pure amorphous silicon pattern thereunder; And removing the second metal layer to expose the first metal layer corresponding to a portion where the pixel electrode and the first common electrode are to be formed, thereby exposing the first metal layer. The method of claim 7, wherein Forming and patterning a photoresist layer on the second metal layer to form a first photoresist pattern having a first thickness corresponding to a portion where the pixel electrode and the first common electrode are to be formed, and the source and drain electrodes And a second photoresist pattern having a second thickness smaller than the first thickness, corresponding to a portion where the data line is to be formed, and formed in a central portion of the impurity amorphous silicon pattern and an area between the pixel and the first common electrode. And exposing the second metal layer with respect to the COT structure array substrate. The method of claim 8, After exposing the pure amorphous silicon pattern, Ashing the first and second photoresist patterns to remove the second photoresist pattern and to form a third photoresist pattern from the first photoresist pattern; Forming a second protective layer using an inorganic insulating material on an entire surface of the substrate including the third photoresist pattern; And simultaneously removing the third photoresist pattern and the second passivation layer thereon by a lift-off method. The method of claim 9, Forming the second protective layer, A method of manufacturing an array substrate for a COT structure liquid crystal display device comprising depositing silicon nitride using a sputter. The method of claim 7, wherein And the first metal layer is made of a material of molybdenum-titanium alloy, molybdenum, chromium, or titanium, and the second metal layer is made of copper. The method of claim 11, Removing the second metal layer to expose the first metal layer, Removing is performed using a mixed acid solution of phosphoric acid-acetic acid-nitric acid (PAN) using a mixed acid solution of COP structure liquid crystal display device. The method of claim 7, wherein The forming of the gate wiring may include forming a gate pad connected to one end of the gate wiring and a data pad positioned at one end of the data wiring. The forming of the source and drain electrodes, the data line, the pixel electrode, and the first common electrode may include contacting the gate pad with a gate pad terminal formed of a first metal layer and connected to the data line. And forming a data pad terminal made of the first metal layer in contact with the data pad. The method of claim 1, And wherein the impurity amorphous silicon pattern and the pure amorphous silicon pattern have a cross-sectional area equal to or smaller than that of the gate electrode and are completely overlapped with each other. Forming a gate wiring extending in one direction on the substrate and a gate electrode connected to the gate wiring; Forming a gate insulating film on a substrate on which the gate wiring and the gate electrode are formed; Forming a pure amorphous silicon pattern and an impurity amorphous silicon pattern on the gate insulating layer, corresponding to the gate electrode; Forming a color filter pattern on the substrate on which the impurity amorphous silicon pattern is formed; Forming a first passivation layer covering the color filter pattern and exposing the impurity amorphous silicon pattern; A source electrode and a drain electrode spaced apart from each other on the exposed impurity amorphous silicon pattern, a data line connected to the source electrode and defining a pixel region crossing the gate line, and connected to the drain electrode and the pixel region. Forming an extended pixel electrode, And removing the impurity amorphous silicon pattern and exposing the pure amorphous silicon pattern by using the spaced source and drain electrodes as a mask to expose the pure amorphous silicon pattern. The method of claim 15, Forming the pure amorphous silicon pattern and the impurity amorphous silicon pattern, Forming a pure amorphous silicon layer, an impurity amorphous silicon layer, and a photoresist layer on the gate insulating film; Partially removing the photoresist layer to form a photoresist pattern corresponding to the gate electrode; And removing the impurity amorphous silicon layer exposed to the outside of the photoresist pattern, the pure amorphous silicon layer and the gate insulating layer below the impurity amorphous silicon layer. The method of claim 15, Forming the first protective layer, Stacking an insulating layer using silicon nitride on the substrate on which the color filter pattern is formed; Coating and patterning a photoresist on the insulating layer to form a photoresist pattern covering the color filter; Dry etching the insulating layer exposed to the outside of the photoresist pattern using a gas including SF ₆ (sulfur hexafluoride) and O ₂ ; Removing the photoresist pattern; and manufacturing the array substrate for the liquid crystal display device of the COT structure. The method of claim 15, The forming of the source and drain electrodes, the data line, and the pixel electrode may include: Stacking a first metal layer and a second metal layer on the first protective layer; Removing the first and second metal layers corresponding to a central portion of the impurity amorphous silicon pattern to form the source and drain electrodes and the data line on the impurity amorphous silicon pattern; Removing the impurity amorphous silicon pattern exposed between the source and drain electrodes to expose the pure amorphous silicon pattern thereunder; And exposing the first metal layer by removing the second metal layer corresponding to a portion where the pixel electrode is to be formed. The method of claim 18, The forming of the source and drain electrodes and the data line may include: Forming and patterning a photoresist layer on the second metal layer to form a first photoresist pattern having a first thickness corresponding to a portion where the pixel electrode is to be formed, and forming the source and drain electrodes and the data line. Forming a second photoresist pattern having a second thickness smaller than the first thickness corresponding to the portion to be formed, and exposing the second metal layer to the central portion of the impurity amorphous silicon pattern and the pixel electrode. A method of manufacturing an array substrate for a COT structure liquid crystal display device. The method of claim 19, Ashing the first and second photoresist patterns to remove the second photoresist pattern and to form a third photoresist pattern from the first photoresist pattern; Forming a second protective layer using an inorganic insulating material on an entire surface of the substrate including the third photoresist pattern; And simultaneously removing the third photoresist pattern and the second passivation layer thereon by a lift-off method. The method of claim 20, Forming the second protective layer, A method of manufacturing an array substrate for a COT structure liquid crystal display device comprising depositing silicon nitride using a sputter. The method of claim 18, And the first metal layer is made of one of molybdenum-titanium alloys, molybdenum, chromium, and titanium, and the second metal layer is made of copper. The method of claim 22, Removing the second metal layer to expose the first metal layer, Removing is performed using a mixed acid solution of phosphoric acid-acetic acid-nitric acid (PAN) using a mixed acid solution of COP structure liquid crystal display device. The method of claim 18, The forming of the gate wiring may include forming a gate pad connected to one end of the gate wiring and a data pad positioned at one end of the data wiring. The forming of the source and drain electrodes, the data line, and the pixel electrode may include contacting the gate pad and a gate pad terminal formed of a first metal layer, and contacting the data pad while being in contact with the data line. 1. A method of manufacturing an array substrate for a liquid crystal display device, comprising: forming a data pad terminal comprising a metal layer. The method of claim 15, And wherein the impurity amorphous silicon pattern and the pure amorphous silicon pattern have a cross-sectional area equal to or smaller than that of the gate electrode and are completely overlapped with each other.

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