KR20090047942A - Apparatus and method for performance mobile platform on-chip bus - Google Patents

Abstract

The present invention relates to an on-chip bus, and in a system using a bus structure, a master outputting a signal indicating direct storage and a first slave receiving the signal indicating the direct storage to output the first slave. It includes a first scheduler that schedules data to be directly forwarded to the second slave to reduce the time the master, such as CPU, DMAC involved in data transmission, so that the master can perform other tasks in advance. Therefore, there is an advantage that can improve the overall system performance.

On-Chip BUS, RDATA, WDATA, D-WAR.

Description

On-chip bus device and method for mobile platform {APPARATUS AND METHOD FOR PERFORMANCE MOBILE PLATFORM ON-CHIP BUS}

The present invention relates to an apparatus and method for improving the performance of an on-chip bus used in a high-performance mobile platform, and more particularly, a master-slave (Master-slave) widely used in a system-on-chip platform. Slave) In the bus structure, the time spent by the master for data transfer by enabling a direct slave-to-slave transaction from the slave to the data transfer between the slaves without relaying the master. The present invention relates to a new high-performance bus protocol method and apparatus for enabling high-speed data transmission by reducing workload and power consumption, and also reducing time required for data transmission.

The bus structure used in most conventional mobile platforms is based on the Advanced Microprocessor Bus Architecture (AMBA) protocol developed by ARM, which is the latest version of the AMBA 3.0-Advanced Extensible Interface (AXI) protocol. It is designed for (Embedded) platform and is gradually applied to high performance mobile platform, and commercial products using this are being released one by one.

All conventional embedded bus structures, such as AMBA buses, are divided into master buses and slave buses. The subject that initiates the read or write transaction is called the master, and the object that responds to the master's transaction is called the slave.

Thus, all bus transactions occur between master and slave. That is, the master initiates a read or write transaction, reads data from the slave's address, and transfers it to the master or writes the data to the slave's address.

1 is a diagram illustrating a conventional bus structure.

Referring to FIG. 1, FIG. 1 illustrates a bus structure implementing the AXI protocol. The AXI bus provides five channels: (1) Read address (AR channel), (2) Read data (RD channel), (3) Write address (AW channel), (4) Write data (WD channel), (5) Write response (B channel).

In the case of a read transaction, the master sends a read address to the slave through the AR channel and receives read data from the slave through the RD channel. In the case of a write transaction, the master sends the write address through the AW channel and the write data through the WD channel to the slave. After the slave completes the write operation, it informs the master that the write operation was successfully completed through the B channel. report.

Each of the channels can be performed independently of both time and space. Therefore, each channel is completely separated within the bus structure.

All transactions in the existing bus structure can be thought of as read or write transactions from master to slave. The pattern of bus transactions that is often required on high-performance mobile platforms and the cause of performance bottlenecks is the movement of data from one address area of a memory slave (DRAM, SRAM, etc.) to another address area of the same memory, or on a memory slave. To move a specific set of data to another slave (USB, PCMCIA, etc.).

As such, data movement from slave to slave occurs very frequently, and for this purpose, the role of the master is required. In other words, the master reads the data from the source slave, receives it, and writes it back to the destination slave. To do this, the master initiates a series of read and write transactions.

Looking at the operation on the bus 110 for each channel, in the situation where the master 100 moves the data of the slave 1 (140) to the slave 2 (150). First, the master 100 transmits a read address to the slave 1 140 through an AR channel.

Thereafter, the master 100 receives read data from the slave 1 140 and stores the read data in the internal register. The master 100 starts an operation for writing the stored data to the slave 2 150.

In this case, the master 100 transmits a write address through the AW channel and write data through the WD channel. Both channels can operate simultaneously. The slave 2 150 performs an internal write operation and, when completed, notifies the master 100 of completion of writing through the B channel.

In the existing bus system, the master 100 transmits the data of the slave 1 140 to the slave 2 150 using each of the five channels in this order. If this is arranged in chronological order for each of the master 100 and the slaves 140 and 150, it may be represented as shown in FIG. 2.

In FIG. 1, the multiplexers 118 and 134 select one of the slaves 140 and 150 under the control of the schedulers 116 and 132, and receive data from the selected slave. The demultiplexers 114, 126, and 130 select one of the slaves 140 and 150 under the control of the schedulers 112, 124, and 128, and output data to the selected scheduler.

The thick line in FIG. 1 represents a process currently in operation, and indicates that data output from the master 100 is output to one of the slaves 140 and 150.

2 is a diagram illustrating a conventional bus operation process.

Referring to FIG. 2, as a result of a read process from the slave 1 220 initialized by the master 210, data read in the register of the master 210 is stored, and then initialized by the master 210. As a result of the writing process to the slave 2 230, the data stored in the register of the master 210 is stored in the slave 2 230.

In the case of the mobile platform bus system, independent and continuous read and write transactions of a master-CPU or a direct memory access controller (DMAC) to perform a simple data transfer operation from a slave to a slave frequently occur in an embedded system. I'm using.

This also works in the case of data movement in the same slave (Memory). This conventional technique has the following problems.

First, in performing transfers between slaves, the master performs two read / write transactions each time. This increases the workload on the master and increases the frequency of bus use. DMAC is used to reduce the work load of the CPU. Since the DMAC performs read and write transactions in the same manner as the CPU, there is no performance improvement of the transmission itself, but there is a problem that increases the cost.

Secondly, the flow of data is transferred from the source slave to the master and then back to the destination slave. In other words, the data movement path is unnecessarily via the master. As a result, unnecessary latency and power are wasted.

In order to solve the above two problems, there is a solution for embedding a built-in DMAC inside the destination slave, but this has been applied to the bus system and the expansion of logic / buffer for additional DMAC functions in the slave. An additional master interface is required. Therefore, it requires power consumption and cost (area). In addition, in the case of a slave, a pre-designed IP (Intellectual Property) is often purchased, and there is a problem in that a slave having a special built-in DMAC function must be separately supplied.

An object of the present invention is to provide an on-chip bus apparatus and method for a mobile platform.

Another object of the present invention is to simplify read and write transactions of an unnecessary master for data transmission between different slaves or within the same slave in an existing bus system, thereby reducing the workload and transmission latency of the master, and a high performance mobile platform. An apparatus and method for reducing data and power and area costs are provided.

According to a first aspect of the present invention, in a system using a bus structure, a master outputting a signal indicating direct storage and a data received by the first slave receiving the signal indicating the direct storage are output. And a first scheduler for scheduling to forward the data directly to the second slave.

According to a second aspect for achieving the object of the present invention, in the method of directly storing data in a system using a bus structure, after the first step and the first step of outputting a signal indicating direct storage by the master, A second process of outputting a write address indicating an address to be stored by the master to the second slave to the second slave and a scheduler receiving a signal indicating the direct storage after the second process may output data output by the first slave. When the third process of scheduling to forward to the second slave directly and the fourth process of storing the forwarded data and the fourth process, the second slave outputs a response signal to the master. And a fifth process.

By using the D-WAR transaction of the present invention, simple data transfer between slaves can be performed quickly. As a result, data transfer time can be reduced on high-performance mobile platforms. In addition, it does not go through the internal resistor of the master, there is an advantage that can reduce the power consumption.

In addition, the present invention reduces the time that the master such as the CPU, DMAC involved in the data transfer, the master can perform other tasks in advance. Therefore, there is an advantage that can improve the overall system performance.

In addition, the present invention has the advantage that it can be applied even when moving data in the same slave.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Hereinafter, the present invention will be described on-chip bus apparatus and method for a mobile platform.

The present invention proposes a transaction protocol and an apparatus configuration therefor that enable direct data transfer between slaves.

Consolidate the continuous and separately executed read and write transactions initiated by the existing master into a new Direct Write After Read (D-WAR) transaction. That is, direct data transfer from the source slave to the destination slave is possible without the master's intervention.

3 illustrates a structure of a bus according to an exemplary embodiment of the present invention.

Referring to FIG. 3, in the bus 300 structure of the present invention, a D-WAR signal is added to the existing bus structure. That is, a 1-bit 'D-WAR' signal is added to the master interface (indicated by the dashed line). A path is added (indicated by the dashed line) in which the signal of the RD channel of the source slave is multiplexed to the WD channel of the destination slave.

The D-WAR signal is output to the scheduler 320. When the scheduler 320 receives the D-WAR signal, the multiplexer 322 multiplexes data output from the slave1 340 to demultiplexer 326. The slave 2 350 outputs the data to slave 2 350, and the slave 2 350 stores the received data.

In the process, the slave 2 350 receives a write address output from the master 300 through an AW channel, stores data in the write address, and when the storing process is completed, a response signal is transmitted through the B channel. Output to the master (300).

The functions of the schedulers 312, 316, 324, 328, 332 and the functions of the multiplexers 318, 334 and the demultiplexers 314, 326, 330 are the same as before. However, while the output data of the slave 1 340 is stored in the slave 2 350, the scheduler 324 is instructed to select the slave 2 350 from the master 300, and the demultiplexer 326 The data output from the multiplexer 322 is demultiplexed to the slave 2 350 under the control of the scheduler 324. All the schedulers operate under the control of the master 300.

4 is a diagram illustrating a bus operation process according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the master 410 outputs a read address indicating the address of the slave 1 420 in which data to be moved to the slave 2 430 is stored, to the slave 1 410. In this case, the AR channel is used.

Thereafter, the slave 1 420 performs a read operation on the read address, and outputs the data read by the slave 1 420 to the master 410, in this case, using an RD channel.

Simultaneously with the above process, the master 410 outputs a D-WAR signal. The master 410 outputs a write address indicating an address to be stored in the slave 2 430 to the slave 2 430. In this case, use the AW channel.

Thereafter, the data output from the slave 1 420 to the master 410 is directly forwarded to the slave 2 430. The forwarding process is performed by the multiplexer 322 and the demultiplexer 326 under the control of the scheduler 328, 324 of FIG. 3 of the master 410. In this case, use the WD channel.

The slave 2 430 performs a write operation on the forwarded data and stores the data. When the write operation is completed, the slave 2 430 outputs a response signal to the master 410. In this case, the B channel is used.

5 is a flowchart illustrating a bus operation process according to an exemplary embodiment of the present invention.

Referring to FIG. 5, the master outputs a read address indicating the address of slave 1 in which data to be moved to slave 2 is stored (step 510). In this case, an AR channel is used.

Thereafter, the slave 1 performs a read operation on the read address (step 520), and outputs the data read by the slave 1 to the master (step 530). In this case, the RD channel is used.

Simultaneously with the above process, the master outputs a D-WAR signal (step 515), and outputs a write address indicating an address to be stored in the slave 2 to the slave 2. In this case, the AW channel is used (step 525).

Here, before the process of step 530 is finished, it is preferable that the process of steps 515 and 525 ends first.

Thereafter, the slave 1 directly forwards the data output to the master to the slave 2 (step 535). In this case, use the WD channel.

The slave 2 performs a write operation on the forwarded data and stores it in operation 540.

When the write operation is completed, the slave 2 outputs a response signal to the master (step 545). In this case, the B channel is used.

It is also possible for the master to selectively store data output by the slave 1 in the above process in a register.

The structure of the present invention is applicable not only to the number of slaves but also to three or more. That is, if the output of the source slave device can be connected to the input of the destination slave device.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described. However, various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

1 is a view showing a conventional bus structure,

2 is a view illustrating a conventional bus operation process;

3 is a view showing the structure of a bus according to an embodiment of the present invention;

4 is a diagram illustrating a bus operation process according to an embodiment of the present invention;

5 is a flowchart illustrating a bus operation process according to an exemplary embodiment of the present invention.

Claims (11)

In a system using a bus structure, A master that outputs a signal indicating direct storage, And a first scheduler configured to receive the signal indicative of the direct storage and schedule to directly forward data output from the first slave to the second slave. The method of claim 1, The master outputs a read address indicating an address of the first slave, in which data to be moved to the second slave, to the first slave, and a write address indicating an address to be stored in the second slave, to the second slave. Device characterized in that. The method of claim 2, And the first slave outputs data stored for the read address to the master. The method of claim 2, And the second slave stores the forwarded data at the write address, and outputs a response signal to the master when the storage is completed. The method of claim 1, And the signal indicating the direct storage is a direct write after read (D-WAR) signal. The method of claim 1, The first scheduler controls a multiplexer to multiplex data from the first slave. The method of claim 1, And a second scheduler for controlling the demultiplexer to demultiplex and forward the data that the first scheduler has multiplexed to the second slave. In a method of directly storing data in a system using a bus structure, A first process of outputting a signal directly instructed by the master to store; A second process of outputting, to the second slave, a write address indicating an address to be stored in the second slave after the first process; A third step of scheduling after receiving the signal indicating the direct storage, the scheduler receiving the first slave data to forward data output from the first slave to a second slave; The second slave stores a forwarded data; And when the fourth process is completed, the second slave outputs a response signal to the master. The method of claim 8, Before the first process, A sixth process of outputting, to the first slave, a read address indicating an address of the first slave in which data to be moved by the master to the second slave is stored; And a seventh process of outputting, by the first slave, data stored for the read address to the master after the sixth output process. The method of claim 8, The signal indicating the direct storage is a direct write after read (D-WAR) signal. The method of claim 8, The third process is Multiplexing the data from the first slave by the scheduler by controlling the multiplexer; And demultiplexing the multiplexed data by another scheduler to control the demultiplexer and forwarding the demultiplexed data to the second slave.

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