KR101423675B1 - Apparatus and method for performance mobile platform on-chip bus - Google Patents

Apparatus and method for performance mobile platform on-chip bus Download PDF

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Publication number
KR101423675B1
KR101423675B1 KR1020070114070A KR20070114070A KR101423675B1 KR 101423675 B1 KR101423675 B1 KR 101423675B1 KR 1020070114070 A KR1020070114070 A KR 1020070114070A KR 20070114070 A KR20070114070 A KR 20070114070A KR 101423675 B1 KR101423675 B1 KR 101423675B1
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KR
South Korea
Prior art keywords
slave
master
data
signal
write
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KR1020070114070A
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Korean (ko)
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KR20090047942A (en
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이강민
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삼성전자주식회사
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package

Abstract

The present invention relates to an on-chip bus (BUS). In a system using a bus structure, a master for outputting a signal for direct storage and a signal for direct storage are received and output from the first slave And a first scheduler for scheduling the data to be directly forwarded to the second slave, so that the master can perform another task in advance by reducing the time involved in data transmission by a master such as a CPU or a DMAC. Therefore, there is an advantage that overall system performance can be improved.
On-Chip BUS, RDATA, WDATA, D-WAR.

Description

[0001] APPARATUS AND METHOD FOR PERFORMANCE MOBILE PLATFORM ON-CHIP BUS FOR MOBILE PLATFORM [0002]

The present invention relates to an apparatus and method for improving the performance of an on-chip bus used in a high-performance mobile platform, and more particularly, to a master- Slave) bus structure enables direct slave-to-slave transaction to transfer data between slaves directly from the slave without relaying the master, so that the time that the master consumes for data transfer (Bus Protocol) method and apparatus for the same, which enable high-speed data transmission by reducing workload and power consumption, and by reducing time required for data transmission.

The AMBA 3.0 - Advanced Extensible Interface (AXI) protocol, which is the most recent version on the AMBA bus, is a high - performance embedded system that is based on the Advanced Microprocessor Bus Architecture (AMBA) (Embedded) platform and is being applied gradually to high performance mobile platform, and commercial products using it are being introduced one by one.

All conventional embedded bus architectures, such as the AMBA bus, are divided into a master bus and a slave bus. A principal that initiates a read or write transaction is called the master, and the object that responds to the master's transaction is called the slave.

Thus, all bus transactions are made between master and slave. That is, the master initiates a read or write transaction, reads data from the corresponding address of the slave and transfers it to the master, or writes the data to the corresponding address of the slave.

1 is a diagram showing a conventional bus structure.

Referring to FIG. 1, FIG. 1 illustrates a bus structure implementing the AXI protocol. The AXI bus provides the following five channels. (1) Read address (AR channel), (2) Read data (RD channel), (3) Write address (AW channel), (4) Write data (WD channel), and (5) Write response (B channel).

For a read transaction, the master forwards the read address to the slave via the AR channel and receives the read data from the slave via the RD channel. Write transaction, the master sends the write address to the slave via the AW channel and the write data to the slave through the WD channel. After the slave completes the write operation, the master notifies the master that the write operation has been completed successfully on the B channel report.

Each of the above channels can be performed independently of both time and space. Therefore, each channel in the bus structure is completely isolated.

All transactions in the existing bus structure can be regarded as read or write transactions from the master to the slave. Patterns that are the main bus transaction patterns required on high-performance mobile platforms and cause performance bottlenecks are those that move data from one address area of a memory slave (DRAM, SRAM, etc.) to another address area of the same memory, To move a specific set of data to another slave (USB, PCMCIA, etc.).

Data transfer from slave to slave occurs very frequently, and a master role is required for this. That is, the master reads the corresponding data from the source slave, receives it, and writes it back to the destination slave. To do this, the master initializes a series of consecutive read and write transactions.

If the master 100 moves the data of the slave 1 140 to the slave 2 150, First, the master 100 transmits a read address to the slave 1 140 through an AR channel.

Then, the master 100 receives the read data from the slave 1 140 and stores it in the internal register. Then, the master 100 starts an operation to write the stored data to the slave 2 (150).

At this time, the master 100 delivers the write address through the AW channel and transmits the write data through the WD channel. Both channels can operate simultaneously. The slave 2 150 performs an internal write operation and, upon completion, notifies the master 100 of the completion of writing via the B channel.

In the conventional bus system, the master 100 transmits data of the slave 1 140 to the slave 2 150 using five channels in this order. 2, the master 100 and the slaves 140 and 150 may be arranged in time order.

1, the multiplexers 118 and 134 select one of the slaves 140 and 150 under the control of the schedulers 116 and 132 and receive data from the selected slave. The demultiplexers 114, 126 and 130 select one of the slaves 140 and 150 under the control of the schedulers 112, 124 and 128 and output the data to the selected scheduler.

The bold line in FIG. 1 indicates a current operation, and indicates that data output by the master 100 is output to one of the slaves 140 and 150.

2 is a diagram illustrating a conventional bus operation process.

Referring to FIG. 2, data read into a register of the master 210 is stored as a result of a reading process from a slave 1 220 initialized by the master 210, As a result of the writing process to the slave 2 230, the data stored in the register of the master 210 is stored in the slave 2 230.

In the above-mentioned mobile platform bus system, in order to perform a simple data transfer operation from a slave to a slave frequently occurring in an embedded system, an independent continuous read transaction and a write transaction of a master-CPU or a direct memory access controller (DMAC) .

This is also applied to the case of data movement in the same slave (Memory). Such conventional techniques have the following problems.

First, in performing a transfer between slaves, the master performs two read / write transactions each time. Therefore, the workload of the master increases, and the number of buses used increases. DMAC is used to reduce the work load of the CPU. Since the DMAC also performs the read and write transactions in the same manner as the CPU, the performance of the transfer itself is not improved, but the cost increases.

Second, the flow of data is transferred from the source slave to the master, and then back to the destination slave. That is, the movement path of the data is unnecessarily passed through the master. There is a problem that unnecessary latency and power are wasted.

In order to solve the above two problems, there is a solution in which a built-in DMAC is built in the destination slave, but it is necessary to add a logic / buffer for the additional DMAC function in the slave, An additional master interface is required. Therefore, it requires power consumption and cost (area). Also, in the case of a slave, most of the cases of purchasing a pre-designed intellectual property (IP), there is a problem that a slave having such a special built-in DMAC function must be supplied separately.

It is an object of the present invention to provide an on-chip bus device and method for a mobile platform.

It is another object of the present invention to simplify read and write transactions of unnecessary masters for data transfer between different slaves or in the same slave in an existing bus system to reduce the task load and transmission delay time of the master, And to reduce the power and area cost.

According to a first aspect of the present invention, there is provided a system using a bus structure, comprising: a master for outputting a signal instructing direct storage and a signal for direct storage; To the second slave directly to the first slave.

According to a second aspect of the present invention, there is provided a method of directly storing data in a system using a bus structure, the method comprising: a first step of outputting a signal instructing a direct storage by a master; And outputting a write address indicating the address to be stored in the second slave to the second slave by the master and a scheduler receiving the signal indicating the direct storage in the second step, A third step of directly scheduling forwarding to the second slave, a fourth step of storing forwarding data, and a fourth step of, when the fourth step is completed, the second slave outputs a response signal to the master And a fifth step.

By using the D-WAR transaction of the present invention, simple data transmission between slaves can be performed quickly. This can shorten data transfer time on high-performance mobile platforms. In addition, since it does not go through the internal register of the master, there is an advantage that power consumption can be reduced.

Further, according to the present invention, the time required for the master such as the CPU and the DMAC to participate in the data transfer is reduced, so that the master can perform another task in advance. Therefore, there is an advantage that overall system performance can be improved.

Further, the present invention is advantageous in that it can be applied to data movement in the same slave.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

Hereinafter, the present invention will be described on an on-chip bus device and method for a mobile platform.

The present invention proposes a transaction protocol that enables direct data transfer between a slave and a slave, and an apparatus configuration therefor.

Consolidate continuous and separately performed read and write transactions that were initiated by an existing master into a single new read-after-write (D-WAR) transaction. That is, it enables direct data transfer from the source slave to the destination slave without the intervention of the master.

3 shows the structure of a bus according to an embodiment of the present invention.

Referring to FIG. 3, the bus 300 of the present invention adds a D-WAR signal to an existing bus structure. That is, a 1-bit 'D-WAR' signal is added to the master interface (indicated by the dotted line). And a path is added (indicated by a dotted line) in which the signal of the RD channel of the source slave is multiplexed to the WD channel of the destination slave.

The D-WAR signal is output to the scheduler 320. When the D-WAR signal is received, the scheduler 320 multiplexes the data output from the slave 1 340 by the multiplexer 322 and outputs the multiplexed data to the demultiplexer 326 To the slave 2 350, and the slave 2 350 stores the received data.

In the above process, the slave 2 350 receives the write address output from the master 300 through the AW channel, stores the data in the write address, and upon completion of the storing process, And outputs it to the master 300.

The functions of the schedulers 312, 316, 324, 328 and 332 and the functions of the multiplexers 318 and 334 and the demultiplexers 314, 326 and 330 are the same as those of the prior art. The scheduler 324 instructs the master 300 to select the slave 2 350 while the output data of the slave 1 340 is stored in the slave 2 350. The demultiplexer 326 And demultiplexes the data output from the multiplexer 322 to the slave 2 350 under the control of the scheduler 324. [ All of the above schedulers operate under the control of the master 300.

4 is a diagram illustrating a bus operation process according to an embodiment of the present invention.

4, the master 410 outputs a read address to the slave 1 410 indicating the address of the slave 1 420 in which data to be transferred to the slave 2 430 is stored. In this case, an AR channel is used.

Then, the slave 1 420 performs a read operation on the read address, and the slave 1 420 outputs the read data to the master 410. In this case, an RD channel is used.

The master 410 outputs a D-WAR signal to the slave 2 430. The master 410 outputs a write address indicating the address to be stored in the slave 2 430 to the slave 2 430. [ In this case, use the AW channel

Then, the data output from the slave 1 420 to the master 410 is directly forwarded to the slave 2 430. The forwarding process is performed by the multiplexer 322 and the demultiplexer 326 under the control of the scheduler 328, 324 of FIG. 3 of the master 410. In this case, the WD channel is used.

The slave 2 430 performs a write operation on the forwarded data and stores the data. When the writing operation is completed, the slave 2 430 outputs a response signal to the master 410. In this case, the B channel is used.

5 is a flowchart illustrating a bus operation process according to an embodiment of the present invention.

Referring to FIG. 5, the master outputs a read address indicating the address of the slave 1 storing data to be transferred to the slave 2 to the slave 1 (operation 510). In this case, an AR channel is used.

Then, the slave 1 performs a read operation on the read address (operation 520), and outputs data read by the slave 1 to the master (operation 530). In this case, an RD channel is used.

At the same time as above, the master outputs a D-WAR signal (step 515) and outputs a write address indicating the address to be stored in the slave 2 to the slave 2. In this case, the AW channel is used (step 525).

Here, it is preferable that the processes of steps 515 and 525 are completed before the process of step 530 is completed.

Thereafter, the slave 1 forwards the data output to the master directly to the slave 2 (step 535). In this case, the WD channel is used.

The slave 2 performs a write operation on the forwarded data and stores it (operation 540).

When the writing operation is completed, the slave 2 outputs a response signal to the master (Step 545). In this case, the B channel is used.

It is also possible for the master to selectively store the data output by the slave 1 in the above process.

The structure of the present invention is applicable not only to the number of slaves but also to three or more slaves. That is, it is possible to connect the output of the source slave device to the input of the destination slave device.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but is capable of various modifications within the scope of the invention. Therefore, the scope of the present invention should not be limited by the illustrated embodiments, but should be determined by the scope of the appended claims and equivalents thereof.

1 shows a conventional bus structure,

2 is a diagram illustrating a conventional bus operation process,

3 is a diagram illustrating a structure of a bus according to an embodiment of the present invention,

4 is a diagram illustrating a bus operation process according to an embodiment of the present invention,

5 is a flowchart illustrating a bus operation process according to an embodiment of the present invention.

Claims (11)

  1. In a system using a bus structure,
    A master outputting a signal instructing direct storage so as to store the data stored in the first slave as the second slave without passing through the master;
    And a first scheduler for receiving a signal indicating direct storage and scheduling to forward data output from the first slave directly to the second slave,
    Wherein the master outputs a read address to the first slave and a write address to the second slave for the same time interval in order to integrate the read transaction and the write transaction into one transaction.
  2. delete
  3. The method according to claim 1,
    Wherein the first slave outputs data stored for the read address to the master.
  4. The method according to claim 1,
    Wherein the second slave stores the forwarded data in the write address and outputs a response signal to the master when the storage is completed.
  5. The method according to claim 1,
    Wherein the signal for direct storage is a Direct-Write After Read (D-WAR) signal.
  6. The method according to claim 1,
    Wherein the first scheduler controls the multiplexer to multiplex data from the first slave.
  7. The method according to claim 1,
    Further comprising: a second scheduler for controlling the demultiplexer to demultiplex and forward the data to the first slave, the data being multiplexed by the first scheduler.
  8. A method for directly storing data in a system using a bus structure,
    A first step of outputting a signal instructing direct storage so that the master stores the data stored in the first slave as the second slave without passing through the master;
    A second step of outputting a read address to the first slave and a write address to the second slave during the same time interval in order to integrate the read transaction and the write transaction into one transaction after the first process; and,
    A third step of scheduling the scheduler to forward the data output from the first slave directly to the second slave after receiving the signal indicating direct storage after the second step;
    A fourth step of storing forwarding data of the second slave;
    And when the fourth step is completed, the second slave outputs a response signal to the master.
  9. 9. The method of claim 8,
    And outputting the data stored for the read address to the master by the first slave.
  10. 9. The method of claim 8,
    Wherein the signal for direct storage is a Direct-Write After Read (D-WAR) signal.
  11. 9. The method of claim 8,
    In the third step,
    The scheduler controlling a multiplexer to multiplex data from the first slave;
    And controlling the demultiplexer to demultiplex the multiplexed data by another scheduler and forwarding the multiplexed data to the second slave.
KR1020070114070A 2007-11-09 2007-11-09 Apparatus and method for performance mobile platform on-chip bus KR101423675B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030060067A (en) * 2000-06-09 2003-07-12 모토로라 인코포레이티드 Integrated processor platform supporting wireless handheld multi-media devices
JP2005228222A (en) * 2004-02-16 2005-08-25 Ricoh Co Ltd Serial data transfer method and device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030060067A (en) * 2000-06-09 2003-07-12 모토로라 인코포레이티드 Integrated processor platform supporting wireless handheld multi-media devices
JP2005228222A (en) * 2004-02-16 2005-08-25 Ricoh Co Ltd Serial data transfer method and device

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