KR20090043984A - Method for fabricating metal line in semiconductor device - Google Patents

Method for fabricating metal line in semiconductor device Download PDF

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Publication number
KR20090043984A
KR20090043984A KR1020070109824A KR20070109824A KR20090043984A KR 20090043984 A KR20090043984 A KR 20090043984A KR 1020070109824 A KR1020070109824 A KR 1020070109824A KR 20070109824 A KR20070109824 A KR 20070109824A KR 20090043984 A KR20090043984 A KR 20090043984A
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KR
South Korea
Prior art keywords
layer
polymer layer
metal wiring
etching
semiconductor device
Prior art date
Application number
KR1020070109824A
Other languages
Korean (ko)
Inventor
남기원
신수범
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070109824A priority Critical patent/KR20090043984A/en
Publication of KR20090043984A publication Critical patent/KR20090043984A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention is to provide a method for manufacturing a metal wiring of a semiconductor device that can prevent the top attack occurs in the metal wiring due to the lack of margin of the photosensitive film pattern and to prevent the bridge between the metal wiring, the present invention provides a conductive layer Making; Forming a multilayer polymer layer on the conductive layer; Forming an adhesive layer on the multilayer polymer layer; Forming a photoresist pattern on the adhesive layer; Etching the adhesive layer and the multilayer polymer layer using the photoresist pattern; Etching the conductive layer to form metal wiring, and further forming a carbon-based polymer layer, a silicon-based polymer layer, and an adhesive layer on the conductive layer to secure a margin of the photosensitive film pattern, thereby forming a metal wiring top. There is an effect that can prevent the bridge between the attack and the metal wiring.

Metallization, Polymer, Etch Margin

Description

METHOD FOR FABRICATING METAL LINE IN SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a metal wiring manufacturing method of a semiconductor device.

As the semiconductor device becomes more integrated, pattern miniaturization continues, and the thickness of the photoresist film becomes thinner in the mask process. Due to the decrease in the thickness of the photoresist layer, the margin is insufficient during the etching process, and thus, there is a problem in that sufficient overetching is not performed when forming the contact hole.

1A and 1B are cross-sectional views illustrating a method of manufacturing a metal wiring of a semiconductor device according to the prior art.

As shown in FIG. 1A, the conductive layer 12 is formed on the substrate 11, and the photosensitive film pattern 13 is formed on the conductive layer 12. At this time, as the pattern of the photosensitive film pattern 13 becomes smaller, the thickness thereof is formed thinner.

As shown in FIG. 1B, the conductive layer 12 is etched using the photoresist pattern 13 as an etching barrier to form the metal wiring 12A.

As described above, in the prior art, etching is performed by using the photoresist pattern 13 as an etching barrier when the metal wiring 12A is formed.

However, according to the related art, the photoresist pattern 13 is lost before the metal wiring 12A is formed because the margin of the photoresist pattern 13 is insufficient. As a result, a top attack 100 may occur in the metal wiring 12A, or a sufficient over etching may not be performed, thereby causing a bridge 200 between the metal wiring 12A.

2 is a plan view illustrating metal wiring of a semiconductor device according to the related art.

As shown in FIG. 2, it can be seen that the top attack occurred due to the lack of margin of the photoresist pattern when the metal wiring was formed.

3 is a TEM photograph showing a metal wiring of a semiconductor device according to the prior art.

As shown in FIG. 3, when the metal wiring is formed, the margin of the photoresist layer pattern is insufficient, so that sufficient overetching is not performed, and thus the loss of the lower oxide layer is insufficient. That is, in order to prevent the bridges from occurring between the metal wires, overetching of 500 kV or more should be performed on the oxide film. However, since the margin of the photoresist film pattern is insufficient, only 400 kPa or less of the excessive etching is performed on the oxide film (300). As such, when the degree of transient etching is insufficient in the oxide layer, all of the metal wirings are not lost, and some of them remain, resulting in a bridge between the metal wirings.

The present invention has been proposed to solve the above problems of the prior art, and provides a method for manufacturing a metal wiring of a semiconductor device that can prevent the occurrence of a top attack on the metal wiring due to lack of margin of the photosensitive film pattern. have.

In addition, an object of the present invention is to provide a method for manufacturing a metal wiring of a semiconductor device that can prevent the bridge between the metal wiring.

Method of manufacturing a metal wiring contact hole of a semiconductor device of the present invention for achieving the above object comprises the steps of forming a conductive layer; Forming a multilayer polymer layer on the conductive layer; Forming an adhesive layer on the multilayer polymer layer; Forming a photoresist pattern on the adhesive layer; Etching the adhesive layer and the multilayer polymer layer using the photoresist pattern; And etching the conductive layer to form metal wires.

In the method of manufacturing a metal wiring of a semiconductor device according to the present invention, a carbon-based polymer layer, a silicon-based polymer layer, and an adhesive layer are further formed on the conductive layer to secure a margin of the photosensitive film pattern. There is an effect that can prevent the bridge of the liver.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

4A through 4E are cross-sectional views illustrating a method for manufacturing metal wiring of a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 4A, the conductive layer 22 is formed on the substrate 21. The substrate 21 may be a semiconductor substrate in which a DRAM process is performed, and a predetermined process such as a gate pattern, a bit line, and a capacitor may be performed before the conductive layer 22 is formed, and the uppermost layer may be an oxide insulating layer. In addition, the conductive layer 22 may be formed of a metal layer, which may be a titanium film or an aluminum film, and a barrier layer (not shown) on the conductive layer 22 to prevent the conductive layer 22 from being exposed to oxidation in the atmosphere. Can be formed.

Subsequently, the first polymer layer 23, the second polymer layer 24, and the adhesive layer 25 are formed on the conductive layer 22. The first polymer layer 23 is used to etch the conductive layer 22, and may be a carbon rich polymer. The first polymer layer 23 may have a thickness of 1500 to 3000 mm by spin on coating. Can be formed. The second polymer layer 24 is used to etch the first polymer layer 23, and may be a silicon-rich polymer (silicon rich polymer), and may be formed to have a thickness of 250 kPa to 1000 kPa by a spin on coating method. have. The adhesive layer 25 is to improve the degree of adhesion between the second polymer layer 24 and the subsequent photosensitive film pattern, and may be formed to have a thickness of 200 kPa to 700 kPa.

Subsequently, the photosensitive film pattern 26 is formed on the adhesive layer 25. The photoresist pattern 26 may be formed by coating the photoresist on the adhesive layer 25 and patterning the metal wiring region to be defined by exposure and development.

As shown in FIG. 4B, the adhesive layer 25 and the second polymer layer 24 are etched using the photoresist pattern 26 as an etching barrier. The adhesive layer 25 and the second polymer layer 24 may be etched at a pressure of 100 mTorr to 400 mTorr using a mixed gas of CF 4 , CHF 3 and O 2 .

Hereinafter, the etched adhesive layer 25 is referred to as an 'adhesive layer pattern 25A' and the etched second polymer layer 24 is referred to as a 'second polymer pattern 24A'.

As shown in FIG. 4C, the first polymer layer 23 is etched to form the first polymer pattern 23A. The first polymer layer 23 may be etched at a pressure of 5 mTorr to 50 mTorr using a mixed gas of CO, O 2 and Ar. In addition, the mixed gas is CO: O 2 : Ar is mixed in a ratio of 1 to 2: 1: 3 to 5, the total flow rate of the mixed gas may be 200 sccm to 1000 sccm.

When the etching of the first polymer layer 23 is completed, the photoresist pattern 26, the adhesive layer pattern 25A, and the second polymer pattern 24A are all lost or the first polymer pattern 23A is completed. After the removal process can be removed.

Therefore, only the first polymer pattern 23A remains on the conductive layer 22.

As shown in FIG. 4D, the conductive layer 22 is etched using the first polymer pattern 23A as an etching barrier to form the metal wiring 22A. The third polymer layer 27 is generated in the process of etching the metal wiring 22A. The third polymer layer 27 may be a metal polymer by metal etching, and the third polymer layer 27 may be a hard polymer by reacting with the first polymer pattern 23A. As the third polymer layer 27 is deposited on the surface of the first polymer pattern 23A, sufficient etching margin may be secured when the conductive layer 22 is etched.

As described above, the first polymer pattern 23A and the third polymer layer 27 serve as an etching barrier when the conductive layer 22 is etched to secure sufficient etching margins to thereby protect the top attack of the metal wiring 22A. It is possible to prevent and also to prevent excessive bridge etching between the metal wires 22A because a sufficient transient etching is possible so that the conductive layer 22 does not remain between the metal wires 22A.

As shown in FIG. 4E, the third polymer layer 27 and the first polymer pattern 23A are removed.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A and 1B are cross-sectional views illustrating a method of manufacturing a metal wiring of a semiconductor device according to the prior art;

2 is a plan view showing a metal wiring of a semiconductor device according to the prior art;

3 is a TEM photograph showing a metallization of a semiconductor device according to the prior art;

4A to 4E are cross-sectional views illustrating a method of manufacturing metal wirings of a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 substrate 22 conductive layer

23: carbon-based polymer layer 24: silicon-based polymer layer

25: adhesive layer 26: photosensitive film pattern

27: hard polymer layer

Claims (11)

Forming a conductive layer; Forming a multilayer polymer layer on the conductive layer; Forming an adhesive layer on the multilayer polymer layer; Forming a photoresist pattern on the adhesive layer; Etching the adhesive layer and the multilayer polymer layer using the photoresist pattern; And Etching the conductive layer to form metal wiring Metal wire manufacturing method of a semiconductor device comprising a. The method of claim 1, The multilayer polymer layer is a metal layer manufacturing method of a semiconductor device is a polymer layer made of different materials. The method of claim 2, The multilayer polymer layer is a metal wiring manufacturing method of a semiconductor device having a laminated structure of a carbon-based polymer layer and a silicon-based polymer layer. The method of claim 3, Wherein the carbon-based polymer layer is formed to a thickness of 1500 kPa to 3500 kPa, the silicon-based polymer layer is formed to a thickness of 250 kPa to 1000 kPa, and the adhesive layer is formed to be 200 kPa to 700 kPa. The method of claim 3, Etching the adhesive layer and the multilayer polymer layer, A first step of etching the adhesive layer and the silicon-based polymer layer; And The metal wire manufacturing method of the semiconductor device proceeds by dividing into a second step of etching the carbon-based polymer layer. The method of claim 5, The first step, A method for manufacturing a metal wiring of a semiconductor device that proceeds at a pressure of 100 mTorr to 400 mTorr using a mixed gas of CF 4 , CHF 3 and O 2 . The method of claim 5, The second step, A method for manufacturing metal wiring in a semiconductor device that proceeds at a pressure of 5 mTorr to 50 mTorr using a mixture of CO, O 2 and Ar. The method of claim 7, wherein The mixed gas is CO: O 2 : Ar is mixed in a ratio of 1 to 2: 1: 3 to 5, the total flow rate of the mixed gas is 200sccm ~ 1000sccm metal wiring manufacturing method. The method of claim 1, Before etching the conductive layer, And removing the photosensitive film pattern, the adhesive layer, and the silicon-based polymer layer. The method of claim 1, And the photoresist pattern, the adhesive layer, and the silicon-based polymer layer are all lost when the etching of the conductive layer is completed. The method of claim 8, In the etching of the conductive layer, The metal wiring manufacturing method of the semiconductor element in which a metal group polymer layer is formed on the surface of the said carbon-type polymer layer.
KR1020070109824A 2007-10-30 2007-10-30 Method for fabricating metal line in semiconductor device KR20090043984A (en)

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KR1020070109824A KR20090043984A (en) 2007-10-30 2007-10-30 Method for fabricating metal line in semiconductor device

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