KR20090043739A - Cmos image sensor - Google Patents

Abstract

CMOS image sensor according to the present invention by forming a power control unit for controlling the power applied to the light receiving unit CMOS, it is possible to control the output signal of the light receiving unit CMOS, through which it is possible to obtain a result suitable for illuminance, Generation of charges formed by unnecessary photoelectric conversion of the light-receiving part CMOS can be suppressed, and problems such as noise generated due to accumulation of the charges in parasitic capacitance can be prevented.

Image sensor, CMOS, NMOS, PMOS, subject, unit pixel

Description

CMOS image sensor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS image sensor, and more particularly, to a CMOS image sensor that exhibits a constant digital output regardless of the amount of light received, that is, provides a dynamic range from low to high illumination. will be.

An image sensor is a device that captures an image instantaneously by using a property of a semiconductor device that responds to light energy. Light generated from each subject existing in the natural world has a unique value in wavelength and the like. The pixel of the image sensor detects light generated from each subject and converts it into an electric value.

That is, the pixel of the image sensor generates an electrical value corresponding to the wavelength of light in response to the magnitude of light energy generated in the subject.

Among these, a charge coupled device (CCD) is a device in which charge carriers are stored and transported in a capacitor while individual MOS capacitors are located in close proximity to each other. A sensor is a device that employs a switching method of forming a pixel array using a CMOS integrated circuit manufacturing technology and sequentially detecting the output. The CMOS image sensor has the great advantage of low power consumption, making it very useful for personal portable systems such as mobile phones.

FIG. 1A is a diagram illustrating a conventional three-transistor CMOS active pixel, a cross-sectional view of a photo-diode including a circuit of peripheral components, and FIG. 1B is a conventional three-transistor seed of FIG. 1A. It is an equivalent circuit diagram of MOS active pixel.

1A and 1B, in a conventional three-transistor CMOS active pixel, an N + type impurity layer 11 and an N + type floating diffusion layer 13 constituting one junction of a photodiode are in contact with each other. Therefore, the capacitance component of the photodiode is substantially the sum of the capacitor components produced by the N + type impurity layer 11 and the N + type floating diffusion layer 13.

Accordingly, an image sensor employing a conventional three-transistor CMOS active pixel has a disadvantage of low sensitivity. The four-transistor CMOS active pixel is to compensate for the disadvantage of the three-transistor CMOS active pixel.

FIG. 2A is a diagram illustrating a conventional 4-transistor CMOS active pixel, showing a cross section of a photodiode including a circuit of peripheral components, and FIG. 2B is an equivalent of the conventional 4-transistor CMOS active pixel of FIG. 2A. It is a circuit diagram.

2A and 2B, the conventional 4-transistor CMOS active pixel includes a transfer transistor 25 controlled by a transmission control signal Tx to remove noise generated in the 3-transistor CMOS active pixel. Used. The N + type impurity layer 21 and the N + type floating diffusion layer 23 constituting one junction of the photodiode are separated from each other.

Therefore, in the conventional 4-transistor CMOS active pixel, the sensitivity of the image sensor may be increased and the image quality may be improved. However, the four-transistor CMOS active pixel has a disadvantage in that the light receiving area is reduced due to the addition of the transfer transistor.

FIG. 3A is a circuit diagram connected to a pixel portion formed of a combination of unit pixels shown in FIGS. 1A and 2A. The pixel unit 30 refers to one column of unit pixels. The pixel portion 30 is provided by the number of columns, and the number of unit pixels included in each pixel portion 30 is provided by the number of rows.

Generally, '640 × 480 VGA', '1024 × 768 XGA, 1280 × 1024 SXGA' means '640 columns × 480 rows', '1024 columns × 768 rows', '1280 columns × 1024', respectively. This means that the image resolution consists of 'rows'. In practice, the number of columns and rows is somewhat higher. 3B illustrates a signal applied to the unit pixel illustrated in FIGS. 1A and 2A.

The processing on the circuit and signal shown in FIGS. 3A and 3B is as follows. When a select signal is applied to a row including a plurality of unit pixels, an image data signal captured during a row enable period (R_en, row enable) in the plurality of unit pixels is captured from the common contact 31 of the column by CDS (Correlated). Double Sampling) 36 is applied. The image data signal includes data signals corresponding to various levels of illuminance according to the surrounding environment, from a high illuminance signal that is a bright light data signal to a low illuminance signal that is a dark light data signal.

The data signal according to the various levels of illumination lowers the reference voltage applied to the circuit including the CDS 36 at each level. That is, the low light data signal lowers the reference voltage relatively less, while the high light data signal drops the reference voltage relatively much.

3C illustrates a voltage drop phenomenon of the data signal according to each illuminance level. Although three levels are illustrated in FIG. 3C for convenience of description, various levels of data signals may exist.

In the 'A' section and the 'C' section of FIG. 3C, a stable section without fluctuation of the signal voltage and a 'B' section are sections in which the drop of the signal voltage occurs. First, while the low enable signal R_en is disabled, the reset sampling drive signal SR is applied to the switch b 32b of the CDS 36 during the reset sampling period A to apply the reset voltage to the capacitor b 33b. Save it.

Thereafter, when the row enable signal R_en of the signal of FIG. 3B is applied to each unit pixel of the row, and the image data signal is applied to the common contact 31 of the column, the switch a 32a of the CDS 36 is external. Data sampling (SD, data sampling) is performed during the 'C' period by the data sampling driving signal applied from the multiplier 35 to store the value in the capacitor a 33a and through the buffer a 34a. Apply a data signal voltage.

After completion of the data sampling (SD), a reset (RST) signal is applied, and when low enable is completed, a reset is applied externally by a switch b32b of the CDS 36 for processing the next image processing data. Reset sampling (SR) is performed during the 'A' period by the sampling driving signal to store the reset voltage in the capacitor b 33b, and apply a signal to the MUX 35 via the buffer b 34b.

When such a series of signals (R_en, SD, RST, SR) proceed for one period, image data stored in the unit pixel is acquired, and a differential amplifier (SHA, Sample and Hold Amplifier) 37, a programmable gain amplifier (PGA) (38) and the analog-digital converter (ADC) 39 output image data.

As a result, the conventional three-transistor CMOS active pixel has a disadvantage of low sensitivity, and the conventional four-transistor CMOS active pixel has a problem in that a light receiving area is small.

The solution to solve this problem will be described below, and the solution to the saturation problem due to high sensitivity at high illumination in the solution solution will be described.

The present invention has been made to solve the above problems, and aims to reduce the size of the image sensor by reducing the pitch size.

In addition, to improve the yield in the process and to reduce the production cost to propose a method to prevent the saturation of the shape at high illumination.

In order to achieve the above object, the present invention provides a power control unit for controlling a power supply, a light receiving unit CMOS that receives the power supplied by the power control unit and receives the light to generate an electrical signal and outputs the signal received from the light receiving unit CMOS Including a secondary CMOS, wherein the power control unit presents a CMOS image sensor for controlling the power applied to the light receiving unit CMOS.

Here, the light receiving unit CMOS, the output unit CMOS and the power control unit are preferably disposed in a unit pixel, and for this purpose, the power control unit preferably has a MOS structure.

The power control unit receives a power control signal from the outside to control the power applied to the light receiving unit CMOS.

The light receiving unit CMOS and the power supply control unit are each one PMOS, and the output unit CMOS is preferably composed of one NMOS, wherein the light receiving unit CMOS includes an N-type doped well on a P-type semiconductor substrate. And a light receiving part to a region of a gate and an N-well, wherein the power control part is a structure that controls the power applied to the light receiving part CMOS while sharing the well on the P-type semiconductor substrate. The P-type semiconductor substrate preferably has a structure for outputting a signal received from the light receiving unit CMOS, and the light receiving unit CMOS and the power supply control unit preferably have a source and a drain formed in the well.

In addition, the gate of the light receiving unit CMOS is preferably floated, it is preferable that the gate of the output CMOS receives a selection signal from the outside.

The connection part may further include a connection part formed in a part of the well to connect the gate of the light receiving part CMOS with the well, and the connection part is preferably formed by doping with the same impurity type as the well. The doping concentration is preferably higher than the doping concentration of the well.

In addition, a metal contact may be formed on the connection part to connect the gate of the connection part and the light receiving part CMOS.

As described above, the CMOS image sensor according to the present invention forms a power control unit for controlling the power applied to the light receiving unit CMOS, thereby controlling the output signal of the light receiving unit CMOS, thereby obtaining a result suitable for illuminance. It is possible to suppress generation of electric charges formed by unnecessary photoelectric conversion of the light-receiving part CMOS, and it is possible to prevent problems such as noise generated due to accumulation of the electric charges in parasitic capacitance.

In addition, by forming the sensor unit with a small number of NMOS and PMOS, the area of the CMOS image sensor can be reduced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is an equivalent circuit diagram conceptually showing the structure of the CMOS image sensor of the present invention. In an active pixel structure of a conventional photodiode type, a light receiving area of a photodiode as a light receiving unit is reduced due to CMOS such as Rx, Sx, and Tx. It is a circuit diagram proposed to solve the low sensitivity characteristic. Referring to FIG. 4, in the CMOS unknown sensor of the present invention, the unit pixel including the light receiving unit 40 and the selection MOS 41 has a passive pixel structure, so that the size of the unit pixel can be relatively reduced compared to the prior art. In addition, since the signal is output as a voltage through the current-voltage converter 42, there is an advantage that the signal processing method from the analog circuit (CDS 43) of the conventional CMOS image sensor to the ADC 47 can be utilized as it is. .

The CMOS pixel array captures an external subject image and divides the image of the subject in individual unit pixels evenly by the number of unit pixels to generate electrical signals corresponding to different brightnesses. In each unit pixel, the charge corresponding to the amount of light absorbed is present in the P-N heterojunction that joins the N-well of the PMOS and the P-type corresponding to the source and drain of the PMOS 40 and the N-type of the N-well, respectively. Electron hole pairs (EHPs) of the depletion layer are separated according to the amount of light and are generated as charge carriers to generate electrical current, and selectively move through the NMOS 41 connected to the PMOS to serve as a switch. .

Therefore, the large photocurrent generated from the PMOS used as the light receiving element is transferred to the current mirror without charge accumulation. In the current mirror 42, the current is amplified, the amplified current is algebraically converted, and the converted voltage is read using a circuit implemented by the CDS 43, the MUX 44, and the SHA 45. The image data is output through the PGA 46 and the ADC 47. Applying this to the pixels of the image sensor can significantly reduce the charge accumulation time.

FIG. 5 is a configuration diagram of the CMOS image sensor of FIG. 4, wherein the unit pixel is formed only by a MOS process of a general semiconductor in fabricating a unit pixel of the CMOS image sensor. The light receiving portion of the unit pixel structure is composed of a PMOS using a photoelectric conversion method by light incidence, and a unit pixel having a 2-transistor structure of 1PMOS and 1NMOS including an NMOS connected to the PMOS and serving as a switch. To form a structure.

That is, by implementing one conventional photodiode and a three-transistor or one photodiode and a four-transistor unit pixel in a two-transistor structure, the pitch size of the unit pixel is reduced, and the control such as the conventional reset ( Since there is no control signal, metal lines are reduced in the layout of the pixel, thereby simplifying the structure of the unit pixel.

The unit pixel forming method is as follows.

In order to implement PMOS and NMOS on the P-type semiconductor substrate 200, an N-well (well) 220 is formed in the PMOS region. In the process of forming the Nwell 220, an ion implantation process is performed on N-type impurities in a state in which a pattern is formed on the P-type semiconductor substrate 200 and only the region where the N-well 220 is to be opened is opened. Then, heat treatment to form the N-well 220. A gate oxide layer 260 and polysilicon are sequentially deposited on the entire surface of the substrate on which the N-well 220 is formed, patterned, and then etched to form a floating gate 240 in the PMOS and a select gate 250 in the NMOS. .

Subsequently, a mask in which only the source / drain formation region of the PMOS region is opened is formed, a high concentration P-type implantation process is performed to form the source / drain 230 in the PMOS region, and the source / drain of the NMOS region is sequentially A mask in which only the formation region is opened is formed, and a source / drain 270 is formed in the NMOS region by performing a high concentration N-type ion implantation process. In addition, a salicide process may be additionally performed to reduce the resistance in regions where the source / drain of PMOS and NMOS is formed. However, since the PMOS is an optical device that receives light, light must pass through the floating gate formed on the upper side of the PMOS. Therefore, it is essential not to perform the salicide process on the floating gate.

Referring to the driving principle of the CMOS image sensor of FIG.

When a voltage is applied to the source of the PMOS formed on the same substrate as the NMOS, the N-well of the PMOS forms a depletion region in an electrically neutral state. Subsequently, when a photon is incident on an N-well, which is a depletion region, by receiving light through a PMOS, which is a light receiving unit, an electron hole pair (EHP) is separated, thereby forming a P channel on a gate bottom of the PMOS device. A voltage is applied to the select gate formed in the NMOS connected to the PMOS, and an N channel is formed between the source and the drain formed in the NMOS to receive the signal charge formed in the PMOS and emit an output signal.

Referring to the graph of FIG. 6, in the conventional photodiode, the current flows when the light intensity is greater than or equal to a critical point, and the current tends to increase as the light intensity increases linearly. As the sensor pixel has a structure in which current flows immediately upon receiving light, there is no dark current, and as shown in area A of FIG. 6, the slope of the current change with respect to a small amount of light is very sharp. The slope of the current change with respect to the light change is relatively gentle.

Therefore, since there is no control signal as in the conventional reset, since the metal line is reduced in the layout of the pixel, the pitch size may be reduced compared to the conventional unit pixel, and in the case of the conventional CMOS image sensor, one photon While generating one electron-hole pair, the PMOS light-receiving device generates a photo current in which one photon is amplified, so that the current gain of the photocurrent reaches 100 to 1000, thereby realizing an image even in low light with a small amount of light incident. Since the charge accumulation time can be reduced by 100 ~ 1000 times compared with the conventional sensor, the charge accumulation time is enough for tens of clock delays instead of one frame or one line, so that integration time is unnecessary and high speed video is realized. To make it possible.

In addition, since the CMOS image sensor described above implements unit pixels in a general MOS process, a dedicated process of the existing CMOS image sensor is unnecessary. Since the present invention receives light from the PMOS without integration time and outputs it through the NMOS, it is possible to minimize the dark current of the sensor due to the long integration except the dark current caused by the leakage current of the switching NMOS.

Therefore, in the conventional CMOS image sensor forming process, an epitaxial layer is formed on the surface of the light receiving unit in order to prevent dark current, and the PMOS light receiving device of the present invention generates light by amplifying one photon. In order to collect the light receiving portion of the unit pixel, a microlens forming process is not required on the unit pixel. All of these processes can be omitted, thus reducing production costs.

FIG. 7 is a configuration diagram of a CMOS image sensor in which a gate of a PMOS is connected to an N-well of a PMOS. In manufacturing a unit pixel, a unit pixel is formed only by a MOS process of a general semiconductor. In the structure of the unit pixel, the light receiving portion is a two-transistor structure of 1 PMOS and 1 NMOS including a PMOS using a photoelectric conversion method by light incident and an NMOS connected to the PMOS and serving as a switch. A unit pixel having a gate connected to an N-well is formed.

Therefore, the CMOS image sensor has a conventional unit pixel having one photodiode and three-transistor or one photodiode and four-transistor structure in a two-transistor structure, thereby reducing the pitch size of the unit pixel. Since there is no control signal such as a reset of, the structure of the unit pixel can be simplified because the metal line is reduced in the layout of the pixel.

The unit pixel forming method of the CMOS image sensor of FIG. 7 is as follows.

In order to implement PMOS and NMOS on the P-type semiconductor substrate 200, an N-well 220 is formed in the PMOS region. In the formation process of the N-well, an ion implantation process is performed on an N-type impurity in a state in which a pattern is formed on a P-type semiconductor substrate and only the region where the N-well is to be formed is opened. Form. The gate oxide layer 260 and the polysilicon are sequentially deposited on the entire surface of the N-well, and are patterned and then etched to form a floating gate 240 in the PMOS and a select gate 250 in the NMOS.

Subsequently, a mask in which only the source / drain formation region of the PMOS region is opened is formed, a high concentration P-type implantation process is performed to form the source / drain 230 in the PMOS region, and the source / drain of the NMOS region is sequentially A mask in which only the formation region is opened is formed, and a source / drain 270 is formed in the NMOS region by performing a high concentration N-type ion implantation process.

In order to connect the gate 240 formed in the PMOS and the N-well 220, a connection portion 210 is formed on the surface of the N-well. The connection portion 210 of the Nwell injects N-type ions to a concentration higher than the formation concentration of the N-well, and forms a metal contact 280 in a region where the high concentration of N-type ions are implanted to electrically connect the PMOS and the N-well. Connect.

At this time, the CMOS image sensor of FIG. 7 is also an optical device that receives light, and since light passes through a gate formed on the PMOS, the gate of the PMOS does not perform a salicide process.

Referring to the driving principle according to the unit pixel of the CMOS image sensor of FIG.

In the independent N-well formed on the same substrate as the NMOS, a depletion region electrically neutral at the interface with the P-type substrate is formed. At this time, a voltage is applied to the source of the PMOS, and the light is received by the light-receiving portion of the PMOS, which causes photons to enter the N-well, which is a depletion region, thereby separating the electron hole pair (EHP). When voltage is applied, electrons remaining in the N-well connected to the PMOS gate act as a bias to the N-type well substrate and the PMOS gate, thereby lowering Vth (the minimum voltage required to form a channel). As it plays a role, the current has the characteristics as shown in the graph of FIG. 6 according to the light intensity. Accordingly, when a turn on voltage is applied to the select gate 250 formed in the NMOS connected to the PMOS, an N channel is formed between the source and the drain formed in the NMOS to receive the signal charge formed in the PMOS and emit an output signal.

Referring to the graph of FIG. 6, in the conventional photodiode, the current flows when the light intensity is greater than or equal to a critical point, and the current tends to increase as the light intensity increases linearly. Due to the separation of EHP due to light incidence, the same number of electrons left in the N-well remain in the N-well and the bias of the N-well changes, and this bias is electrically connected to the PMOS gate and the N-type well. ) It acts as a substrate bias and lowers Vth (the minimum voltage required to form a channel), while the slope of the current change with respect to the small amount of light changes as shown in area A of FIG. It can be seen that the change is more rapid than the change shown in the unit pixel of 5, and in the region B, the slope of the current change with respect to the light change is the unit pixel of FIG. It represents a gentle change patterns than shown.

Therefore, since the CMOS image sensor of FIG. 7 also has no control signal as in the conventional reset, since the metal lines are reduced in the layout of the pixels, the pitch size may be reduced compared to the existing unit pixels, and a small amount of light may be applied to the PMOS. Even when this incident, a large amount of current can flow, so that a clear phase can be realized at low light, and integration time is unnecessary, thereby enabling high speed video.

In addition, since the CMOS image sensor of FIG. 7 implements a unit pixel in a general MOS process, a dedicated process of the existing CMOS image sensor is not necessary, and thus, an effect of increasing process yield and reducing process cost may be induced in the future. Can be.

In the above, the CMOS image sensor, which has a high sensitivity and high-speed processing even at low light by configuring the unit pixel structure of the light receiving unit PMOS and the output NMOS, has been described. A light receiving unit CMOS for generating a typical signal is formed, and an output unit CMOS for outputting a signal received from the PMOS is formed using one NMOS.

However, the CMOS image sensor having such a structure may be problematic in that it is excellent in sensitivity to light. That is, there is no problem due to the high sensitivity at low illuminance, but saturation may occur at high illuminance. In particular, this phenomenon is expected at 1000 lux or more, and in order to solve this problem, the aperture of the imager equipped with the CMOS image sensor should be adjusted, which may cause inconvenience to the user. Let's look at it.

8 is a block diagram illustrating a CMOS image sensor according to an exemplary embodiment of the present invention.

Referring to FIG. 8, the CMOS image sensor according to the present embodiment includes a power control unit 130 for controlling power; A light receiving unit CMOS 110 that receives power from the power control unit 130 and receives light to generate an electrical signal; An output unit CMOS 120 for outputting a signal received from the light receiving unit CMOS (110), the power control unit 130 controls the power applied to the light receiving unit CMOS (110).

As described above, the light receiving unit CMOS 110 is a light receiving device and receives an external light to generate an electrical signal corresponding to the brightness of the received light (photoelectric conversion). This means imaging of an external subject image.

As described above, the output unit CMOS 120 is a kind of switch element, and serves as a switch for an electrical signal, more specifically, an electrical current output from the light receiver CMOS 110.

The power control unit 130 controls the power applied to the light receiving unit CMOS 110, and is disposed in front of the light receiving unit CMOS 110.

The light receiving unit CMOS 110, the output unit CMOS 120, and the power supply control unit 130 are preferably disposed in the unit pixel 100 as shown in FIG. 9. The light receiving unit CMOS 110 and the output unit are formed as an aggregate of MOSs. As with the CMOS 120, forming in a MOS structure is advantageous for placement in unit pixels.

In addition, the power control unit 130 receives a power control signal from the outside and operates according to the power control signal, so that the light receiving unit CMOS 110 receives power by external control.

Since the power control signal is preferably formed as a timing signal for applying power at an ON point of the output unit CMOS 120, the select signal (selection signal) of the output unit CMOS 120 is considered. Should be formed.

Through such a configuration, power may be applied to increase the output of the light receiving unit CMOS 110 in dark illumination, and power may be applied to reduce the output of the light receiving unit CMOS 110 in bright illumination. Corresponding suitable image results can be obtained.

Such processing is performed through the power control unit 130, and in order to automatically process without user intervention, a light source measuring unit measuring external illuminance to an element to which a power control signal of the power control unit 130 is applied; Preferably, a power control signal generator for generating the power control signal is further formed according to the illuminance measured by the light source measuring unit.

In addition, according to the configuration of FIG. 8, it is possible to prevent charges generated by the light receiving unit CMOS 110 continuously receiving and photoelectrically converting during the frame adjustment period, that is, the period in which the select signal is not applied. This is possible by using the power control unit 130 to prevent power from being applied to the light receiving unit CMOS 110 during the frame adjustment period.

Since VDD is continuously applied to the input terminal of the power control unit 130, even if charge accumulates in the parasitic capacitance due to the VDD, the charge generated by the photoelectric conversion of the light receiving unit CMOS 110 is parasitic capacitance. Due to the accumulation of noise, the expected noise does not occur.

The amount of charge generated by photoelectric conversion in the light receiving unit CMOS 110 is different for each pixel according to a subject, and the amount of charge showing the difference is accumulated in parasitic capacitance and the output unit CMOS 120 is turned on. In this case, it is added to the normal output signal of the light receiver CMOS 110. That is, a non-uniform value (charge amount showing a difference) is added to the normal output of the light receiver CMOS 110 to generate a final output, and noise is generated due to the non-uniform value.

Therefore, even if the amount of charge is accumulated in the parasitic capacitance due to the power control unit 130, the amount of charge is due to VDD and thus the same amount of charge will be accumulated in the parasitic capacitance for all unit pixels. This means that each unit pixel has the same initial state, and thus problems such as noise, which are expected due to accumulation of charge generated in the light receiving unit CMOS 110, do not occur.

FIG. 10 is a circuit diagram illustrating a specific example of FIG. 8. Referring to FIG. 10, the light receiver CMOS 110 and the power controller 130 are each formed as one PMOS, and the output CMOS 120 is configured as one NMOS. have.

Except for the power control unit 130, the unit pixel structure of the image sensor described in FIGS. 4 to 7 is the same.

By forming the power control unit 130 as a PMOS, the power control unit 130 is preferably arranged together with the light receiving unit CMOS 110, which is shown in detail in FIG. 11 showing the equivalent MOS structure of FIG. .

Referring to FIG. 11, the light receiving unit CMOS 110 is a central PMOS structure including an N-type doped well on a P-type semiconductor substrate and receiving light into a partial region of a gate and an N-well. 130 is a PMOS structure on the left side that shares the well and controls the power applied to the light receiving unit CMOS 110 on the P-type semiconductor substrate, and the output CMOS 120 is formed on the P-type semiconductor substrate. The NMOS structure on the right side outputs the signal received from the light receiver CMOS 110.

The light receiving unit CMOS 110 and the power control unit 130 have a source and a drain formed in the well, and the source of the light receiving unit CMOS 110 and the drain of the power control unit 130 have a shared P. It is formed by a channel.

Other configurations are the same as the structures described with reference to FIGS. 4 to 7, and thus, a detailed description thereof is omitted, and the gate of the light receiver CMOS 110 is preferably floated, and the gate of the output CMOS 120 is external. Has a structure in which a selection signal (select signal) is applied.

The connection part may further include a connection part formed in a part of the well to connect the gate of the light receiving part CMOS 110 to the well, and the connection part may be formed by doping with the same impurity type as the well. The doping concentration of is preferably higher than the doping concentration of the well.

In addition, a metal contact may be formed on the connection part to connect the gate of the connection part and the light receiving part CMOS.

In such a MOS structure, the light receiving unit CMOS 110, the output unit CMOS 120, and the power supply control unit 130 are preferably formed on a unit pixel. The panel of the finished CMOS image sensor is formed.

FIG. 13 illustrates a circuit to which the configuration of FIG. 10 is applied, and a current mirror unit 150 for stable output is disposed at a rear end of the output unit CMOS 120, and the current mirror unit 150 is provided. In the other end that is not connected to the output CMOS (120) is formed a MOS diode 170 for current-voltage conversion. As a result, the voltage signal is output to the output signal through a separate amplifier and an analog-to-digital converter to appear as the resulting digital information.

In FIG. 13, the gates of the light receiving unit CMOS 110 and the power control unit 130 are electrically connected using the connection line 140, which causes the power control unit 130 to also perform some photoelectric conversion. This is to improve (reactivity). Of course, the power control unit 130 is advantageous to improve the reliability to form a structure that blocks light reception, even if the structure does not block light reception shows that there is no problem.

It can be applied to image sensor using CMOS.

1A is a schematic diagram illustrating CMOS active pixels of a conventional three-transistor image sensor.

1B is a circuit diagram illustrating an equivalent circuit of FIG. 1A.

2A is a schematic diagram showing CMOS active pixels of a conventional four-transistor CMOS image sensor.

FIG. 2B is a circuit diagram showing an equivalent circuit of FIG. 2A. FIG.

FIG. 3A is a circuit diagram connected with a pixel portion consisting of a combination of pixels shown in FIGS. 1A and 2A.

3B is a graph showing a signal applied to the pixels shown in FIGS. 1A and 2A.

3C is a graph illustrating voltage drop phenomenon of data signals according to conventional illumination levels.

4 is a schematic circuit diagram illustrating a process of transferring signal charge in a unit pixel of a CMOS image sensor to solve the problems of FIGS. 1 and 2.

5 is a cross-sectional view of a unit pixel of the CMOS image sensor of FIG. 4.

FIG. 6 is a graph illustrating a PMOS current change according to light intensity change in a unit pixel of FIG. 4. FIG.

7 is a cross-sectional view of another unit pixel of a CMOS image sensor according to another example of FIG. 4.

8 is a schematic view showing a CMOS image sensor according to an embodiment of the present invention.

9 is a schematic diagram illustrating another example of FIG. 8.

10 is a circuit diagram illustrating a specific example of FIG. 8.

FIG. 11 is a cross-sectional view illustrating the equivalent MOS structure of FIG. 10. FIG.

12 is a schematic view showing the plane in which FIG. 11 is disposed;

FIG. 13 is a circuit diagram to which the configuration of FIG. 10 is applied. FIG.

* Description of the symbols for the main parts of the drawings *

110 Receiver CMOS 120 Output CMOS

130 ... Power Control

Claims (13)

A power control unit controlling power; A light receiving unit CMOS that receives power from the power control unit and receives light to generate an electrical signal; An output unit CMOS for outputting a signal received from the light receiving unit CMOS; Including; And the power controller controls the power applied to the light receiver CMOS. The method of claim 1, And the light receiver CMOS, the output CMOS and the power controller are arranged in a unit pixel. The method of claim 2, The power control unit CMOS image sensor, characterized in that the MOS structure. The method of claim 1, The power control unit CMOS image sensor, characterized in that receiving a power control signal from the outside. The method of claim 1, And each of the light receiver CMOS and the power controller is one PMOS, and the output CMOS is one NMOS. The method of claim 5, wherein The light-receiving unit CMOS includes a well doped with an N-type on a P-type semiconductor substrate and receives light into a portion of a gate and an N-well, The power control unit is configured to control the power applied to the light-receiving unit CMOS while sharing the well on the P-type semiconductor substrate. And the output unit CMOS has a structure for outputting a signal received from the light receiving unit CMOS on the P-type semiconductor substrate. The method of claim 6, The CMOS image sensor of claim 1, wherein the light source CMOS and the power controller are formed with a source and a drain in the well. The method of claim 6, And the gate of the light-receiving part CMOS is floated. The method of claim 6, The CMOS image sensor, characterized in that the gate of the output CMOS receives a selection signal from the outside. The method of claim 6, And a connection part formed in a part of the well to connect the gate of the light receiving part CMOS and the well. The method of claim 10, And the connection part is formed by doping with the same impurity type as the well. The method of claim 10, And the doping concentration of the connection portion is higher than the doping concentration of the well. The method of claim 10, And a metal contact is formed on the connection part to connect the connection part and the gate of the light receiving part CMOS.

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