KR20090041007A - Stacked semiconductor package - Google Patents

Abstract

A stacked semiconductor package is provided to prevent the reduction of the data storage capacity of each semiconductor chip by arranging a conductive connection member exposed from the side of each semiconductor chip for connecting the chips electrically. A stacked semiconductor package includes a semiconductor chip module(100) and a receiving substrate(250). The semiconductor chip module includes at least two stacked semiconductor chips(90). A pad(20) is arranged in the upper side of the semiconductor chip body. A recess part is arranged in the side of the semiconductor chip body. A conductive connection pattern(40) covers the groove formed in the side of the semiconductor chip body by the recess part. A receiving substrate includes a receiving unit and a connecting pattern. The receiving unit is the recess formed from the upper part of the receiving substrate with a predetermined depth. The semiconductor chip module is received in the receiving unit. The connecting pattern(260) is formed on the inner side of the receiving substrate formed by the receiving unit.

Description

Multilayer Semiconductor Packages {STACKED SEMICONDUCTOR PACKAGE}

The present invention relates to a laminated semiconductor package.

In recent years, with the development of semiconductor manufacturing technology, various kinds of semiconductor packages having semiconductor devices suitable for processing more data in a short time have been developed.

The semiconductor package is manufactured through a semiconductor chip manufacturing process for manufacturing a semiconductor chip including a semiconductor element on a wafer made of high purity silicon, a die sorting process for electrically inspecting the semiconductor chip, and a packaging process for packaging a good semiconductor chip. .

Recently, a chip scale package in which the size of a semiconductor package is only about 100% to 105% of the size of a semiconductor chip, and a stacked semiconductor in which a plurality of semiconductor chips are stacked on each other to improve data capacity and processing speed of a semiconductor device. Packaged semiconductor packages and the like are being developed.

In the stacked semiconductor package in which a plurality of semiconductor chips are stacked, a through hole is formed in the semiconductor chip to electrically connect the stacked semiconductor chips, and a through electrode is disposed in the through hole.

When the through electrodes penetrating the semiconductor chips are formed to manufacture the stacked semiconductor package, the data capacity of each semiconductor chip is reduced by the area occupied by the through electrodes.

In addition, when the through electrode is formed on the semiconductor chip, breakage of the semiconductor chip may occur, and a semiconductor chip applied only to the laminated semiconductor package is required by the through electrode.

One object of the present invention is to provide a stacked semiconductor package in which a plurality of semiconductor chips are stacked and reduced in volume without improving data storage capacity by improving the structure of the through electrode.

The stacked semiconductor package according to the present invention includes a semiconductor chip body having an upper surface, a lower surface, side surfaces connecting the upper surface and the lower surface, and a circuit portion, pads connected to the circuit portion and disposed at edges of the upper surface, and corresponding to each pad. A semiconductor chip module formed concave in the side surface and including at least two semiconductor chips disposed on a surface of the recess portion connecting the upper surface and the lower surface and a conductive connection pattern connected to the pad; And an accommodating substrate having an accommodating part for accommodating the semiconductor chip module, the accommodating substrate having a connection pattern disposed on an inner side facing the semiconductor chip module among the inner surfaces formed by the accommodating part and connected to the conductive connection patterns. do.

The accommodating portion of the accommodating substrate of the multilayer semiconductor package is a through hole penetrating through an upper surface of the accommodating substrate and a lower surface opposing the upper surface.

The accommodating substrate of the multilayer semiconductor package may include a cover disposed on the upper surface to cover one side of the accommodating part and a molding member covering the other side of the accommodating substrate.

The connection pattern of the multilayer semiconductor package includes a plating pattern disposed on the inner side surface and a solder pattern formed on the plating pattern and electrically connected to the conductive connection member.

A ball land pattern electrically connected to the connection pattern is formed on at least one of an upper surface of the accommodating substrate and a lower surface of the multilayer semiconductor package facing the upper surface.

At least two accommodating substrates in which the semiconductor chip modules of the multilayer semiconductor package are accommodated are stacked, and ball land patterns facing each other among the stacked accommodating substrates are electrically connected by solder balls.

The accommodating substrate of the multilayer semiconductor package includes at least two accommodating portions.

According to the present invention, in order to electrically connect the semiconductor chips constituting the laminated semiconductor package with each other, the conductive connection members exposed from the sides of the semiconductor chips are disposed to prevent the data storage capacity of each semiconductor chip from being reduced, as well as the stacked semiconductors. The package may be mounted in an accommodating substrate having a recess to significantly reduce the thickness of the laminated semiconductor package.

Hereinafter, the multilayer semiconductor package according to the embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and those skilled in the art will appreciate The present invention may be embodied in various other forms without departing from the spirit of the invention.

1 is an exploded perspective view illustrating a laminated semiconductor package according to an embodiment of the present invention.

Referring to FIG. 1, the stacked semiconductor package 400 includes a semiconductor chip module 100 and an accommodation substrate 250.

The semiconductor chip module 100 includes at least two semiconductor chips 90 stacked on the semiconductor chip module 100. In this embodiment, the semiconductor chip module 100 includes, for example, four semiconductor chips 90.

FIG. 2 is a partially cutaway perspective view illustrating a semiconductor chip of any one of the semiconductor chip modules illustrated in FIG. 1. 3 is a cross-sectional view taken along the line II ′ of FIG. 2. 4 is an enlarged view of a portion 'A' of FIG. 3.

2 and 3, each semiconductor chip 90 of the semiconductor chip module 100 may include a semiconductor chip body 10, pads 20, a recessed portion 30, and a conductive connection pattern 40. Include.

The semiconductor chip body 10 has a rectangular parallelepiped shape, for example. The semiconductor chip body 10 having a rectangular parallelepiped shape includes an upper surface 1, a lower surface 3 facing the upper surface 1, side surfaces 5 connecting the upper surface 1 and the lower surface 3, and a circuit portion 8. ). The semiconductor chip body 10 having a cuboid shape includes four side surfaces 5. The circuit sections 8 comprise elements such as transistors, capacitors, resistors and the like, for example, for storing and processing data.

The pads 20 are disposed on the top surface 1 of the semiconductor chip body 10. The pads 20 are electrically connected to the circuit section 8. The pads 20 electrically connected to the circuit part 8 are arranged, for example, at the edge portion of the upper surface 1.

The recess 30 is disposed on the side surfaces 5 of the semiconductor chip body 10. For example, the recesses 30 are each disposed on a pair of opposing side surfaces 5, and the recesses 30 have a recess shape formed concave from the side surfaces 5. In the present embodiment, the recess 30 is disposed at a position corresponding to each pad 20.

In this embodiment, for example, a semicircular groove is formed in the side surface 5 of the semiconductor chip body 10 by the recess portion 30. The recess 30 connects the upper surface 1 and the lower surface 3 of the semiconductor chip body 10.

In the present embodiment, when the semicircular groove is formed in the side surface 5 of the semiconductor chip body 10 by the recess portion 30, the area of the circuit portion 8 is increased to store the data of the circuit portion 8. The capacity can be greatly improved.

The pad 20 and the recess 30 corresponding to each pad 20 may be disposed adjacent to each other. Alternatively, the pads 20 and the recesses 30 corresponding to the pads 20 may be spaced apart from each other by a predetermined interval. In the present embodiment, the pads 20 and the recesses 30 corresponding to the respective pads 20 are disposed adjacent to each other.

The conductive connection pattern 40 covers the groove formed in the side surface 5 of the semiconductor chip body 10 by the recess portion 30, and a part of the conductive connection pattern 40 is formed on the top surface of the semiconductor chip body 10. Cover the pad 20 disposed in 1). The conductive connection pattern 40 has a semi-cylindrical shape, for example.

Referring to FIG. 4, the conductive connection pattern 40 may include a metal seed pattern 42. The metal seed pattern 42 covers the grooves and the pads 20 formed in the side surface 5 of the semiconductor chip body 10 by the recesses 30. In this embodiment, examples of materials that can be used as the metal seed pattern 42 include titanium, nickel, vanadium, and the like.

The conductive connection pattern 40 may be, for example, a low melting point metal having a melting point similar to lead. In the present embodiment, the conductive connection pattern 40 disposed on the metal seed pattern 42 may include solder. In the present embodiment, the metal seed pattern 42 and the conductive connection pattern 40 have substantially the same shape and size.

As shown in FIG. 1, a plurality of semiconductor chips 90 illustrated in FIG. 2 are stacked. For example, four semiconductor chips 90 are stacked.

An insulating adhesive member 70 is disposed on the upper surface 1 and the lower surface 3 of the stacked semiconductor chip 90 to stack the plurality of semiconductor chips 90. The stacked semiconductor chips 90 are attached to each other by the insulating adhesive member 70, and a pair of adjacent semiconductor chips 90 are spaced apart from each other by the thickness of the insulating adhesive member 70.

Meanwhile, the insulating adhesive member 70 not only attaches the stacked semiconductor chips 90 to each other, but also prevents the pad 40 of the lower semiconductor chip and the upper semiconductor chip disposed on the lower semiconductor chip from being electrically shorted.

Each conductive connection pattern 40 of the stacked semiconductor chips 90 is aligned at the same position so that each conductive connection pattern 40 of the stacked semiconductor chips 90 overlaps each other. The aligned conductive connection patterns 40 are electrically connected to each other by a method such as reflow, and thus, each conductive connection pattern 40 of each semiconductor chip 90 is electrically connected to each other.

In the present exemplary embodiment, the semiconductor chip bodies 10 of the stacked semiconductor chips 90 are spaced apart from each other by the insulating adhesive member 70, but the conductive connection patterns 40 including solder are electrically connected to each other.

FIG. 5 is a cross-sectional view of the multilayer semiconductor package illustrated in FIG. 1.

1 and 5, the accommodating substrate 250 includes an accommodating part 255 and a connection pattern 260.

The storage substrate 250 including the storage portion 255 and the connection pattern 260 has a plate shape, for example. The accommodating substrate 250 having a plate shape may be, for example, a printed circuit board (PCB).

The accommodating part 255 may be disposed, for example, in the center portion of the accommodating substrate 250, and the accommodating part 255 is a through hole penetrating the upper surface 251 and the lower surface 252 of the accommodating substrate 250. Can be. Alternatively, the accommodating part 255 may be a recess formed to a predetermined depth from the upper surface 251 of the accommodating substrate 250, and the depth of the recess has a depth suitable for accommodating the semiconductor chip module 100. In the present exemplary embodiment, the accommodating part 255 is a through hole penetrating the upper surface 251 and the lower surface 252 of the accommodating substrate 250.

The semiconductor chip module 100 is accommodated in the accommodating part 255. In order to accommodate the semiconductor chip module 100 in the accommodating part 255, the accommodating part 255 has a size slightly larger than that of the semiconductor chip module 100.

The connection pattern 260 is formed on the inner side surface 255 of the accommodation substrate 250 formed by the accommodation unit 255. The connection pattern 260 is optional on the inner side 255 of the inner side 255 of the accommodating substrate 250 formed by the accommodating part 255 facing the conductive connection pattern 40 of the semiconductor chip module 100. Is formed.

Referring back to FIG. 5, the connection pattern 260 includes a plating pattern 262 and a solder pattern 264.

The plating pattern 262 is disposed on, for example, the inner surface 255 facing the conductive connection pattern 40, and the plating pattern 262 may be formed by, for example, various plating methods. have. Examples of materials that can be used as the plating pattern 262 may include titanium, nickel and vanadium, copper, and the like.

The solder pattern 264 is selectively formed on the plating pattern 262. The solder pattern 264 is formed on the plating pattern 262 by the plating method, for example. The solder pattern 264 is electrically connected to the conductive connection pattern 40 of the semiconductor chip module 100.

Ball land patterns 275 and 277 may be formed on the top and bottom surfaces 251 and 252 of the storage substrate 250 including the storage unit 255 and the connection pattern 260, respectively. ) Is electrically connected to the connection pattern 260 of the accommodation substrate 250.

Meanwhile, the solder balls 280 may be attached onto the ball land patterns 255 and 257.

The accommodation substrate 250 may further include a cover 285 and a molding member 287. The cover 285 and the molding member 287 protect the semiconductor chip module 100 accommodated in the accommodating part 255 of the accommodating substrate 250 from externally applied shocks and / or vibrations, and insulate from external conductors. It serves to quickly dissipate heat generated from the semiconductor chip module 100.

The cover 285 may cover the semiconductor chip module 100 exposed from the upper surface 251 of the accommodating substrate 250, and the cover 285 may include a metal. The molding member 287 may cover the semiconductor chip module 100 exposed from the bottom surface 252 of the accommodation substrate 250, and the molding member 287 may include an epoxy resin or the like.

In the present exemplary embodiment, at least two stacked semiconductor packages 400 illustrated in FIGS. 1 and 5 may be stacked as illustrated in FIG. 6. 1 and 5, at least two accommodating parts 255 are formed on the accommodating substrate 250, and each accommodating part 255 is formed as shown in FIG. 7. The semiconductor chip module 100 may be accommodated.

In order to electrically connect the semiconductor chips constituting the stacked semiconductor package, the conductive connection members exposed from the sides of the semiconductor chips are disposed to prevent the data storage capacity of each semiconductor chip from being reduced and to recess the stacked semiconductor packages. It is mounted in an accommodating substrate having the advantage of greatly reducing the thickness of the laminated semiconductor package.

In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

1 is an exploded perspective view illustrating a laminated semiconductor package according to an embodiment of the present invention.

FIG. 2 is a partially cutaway perspective view illustrating a semiconductor chip of any one of the semiconductor chip modules illustrated in FIG. 1.

3 is a cross-sectional view taken along the line II ′ of FIG. 2.

4 is an enlarged view of a portion 'A' of FIG. 3.

FIG. 5 is a cross-sectional view of the multilayer semiconductor package illustrated in FIG. 1.

6 is a cross-sectional view illustrating a laminated semiconductor package according to another embodiment of the present invention.

7 is a cross-sectional view illustrating a laminated semiconductor package according to still another embodiment of the present invention.

Claims (7)

A top surface, a bottom surface, a semiconductor chip body having side surfaces and circuit portions connecting the top surface and the bottom surface, pads connected to the circuit portion and disposed at edges of the top surface, and concave on the side surfaces corresponding to the respective pads; A semiconductor chip module disposed on a surface of the recess and connecting the upper and lower surfaces, and at least two semiconductor chips including a conductive connection pattern connected to the pad; And And an accommodating substrate having an accommodating part for accommodating the semiconductor chip module, the accommodating substrate having a connection pattern disposed on an inner side facing the semiconductor chip module among the inner surfaces formed by the accommodating part and connected to the conductive connection patterns. Laminated semiconductor package. The method of claim 1, And the receiving portion of the storage substrate is a through hole penetrating through an upper surface of the storage substrate and a lower surface facing the upper surface. The method of claim 2, The accommodating substrate may include a cover disposed on the upper surface to cover one side of the accommodating part and a molding member to cover the other side facing the one side of the accommodating substrate. The method of claim 1, The connection pattern may include a plating pattern disposed on the inner surface and a solder pattern formed on the plating pattern to be electrically connected to the conductive connection member. The method of claim 1, And a ball land pattern electrically connected to the connection pattern on at least one of an upper surface of the accommodating substrate and a lower surface of the accommodating substrate. The method of claim 5, At least two accommodating substrates in which the semiconductor chip module is accommodated are stacked, and ball land patterns facing each other among the stacked accommodating substrates are electrically connected by solder balls. The method of claim 1, The accommodating substrate may include at least two accommodating portions.

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