KR20090028993A - Overlay vernier - Google Patents

Overlay vernier Download PDF

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Publication number
KR20090028993A
KR20090028993A KR1020070094187A KR20070094187A KR20090028993A KR 20090028993 A KR20090028993 A KR 20090028993A KR 1020070094187 A KR1020070094187 A KR 1020070094187A KR 20070094187 A KR20070094187 A KR 20070094187A KR 20090028993 A KR20090028993 A KR 20090028993A
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KR
South Korea
Prior art keywords
vernier
trench
overlay
parent
mother
Prior art date
Application number
KR1020070094187A
Other languages
Korean (ko)
Inventor
이준석
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070094187A priority Critical patent/KR20090028993A/en
Publication of KR20090028993A publication Critical patent/KR20090028993A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

Abstract

According to the present invention, a second mother vernier having a mesa shape is formed inside a first mother vernier formed by a box-shaped trench, or the first mother vernier is formed of a mesa and the second mother vernier is a trench. By measuring or simultaneously measuring the first parent vernier or the second parent vernier as needed, it is possible to reduce the error of overlay vernier measurement due to the characteristics of the materials being used in the process or the variables of the process in a limited scribe lane. Discuss the technology.

Description

Overlay vernier {Overlay vernier}

The present invention relates to a semiconductor device, and more particularly, to form a mesa-shaped second mother vernier in a first mother vernier formed of a box-shaped trench, or the first mother vernier may be a mesa. The second parent vernier is formed into a trench, and the first parent vernier or the second parent vernier is measured or simultaneously measured as needed, depending on the characteristics of the material being used in the process in a limited scribe lane The present invention relates to an overlay vernier that can reduce measurement errors caused by variables.

In general, a lithography process is a process of performing exposure and development after applying a photoresist on a wafer, and is performed before an etching process or an ion implantation process requiring a mask.

Since the manufacturing process of the integrated device is a process of forming a multi-layer pattern by applying a lithography process or the like, accurate alignment between upper and lower layer patterns is required.

Overlay accuracy is an index that represents the alignment between the top and bottom layer patterns formed at the front and back stages of the process. This overlay accuracy acts as an important variable according to the high integration of the semiconductor device.

Here, overlay accuracy is measured using an overlay vernier formed in a scribe lane of the wafer.

The overlay vernier consists of the parent vernier (mother) formed in the lower layer in the previous process and the child vernier (son) formed in the current layer in the current process to measure the degree of misalignment to measure the alignment between the two layers. .

Typically, the parent vernier forms a pattern in the shape of a square strip of the same material as the actual pattern, and the vernier forms a square box type trench in a photoresist pattern.

In addition, the parent vernier forms a trench type or mesa type pattern according to the process of the lower layer, and the child vernier forms a trench type pattern to measure the parent vernier of the previous process in the current process. The method of forming the is mainly used.

However, when measuring overlay vernier to check the alignment between layers, the measurement of overlay vernier due to process characteristics such as step coverage, transparency or thickness of the deposition material used in the lower layer, or process dependent variables The value may have an error.

To reduce this error, different types of overlay vernier must be formed in different forms in the process.

However, as the degree of integration of semiconductor devices increases, the planar area occupied by the electronic devices constituting the semiconductor device shrinks, and as the mask process increases and various test patterns for monitoring increase, the out frame of the mask ( There is a problem that the space for forming all the desired overlay vernier on the outframe (or scribe lane) is insufficient.

It is an object of the present invention to provide an overlay vernier that can reduce measurement errors due to the nature of the material being used in the process in a limited scribe lane or to process dependent variables.

The overlay vernier according to the present invention

A first parent vernier implemented as a first trench in a box shape on the semiconductor substrate;

A second mother vernier having four bar-shaped mesas in the form of a picture frame in the first mother vernier; And

It characterized in that it comprises a ruler vernier implemented as a second trench in the form of a box exposing the second mother vernier.

The apparatus may further include a third trench formed in a box shape inside the first parent vernier,

The second parent vernier is formed inside the third trench,

The width of the third trench is formed to 10 ~ 18㎛,

The ruler vernier is formed of a photosensitive film,

The second parent vernier is formed inside the child vernier,

The width of the first mother vernier is formed to 14 ~ 22㎛, the line width is formed to be more than 0 and less than 4㎛,

The width of the second mother vernier is formed to be more than 0 and 6 ㎛ or less, the line width is formed to be more than 0 and 2 ㎛ or less,

The magnetic vernier is characterized in that the width is formed to 6 ~ 14㎛.

Meanwhile, the overlay vernier according to another embodiment of the present invention is

A first parent vernier embodied in a mesa in the form of a box on the semiconductor substrate;

A second parent vernier in which four bar trenches are formed in a picture frame in the first parent vernier; And

It characterized in that it comprises a ruler vernier implemented as a first trench in the form of a box exposing the second mother vernier.

In addition, the second mother vernier is formed inside the child vernier,

The semiconductor device further includes a second trench formed in a strip shape on the semiconductor substrate.

The first parent vernier is formed inside the second trench,

The line width of the second trench may be formed to be greater than 0 and less than 12 μm.

According to the present invention, a second mother vernier having a mesa shape is formed inside a first mother vernier formed with a box-shaped trench, or the first mother vernier is formed of a mesa, and the second mother vernier is formed of a trench to form a first mother vernier as needed. Alternatively, by measuring or simultaneously measuring the second parent vernier, there is an effect of reducing the overlay vernier measurement error due to the characteristics of the material being used in the process or the process dependent variable in a limited scribe lane.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the spirit of the present invention is thoroughly and completely disclosed, and the spirit of the present invention to those skilled in the art will be fully delivered. Also, like reference numerals denote like elements throughout the specification.

1 is a plan view showing an overlay vernier according to the present invention.

The overlay vernier forms a trench 13 having a predetermined size inside the first mother vernier 12 and the first mother vernier 12 implemented as a strip-shaped trench in a square box shape on the semiconductor substrate 10, A square box-shaped trench that exposes the second mother vernier 14 and the second mother vernier 14 in the form of a picture frame, which are formed of four bar-shaped mesa patterns inside the trench 13. Vernier 16 is included. Here, even if the second mother vernier 14 is formed inside the child vernier 16, there is no problem in the overlay measurement.

In addition, the width of the first parent vernier 12 is formed to 14 ~ 22㎛, the optimum width is 18㎛, the line width of the first parent vernier 12 is formed to be more than 0 and 4㎛ or less, the optimum line width is 2 Μm, the width of the trench 13 is 10 to 18 μm, the optimum width is 14 μm, and the width of the second parent vernier 14 is formed to be greater than 0 and 6 μm, and the optimum width is 3 μm. The line width of the second mother vernier 14 is formed to be greater than 0 and less than or equal to 2 μm. The optimum line width is 1 μm, and the width of the vernier 16 is 6 to 14 μm, and the optimum width is 10 μm. .

FIG. 2 is a cross-sectional view illustrating the overlay vernier illustrated in FIG. 1.

A first mother vernier 12 is formed in the semiconductor substrate 10 by a band trench, a trench 13 is formed in the first mother vernier 12, and four trenches 13 are formed in the trench 13. The photosensitive film 18 is formed by forming a second mother vernier 14 in the form of a picture frame formed of bar type patterns having a mesa shape, and forming a second mother vernier 14 by exposing the second mother vernier 14. To form the vernier 16.

3 is a plan view illustrating an overlay vernier according to another embodiment of the present invention.

The overlay vernier forms a strip-shaped trench 23 having a predetermined width in the form of a square box on the semiconductor substrate 10, and has a square box-shaped strip-shaped first parent vernier formed in a mesa pattern inside the trench 23. 22) a square box embodied in a box-shaped trench that exposes a second frame vernier 24 and a second parent vernier 24 in the form of a picture frame formed of four bar trenches in the first moverier 22. It includes a ruler vernier 26 of the form.

Here, the width of the first mother vernier 22 is formed to 14 ~ 22㎛, the optimum width is 18㎛, the line width of the first mother vernier 22 is formed to be more than 0 and 4㎛ or less, the optimum line width is 2 The width of the trench 23 is formed to be greater than 0 and 12 µm or less. The optimum width is 6 µm, and the width of the second mother vernier 24 is formed to be greater than 0 and 6 µm or less. The optimum width is 3 µm. The line width of the second mother vernier 24 is formed to be greater than 0 and 2 μm or less. The optimum line width is 1 μm, and the width of the child vernier 26 is 6 to 14 μm, and the optimum width is 10 μm. .

4 is a cross-sectional view illustrating the overlay vernier illustrated in FIG. 3.

A band trench 23 having a predetermined width is formed in the semiconductor substrate 10, and the first mother vernier 22 is formed in the trench 23 in a mesa pattern, and the first mother vernier 22 is formed inside the trench 23. The second mother vernier 24 is formed in the trench, and the magnetic vernier 26 is formed using the photosensitive film 28 in the box-shaped trench exposing the second mother vernier 24.

According to the present invention as described above, the second mother vernier having a mesa shape is formed inside the first mother vernier formed with the box-shaped trench, or the first mother vernier is formed with the mesa and the second mother vernier is formed with the trench as necessary. Disclosed is a technique for measuring an overlay vernier measurement error due to a characteristic of a material being used in a process or a variable according to a process by measuring or simultaneously measuring a first parent vernier or a second parent vernier. .

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1 is a plan view showing an overlay vernier according to the present invention.

FIG. 2 is a cross-sectional view illustrating the overlay vernier illustrated in FIG. 1.

3 is a plan view illustrating an overlay vernier according to another embodiment of the present invention.

4 is a cross-sectional view illustrating the overlay vernier illustrated in FIG. 3.

<Description of the symbols for the main parts of the drawings>

10: semiconductor substrate 12, 22: first parent vernier

13, 23: trench 14, 24: second parent vernier

16, 26: purple vernier 18: photosensitive film

Claims (14)

A first parent vernier implemented as a first trench in a box shape on the semiconductor substrate; A second mother vernier having four bar-shaped mesas in the form of a picture frame in the first mother vernier; And An overlay vernier comprising a vernier vernier implemented as a second trench in the form of a box exposing the second parent vernier. The method of claim 1, The overlay vernier further comprises a third trench implemented in a box shape inside the first parent vernier. The method of claim 2, And the second parent vernier is formed inside the third trench. The method of claim 2, Overlay vernier, characterized in that the width of the third trench is formed to 10 ~ 18㎛. The method of claim 1, The ruler vernier is overlay vernier, characterized in that formed by a photosensitive film. The method of claim 1, Overlay vernier, characterized in that the second parent vernier is formed inside the child vernier. The method of claim 1, An overlay vernier, characterized in that the width of the first mother vernier is formed to 14 ~ 22㎛, the line width is formed to 0 and less than 4㎛. The method of claim 1, An overlay vernier, wherein the width of the second mother vernier is formed to be greater than 0 and 6 µm or less, and the line width is formed to be greater than 0 and 2 µm or less. The method of claim 1, The overlay vernier, characterized in that the width of the magnetic vernier is formed to 6 ~ 14㎛. A first parent vernier embodied in a mesa in the form of a box on the semiconductor substrate; A second parent vernier in which four bar trenches are formed in a picture frame in the first parent vernier; And An overlay vernier comprising a vernier vernier implemented as a first trench in the form of a box exposing the second parent vernier. The method of claim 10, Overlay vernier, characterized in that the second parent vernier is formed inside the child vernier. The method of claim 10, The overlay vernier of the semiconductor substrate further comprises a second trench implemented in a strip form. The method of claim 12, And the first parent vernier is formed inside the second trench. The method of claim 12, Overlay vernier, characterized in that the line width of the second trench is formed to more than 0 and less than 12㎛.
KR1020070094187A 2007-09-17 2007-09-17 Overlay vernier KR20090028993A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070094187A KR20090028993A (en) 2007-09-17 2007-09-17 Overlay vernier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070094187A KR20090028993A (en) 2007-09-17 2007-09-17 Overlay vernier

Publications (1)

Publication Number Publication Date
KR20090028993A true KR20090028993A (en) 2009-03-20

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