CN116931389B - Line width measuring method - Google Patents
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- CN116931389B CN116931389B CN202311195651.6A CN202311195651A CN116931389B CN 116931389 B CN116931389 B CN 116931389B CN 202311195651 A CN202311195651 A CN 202311195651A CN 116931389 B CN116931389 B CN 116931389B
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000012360 testing method Methods 0.000 claims abstract description 215
- 238000005259 measurement Methods 0.000 claims abstract description 79
- 230000003287 optical effect Effects 0.000 claims abstract description 37
- 238000001259 photo etching Methods 0.000 claims abstract description 20
- 230000000694 effects Effects 0.000 claims abstract description 17
- 238000000691 measurement method Methods 0.000 claims description 38
- 229920002120 photoresistant polymer Polymers 0.000 claims description 35
- 238000000206 photolithography Methods 0.000 claims description 12
- 238000004088 simulation Methods 0.000 claims description 9
- 238000012937 correction Methods 0.000 claims description 6
- 238000006386 neutralization reaction Methods 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000006552 photochemical reaction Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 17
- 238000001459 lithography Methods 0.000 description 15
- 238000011161 development Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 7
- 238000013461 design Methods 0.000 description 3
- 238000001878 scanning electron micrograph Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000010408 film Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000008033 biological extinction Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004626 scanning electron microscopy Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/708—Construction of apparatus, e.g. environment aspects, hygiene aspects or materials
- G03F7/7085—Detection arrangement, e.g. detectors of apparatus alignment possibly mounted on wafers, exposure dose, photo-cleaning flux, stray light, thermal load
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Abstract
The invention provides a line width measuring method, firstly selecting a part of test patterns containing optical proximity effect from a plurality of test patterns as measuring point patterns, and obtaining position information of the measuring point patterns; establishing an automatic measurement program through the position information of the measurement point graph to acquire wafer data corresponding to the measurement point graph, wherein the wafer data comprises the line width of an actual measurement point graph corresponding to the measurement point graph on the wafer; establishing a photoetching model through the wafer data to form a new layout through the photoetching model, wherein the new layout comprises a plurality of new test patterns; and acquiring the position information of the new test pattern, and establishing a new automatic measurement program through the position information of the new test pattern to acquire new wafer data corresponding to the new test pattern, wherein the new wafer data comprises the line width of the new test pattern corresponding to the actual pattern on the wafer. The line width of the actual graph on the wafer can be measured by only establishing an automatic measuring program, and the success rate of line width measurement can be improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a line width measuring method.
Background
With the development of semiconductor technology, the critical dimensions (Critical Dimension, CD) of the semiconductor device, such as the line width, are smaller and smaller, and the chip integration is higher and higher, and the semiconductor manufacturing process is required to be more and more strictly, so that the error of each step must be reduced as much as possible during the process, and the device failure caused by the error is reduced. Currently, line widths (linewidth) of patterns formed by etching a substrate using a photoresist or other thin film stack layer as a mask are measured mainly by scanning electron microscopy (SEM, scanning Electron Microscope). Scanning electron microscopes require the creation of an automatic measurement program from the original layout of the semiconductor device, by which the line width of the pattern is measured. However, with the rapid development of integrated circuit designs, the size of semiconductor devices is continuously reduced, image distortion occurs during the process of transferring the pattern on the original layout onto the wafer, and the pattern formed on the wafer is deformed and deviated compared with the pattern of the original layout, that is, optical proximity effect (opticalproximity effect, OPE) occurs. Therefore, a measurement failure phenomenon occurs when the automatic measurement program measures the line width of the pattern, and a plurality of automatic measurement programs need to be established during the measurement.
Disclosure of Invention
The invention aims to provide a line width measuring method which is used for reducing the number of automatic measuring programs established in the line width measuring process and improving the success rate of line width measurement.
In order to achieve the above object, the present invention provides a line width measuring method, comprising: providing an original layout, wherein the original layout comprises a plurality of test patterns; selecting a part of test patterns including optical proximity effect from a plurality of test patterns as measurement point patterns; acquiring the position information of the measuring point graph, and establishing an automatic measuring program according to the position information of the measuring point graph to acquire wafer data corresponding to the measuring point graph, wherein the wafer data comprises the line width of an actual measuring point graph on a wafer corresponding to the measuring point graph; establishing a photoetching model through the wafer data, and carrying out optical proximity effect correction on a plurality of test patterns in the original layout through the photoetching model to form a new layout, wherein the new layout comprises a plurality of new test patterns; and acquiring the position information of a plurality of new test patterns, and establishing a new automatic measurement program according to the position information of the new test patterns so as to acquire new wafer data corresponding to the new test patterns, wherein the new wafer data comprises the line width of the actual patterns on the wafer corresponding to the new test patterns.
Optionally, in the line width measurement method, before acquiring the position information of the measurement point pattern, the line width measurement method further includes: transferring a plurality of test patterns in the original layout to a test mask; and transferring the test patterns on the test mask plate to the wafer by utilizing a photoetching process so as to form a plurality of actual patterns corresponding to the test patterns on the wafer, wherein the actual patterns comprise the actual measuring point patterns.
Optionally, in the line width measurement method, the plurality of test patterns include a plurality of first test patterns, a plurality of second test patterns, and a plurality of third test patterns, the third test patterns and the second test patterns are two-dimensional patterns, the third test patterns and the second test patterns are different in shape, and the first test patterns are one-dimensional patterns.
Optionally, in the line width measurement method, the second test pattern includes a plurality of second sub-test patterns, the second sub-test patterns in the first direction are arranged in parallel, the second sub-test patterns in the second direction are located on the same straight line, and the first direction and the second direction are mutually perpendicular.
Optionally, in the line width measurement method, the measurement point pattern includes a plurality of the first test patterns, or the measurement point pattern includes a plurality of the first test patterns and the second test patterns.
Optionally, in the line width measurement method, all the first test patterns in the measurement point patterns are located in a plurality of measurement areas, each measurement area has at least one first test pattern therein, a distance between the first test patterns in all the measurement areas is gradually increased, and a distance between the first test patterns in each measurement area is the same, where a line width of the first test pattern in the measurement point patterns is smaller than an exposure wavelength in the photolithography process.
Optionally, in the line width measurement method, the new wafer data further includes a pitch between actual patterns on the wafer.
Optionally, in the line width measurement method, the method for obtaining wafer data corresponding to the measurement point pattern includes: acquiring an image of the wafer through a scanning electron microscope; identifying an alignment mark in the image of the wafer, wherein the shape of the alignment mark is a cross; and determining an image of the measuring point graph according to the position information of the alignment mark in the original layout and the position information of the measuring point graph, and obtaining the wafer data according to the image of the measuring point graph.
Optionally, in the line width measurement method, the photoresist pattern includes an optical pattern and a photoresist pattern.
Optionally, in the line width measurement method, the method for establishing an optical model includes: establishing the optical model according to the wafer data, the optical parameters of the wafer and the optical system parameters; the method for establishing the photoresist model comprises the following steps: and establishing the photoresist model according to the threshold condition of the photochemical reaction of the photoresist, the diffusion length and the neutralization coefficient of the photoresist.
In the line width measuring method provided by the invention, a part of test patterns containing optical proximity effect is selected from a plurality of test patterns to serve as measuring point patterns, the position information of the measuring point patterns is obtained, then an automatic measuring program is established through the position information of the measuring point patterns to obtain wafer data corresponding to the measuring point patterns, and the wafer data comprises the line width of the actual measuring point patterns of the measuring point patterns corresponding to the wafer; then, establishing a photoetching model through wafer data, and carrying out optical proximity effect correction on a plurality of test patterns in an original layout through the photoetching model to form a new layout, wherein the new layout comprises a plurality of new test patterns; and acquiring the position information of the new test pattern, and establishing a new automatic measurement program through the position information of the new test pattern to acquire new wafer data corresponding to the new test pattern, wherein the new wafer data comprises the line width of the new test pattern corresponding to the actual pattern on the wafer. Therefore, when the line width of the actual graph on the wafer is measured, the line width of the actual graph on the wafer can be measured only by establishing an automatic measurement program, a new layout is formed by the photoetching model established by the wafer data, the position deviation between the new test graph in the new layout and the actual graph on the wafer can be reduced, the shape of the actual graph on the wafer can be accurately predicted by the photoetching model, and the success rate of the line width measurement of the actual graph on the wafer is improved.
Drawings
Fig. 1 is a flow chart of a line width measurement method according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a test pattern in a line width measurement method according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a measurement point pattern in the line width measurement method according to the embodiment of the present invention.
Fig. 4 is a wafer SEM schematic diagram of a line width measurement method according to an embodiment of the invention.
Fig. 5 is a schematic diagram of a test pattern and an exposure simulation pattern in the line width measurement method according to the embodiment of the invention.
Fig. 6 is a schematic diagram of a test pattern and a new test pattern in the line width measurement method according to the embodiment of the invention.
Fig. 7 is an SEM schematic diagram of test patterns and actual patterns in the line width measurement method according to the embodiment of the invention.
Fig. 8 is a schematic diagram of a test pattern and a new test pattern formed by a lithography model in the line width measurement method according to the embodiment of the present invention.
Fig. 9 is a schematic diagram of a test pattern and a new test pattern formed by another photolithography model in the line width measuring method according to the embodiment of the present invention.
Fig. 10 is a schematic diagram of a non-lithographic pattern in a line width measurement method according to an embodiment of the invention.
Wherein reference numerals are as follows: 10-test patterns; 20-new test patterns; 30-exposing the simulated patterns; 40-actual graph; 50-non-photoresist pattern, 60-measuring frame; 110-a first test pattern; 120-a second test pattern; 121-a second subtest pattern; 130-a third test pattern; 131-third subtest pattern.
Detailed Description
The line width measuring method according to the present invention will be described in further detail with reference to the accompanying drawings and specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 1 is a flow chart of a line width measurement method according to an embodiment of the present invention. As shown in fig. 1, the present embodiment provides a line width measurement method, including: step S1: providing an original layout, wherein the original layout comprises a plurality of test patterns; step S2: selecting a part of test patterns including optical proximity effect from a plurality of test patterns as measurement point patterns; step S3: acquiring the position information of the measuring point graph, and establishing an automatic measuring program according to the position information of the measuring point graph to acquire wafer data corresponding to the measuring point graph, wherein the wafer data comprises the line width of an actual graph of the measuring point graph on a wafer; step S4: establishing a photoetching model through the wafer data, and carrying out optical proximity effect correction on a plurality of test patterns in the original layout through the photoetching model to form a new layout, wherein the new layout comprises a plurality of new test patterns; step S5: and acquiring the position information of the new test pattern, and establishing a new automatic measurement program through the position information of the new test pattern to acquire new wafer data corresponding to the new test pattern, wherein the new wafer data comprises the line width of the actual pattern of the new test pattern corresponding to the wafer.
The line width measuring method provided in this embodiment will be described in more detail with reference to fig. 2 to 9.
Fig. 2 is a schematic diagram of a test pattern in a line width measurement method according to an embodiment of the present invention. Referring to fig. 2, in step S1, an original layout including a plurality of test patterns 10 is provided. In this embodiment, the original layout is stored in an original layout file. The original layout file refers to a layout file containing design graphics, which is designed and formed by using an EDA tool. Typically, the original layout file is a layout file that has been validated by DRC (design rulecheck). The file format of the original layout may be a GDS format. In other embodiments, the file format of the original layout may be other formats such as OASIS.
Furthermore, the original layout is a preset graph which needs to be generated in the mask, and the original layout can be determined according to different semiconductor process requirements.
As shown in fig. 2, the plurality of test patterns 10 includes a plurality of first test patterns 110, a plurality of second test patterns 120, and a plurality of third test patterns 130, the third test patterns 130 and the second test patterns 120 are two-dimensional patterns, and the shapes of the third test patterns 130 and the second test patterns 120 are different, and the first test patterns 110 are one-dimensional patterns. The one-dimensional pattern is a pattern having periodicity in only one direction, and has a relatively simple structure, such as a line. The two-dimensional pattern is a pattern having periodicity in both directions, and the structure is relatively complex.
Specifically, the second test pattern 120 includes a plurality of second sub-test patterns 121, the second sub-test patterns 121 in the first direction Y are arranged in parallel, the second sub-test patterns 121 in the second direction X are located on the same line, and the first direction Y is perpendicular to the second direction X.
As shown in fig. 2, the third test pattern 130 includes a vertical third sub-test pattern 131, two sides of the vertical third sub-test pattern 131 are respectively provided with a plurality of horizontal third sub-test patterns 131, the plurality of horizontal third sub-test patterns 131 on each side of the vertical third sub-test pattern 131 are arranged in a row, and the plurality of horizontal third sub-test patterns 131 in each row are arranged in parallel with each other.
Fig. 3 is a schematic diagram of a measurement point pattern in the line width measurement method according to the embodiment of the present invention. Referring to fig. 3, step S2 is performed, wherein a portion of the test patterns 10 including the optical proximity effect is selected as a measurement point pattern from the plurality of test patterns 10, and the test patterns 10 including the optical proximity effect refer to patterns having a line width smaller than an exposure wavelength in a photolithography process. In this embodiment, as shown in fig. 3, the measurement point pattern includes a plurality of the first test patterns 110. Because the first test pattern 110 is a one-dimensional pattern, the measurement deviation of the wafer data corresponding to the first test pattern 110 is smaller, so that the accuracy of the subsequently acquired wafer data can be improved, and the difficulty of acquiring the wafer data can be reduced.
Further, as shown in fig. 3, all the first test patterns 110 in the measurement point patterns are located in a plurality of measurement areas, in this embodiment, the example is described by taking that all the first test patterns 110 in the measurement point patterns are located in four measurement areas, for example, a first measurement area a, a second measurement area B, a third measurement area C and a fourth measurement area D, where the line widths of the first test patterns 110 in the measurement point patterns may be different.
More specifically, each of the measurement regions has at least one of the first test patterns 110 therein, wherein the pitch between the first test patterns 110 in all of the measurement regions is gradually increased, for example, the pitch between the first test patterns 110 in the second measurement region B is larger than the pitch between the first test patterns 110 in the first measurement region a. And the first test patterns 110 in each measurement region have the same pitch, for example, the first test patterns 110 in the second measurement region B have the same pitch, and the first test patterns 110 in the first measurement region a have the same pitch. In this way, the accuracy of the subsequently formed lithographic model may be improved.
Preferably, the line width of the first test pattern 110 in the measurement point pattern is smaller than the exposure wavelength in the photolithography process. In this way, the first test pattern 110 in the measurement point pattern can be made to contain more optical proximity effect corresponding to the actual pattern 40 on the wafer, so as to improve the accuracy of the morphology of the actual pattern 40 on the wafer simulated by the lithography model formed later.
In other embodiments, the measurement point pattern may include a plurality of the first test pattern 110 and the second test pattern 120.
Next, referring to fig. 4, an SEM of a wafer in the line width measurement method according to the present embodiment is shown. As shown in fig. 4, transferring a plurality of test patterns 10 in the original layout to a test mask; the plurality of test patterns 10 on the test mask are transferred onto the wafer by using a photolithography process to form a plurality of actual patterns 40 corresponding to the plurality of test patterns 10 on the wafer, that is, a patterned photoresist layer is formed on the wafer, and the patterned photoresist layer has the plurality of actual patterns 40 therein. The actual pattern 40 includes the actual measurement point pattern, that is, a portion of the actual pattern 40 on the wafer is used as the actual measurement point pattern. Wherein the photolithography process includes sequentially performing exposure, baking, and development. The wafer may include a substrate, and a dielectric layer, an anti-reflection layer, and the like sequentially formed on the substrate.
And then, executing step S3, obtaining the position information of the measuring point graph, and establishing an automatic measuring program according to the position information of the measuring point graph to obtain the wafer data corresponding to the measuring point graph, wherein the wafer data comprises the line width of the actual measuring point graph of the measuring point graph corresponding to the wafer. The position information of the measurement point pattern includes coordinates of the measurement point pattern.
Specifically, the method for acquiring the wafer data corresponding to the measuring point pattern comprises the following steps: firstly, obtaining an image of the wafer, namely an SEM image, through a scanning electron microscope; then, an alignment mark (an alignment mark for alignment is usually provided on the wafer) in the image of the wafer is identified, the shape of the alignment mark is a cross, that is, the alignment mark contains position information in a first direction Y and position information in a second direction X, thereby being capable of reducing alignment offset in the first direction Y and the second direction X; and then, determining an image of the measuring point graph according to the position information of the alignment mark in the original layout and the position information of the measuring point graph, and obtaining the wafer data according to the image of the measuring point graph. The method comprises the steps of determining position information of a measuring point graph on an original layout based on the original layout, placing a measuring frame (shown in reference to fig. 2 and 4) on the position of the measuring point graph, aligning an SEM image of the measuring point graph with the graph in the original layout, determining the position of the measuring frame on the SEM image of the measuring point graph based on an alignment result, measuring and outputting a measuring result, and accordingly obtaining wafer data according to the position information of the measuring point graph in the original layout. Further, the height of the measuring frame 60 may be one third to two thirds of the line width of the first test pattern 110 in the measuring point pattern, so as to reduce the influence of the line edge roughness on the measuring result and improve the accuracy of the measuring result.
That is, by passing the position information of the measurement point pattern, an automatic measurement program is established in the scanning electron microscope so as to measure the line width of the actual measurement point pattern corresponding to the measurement point pattern on the wafer, thereby obtaining the wafer data.
Referring to fig. 6, a schematic diagram of a test pattern and a new test pattern in the line width measurement method according to the embodiment of the invention is shown. As shown in fig. 6, step S4 is performed to build a lithography model from the wafer data, and perform optical proximity effect correction on the test pattern 10 of the original layout by the lithography model to form a new layout including a plurality of new test patterns 20. Wherein the lithography model is used to simulate the morphology of the actual pattern on the wafer, i.e. the new test pattern 20 is obtained by simulating the morphology of the actual pattern on the wafer. The new test pattern 20 includes a new first test pattern, a new second test pattern, and a new third test pattern, where the new third test pattern and the new second test pattern are two-dimensional patterns, and the new first test pattern is a one-dimensional pattern. The lithography model includes an optical model and a photoresist model.
Fig. 5 is a schematic diagram of a test pattern and an exposure simulation pattern in the line width measurement method according to the embodiment of the invention. As shown in fig. 5, the optical model is used for performing exposure simulation on all test patterns 10 in the original layout to simulate the morphology of an actual pattern 40 on the exposed wafer in the photolithography process, thereby obtaining an exposure simulation pattern 30.
As shown in fig. 6, the photoresist model is used to perform development simulation on the exposure simulation pattern 30, that is, the photoresist model is superimposed on the optical model to obtain the morphology of the actual pattern 40 on the developed wafer, so as to obtain a development simulation pattern, and the development simulation pattern is used as a new test pattern 20. Fig. 7 is an SEM schematic diagram of test patterns and actual patterns in the line width measurement method according to the embodiment of the invention. As can be seen from comparing fig. 5, 6 and 7, the lithography model can more accurately simulate the morphology of the actual pattern 40 on the wafer than the optical model, so that the morphology of the new test pattern 20 is close to the morphology of the actual pattern 40.
Fig. 8 is a schematic diagram of a test pattern and a new test pattern formed by a lithography model in the line width measurement method according to the embodiment of the present invention. In one lithography model, the measurement point pattern corresponding to the wafer data of the measurement point pattern includes a plurality of first test patterns 110, and since the first test patterns are one-dimensional patterns, the acquisition of the wafer data is simpler. Comparing fig. 7 and fig. 8, it can be seen that the appearance of the new test pattern 20 simulated by the photolithography model is close to the appearance of the actual pattern 40, i.e. the accuracy of the new test pattern 20 formed by simulating the actual pattern by the photolithography model is higher.
Fig. 9 is a schematic diagram of a test pattern and a new test pattern formed by another photolithography model in the line width measuring method according to the embodiment of the present invention. In another lithography model, the measurement point pattern corresponding to the wafer data of the measurement point pattern includes a plurality of first test patterns 110 and a plurality of second test patterns 120. Comparing fig. 9 and fig. 8, it can be seen that the shapes of the actual patterns 40 on the wafer simulated by the two lithography models are relatively close, so that the shapes of all the actual patterns 40 on the wafer can be accurately simulated by using only the first test pattern 110 as the measurement point pattern, that is, in this embodiment, the lithography model established by the wafer data corresponding to the one-dimensional pattern can accurately simulate not only the one-dimensional pattern (the actual pattern on the wafer corresponding to the first test pattern) in the actual pattern on the wafer, but also the shapes of the two-dimensional patterns (the actual patterns on the wafer corresponding to the second test pattern and the third test pattern) in the actual pattern on the wafer.
Further, the method for establishing the optical model comprises the following steps: and establishing the optical model according to the wafer data, the optical parameters of the wafer and the optical system parameters, wherein the optical parameters of the wafer comprise refractive indexes of all film layers in the wafer, extinction coefficients of all film layers in the wafer, the thickness of the wafer and the thickness of the photoresist layer. The optical system parameters include numerical aperture, light source type and light source size of the lithography machine.
The method for establishing the photoresist model comprises the following steps: and establishing the photoresist model according to the threshold condition of the photochemical reaction of the photoresist, the diffusion length and the neutralization coefficient of the photoresist. Wherein the neutralization coefficient is a reaction rate coefficient at the time of neutralization of the developing solution in the developing process and the acid in the photoresist.
In this embodiment, the photoresist pattern after development can be simulated by the photoresist model, that is, the pattern of the actual pattern 40 formed on the wafer after development of the test pattern 10 in the photolithography process can be simulated, so that the success rate of line width measurement can be improved.
Next, step S5 is executed to obtain the position information of the new test patterns 20, and a new automatic measurement procedure is established according to the position information of the new test patterns 20 to obtain new wafer data corresponding to the new test patterns 20, where the new wafer data includes line widths of the actual patterns 40 on the wafer corresponding to the new test patterns 20. In this way, when measuring the line width of the actual pattern on the wafer, the line width of the actual pattern 40 on the wafer can be measured by only establishing an automatic measurement program, and a new layout is formed by establishing a lithography model through wafer data, so that the position deviation between the new test pattern 20 in the new layout and the actual pattern 40 on the wafer can be reduced, the shape of the actual pattern on the wafer can be accurately predicted through the lithography model, and the success rate of the line width measurement of the actual pattern 40 on the wafer is improved.
In this embodiment, the position information of the plurality of new test patterns 20 may be obtained by a scanning electron microscope, the image of the wafer may be obtained by the scanning electron microscope, the image of the actual pattern 40 may be determined according to the position information of the new test pattern 20 in the new layout, and the new wafer data may be obtained according to the image of the actual pattern 40.
Fig. 10 is a schematic diagram of a non-lithographic pattern in a line width measurement method according to an embodiment of the invention. As shown in fig. 10, the actual pattern 40 on the wafer may be a photoresist pattern. A non-photoresist pattern 50 (e.g., a dielectric layer pattern, which may be made of silicon, silicon germanium, or a low-k material, an ultra-low-k material, or a metal) is provided between adjacent ones of the actual patterns 40. In addition, the new wafer data also includes a spacing d between actual patterns 40 on the wafer, i.e., a line width of non-photoresist patterns 50. As shown in fig. 9, the measuring frame 60 may be used to obtain the line width of the non-photoresist pattern 50 based on the new layout corresponding to the non-photoresist pattern 50.
The success rate of the line width of the actual pattern obtained by adopting the two-dimensional pattern in the original layout, namely the second test pattern and the third test pattern is 33.8% -39.6%, the success rate of the line width of the actual pattern obtained by adopting the two-dimensional pattern in the new layout, namely the new second test pattern and the new third test pattern is 95.1% -98.2%, the success rate of the line width of the non-photoresist pattern 50 obtained by adopting the original layout is 2.0%, and the success rate of the line width of the non-photoresist pattern 50 obtained by adopting the new layout is 98.2%, so that the success rate of the new wafer data obtained by adopting the new test pattern in the new layout is higher than the success rate of the wafer data obtained by adopting the test pattern in the original layout.
In summary, in the line width measurement method provided by the embodiment of the invention, a part of test patterns including optical proximity effect are selected from a plurality of test patterns as measurement point patterns, the position information of the measurement point patterns is obtained, then an automatic measurement program is established through the position information of the measurement point patterns to obtain wafer data corresponding to the measurement point patterns, and the wafer data comprises the line width of the actual measurement point patterns corresponding to the measurement point patterns on the wafer; then, establishing a photoetching model through wafer data, and carrying out optical proximity effect correction on a plurality of test patterns in the original layout through the photoetching model to form a new layout, wherein the new layout comprises a plurality of new test patterns; and acquiring the position information of the new test pattern, and establishing a new automatic measurement program through the position information of the new test pattern to acquire new wafer data corresponding to the new test pattern, wherein the new wafer data comprises the line width of the new test pattern corresponding to the actual pattern on the wafer. Therefore, when the line width of the actual graph on the wafer is measured, the line width of the actual graph on the wafer can be measured only by establishing an automatic measurement program, a new layout is formed by establishing a photoetching model through wafer data, the position deviation between the new test graph in the new layout and the actual graph on the wafer can be reduced, the shape of the actual graph on the wafer can be accurately predicted through the photoetching model, and the success rate of line width measurement of the actual graph on the wafer is improved.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (8)
1. A line width measurement method, comprising:
providing an original layout, wherein the original layout comprises a plurality of test patterns, and the plurality of test patterns comprise a plurality of first test patterns and a plurality of second test patterns;
selecting a test pattern with part including an optical proximity effect from a plurality of test patterns as a measurement point pattern, wherein the measurement point pattern comprises a plurality of first test patterns selected from the plurality of test patterns, or the measurement point pattern comprises a plurality of first test patterns and second test patterns selected from the plurality of test patterns, all the first test patterns in the measurement point pattern are positioned in a plurality of measurement areas, at least one first test pattern is arranged in each measurement area, and the intervals between the first test patterns in all the measurement areas are gradually increased;
acquiring the position information of the measuring point graph, and establishing an automatic measuring program according to the position information of the measuring point graph to acquire wafer data corresponding to the measuring point graph, wherein the wafer data comprises the line width of an actual measuring point graph on a wafer corresponding to the measuring point graph, and the actual measuring point graph is formed on the wafer through a photoetching process;
establishing a photoetching model through the wafer data, and carrying out optical proximity effect correction on a plurality of test patterns in the original layout through the photoetching model to form a new layout, wherein the new layout comprises a plurality of new test patterns, the photoetching model comprises an optical model and a photoresist model, the optical model is used for carrying out exposure simulation on all the test patterns in the original layout, and the photoresist model is used for simulating the developed photoresist morphology; the method comprises the steps of,
acquiring position information of a plurality of new test patterns, and establishing a new automatic measurement program according to the position information of the new test patterns to acquire new wafer data corresponding to the new test patterns, wherein the new wafer data comprises line widths of actual patterns on the wafer corresponding to the new test patterns.
2. The line width measurement method according to claim 1, wherein before acquiring the position information of the measurement point pattern, the line width measurement method further comprises:
transferring a plurality of test patterns in the original layout to a test mask;
and transferring the test patterns on the test mask plate to the wafer by utilizing a photoetching process so as to form a plurality of actual patterns corresponding to the test patterns on the wafer, wherein the actual patterns comprise the actual measuring point patterns.
3. The line width measurement method of claim 2, wherein the plurality of test patterns further includes a plurality of third test patterns, the third test patterns and the second test patterns are two-dimensional patterns, the third test patterns and the second test patterns are different in shape, and the first test patterns are one-dimensional patterns.
4. The line width measuring method of claim 3, wherein the second test pattern comprises a plurality of second sub-test patterns, the second sub-test patterns in a first direction are arranged in parallel, the second sub-test patterns in a second direction are positioned on the same line, and the first direction and the second direction are perpendicular to each other.
5. The line width measurement method of claim 1, wherein a pitch between first test patterns in each of the measurement areas is the same, wherein a line width of the first test pattern in the measurement point pattern is smaller than an exposure wavelength in the photolithography process.
6. The line width measurement method of claim 1, wherein the new wafer data further comprises a spacing between actual patterns on the wafer.
7. The line width measurement method of claim 1, wherein the method for obtaining wafer data corresponding to the measurement point pattern comprises:
acquiring an image of the wafer through a scanning electron microscope;
identifying an alignment mark in the image of the wafer, wherein the shape of the alignment mark is a cross;
and determining an image of the measuring point graph according to the position information of the alignment mark in the original layout and the position information of the measuring point graph, and obtaining the wafer data according to the image of the measuring point graph.
8. The line width measurement method according to claim 1, wherein the method for creating the optical model comprises: establishing the optical model according to the wafer data, the optical parameters of the wafer and the optical system parameters;
the method for establishing the photoresist model comprises the following steps: and establishing the photoresist model according to the threshold condition of the photochemical reaction of the photoresist, the diffusion length and the neutralization coefficient of the photoresist.
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