KR20090028937A - Data modulation method, modulator, recording method, and recording apparatus - Google Patents

Abstract

A data modulating method and apparatus and a recording method and apparatus are provided to facilitate the change of k-constraint condition by bit flip and prevent error propagation by bit flip. A data modulating method comprises the steps of: producing a channel sequence about input sequence; determining whether RLL(Run Length Limit) condition is violated; and, when the RLL condition is violated, performing bit flip at the position before the violation occurrence position among the bits included in the channel sequence. The bit flip performing step includes determining the bit flip position in order to prevent error propagation in decoding.

Description

Data modulation method, modulation device, recording method and recording device {DATA MODULATION METHOD, MODULATOR, RECORDING METHOD, AND RECORDING APPARATUS}

The present invention relates to a data modulation method, a modulation device, a recording method, and a recording device, and more particularly, to a method and apparatus for modulating data recorded on an optical recording medium, and a recording method and apparatus using the same.

A general recording system uses a modulation code, which is used to reduce distortion of a reproduction signal caused by interference between adjacent symbols in the reproduction portion of the recording system and to provide smooth timing recovery.

The modulation code at this time may be expressed as (d, k), which is called a run length limit (RLL) code. Here, d is a constraint condition that means the minimum number of zeros that may exist between 1 and 1 of the modulation code, and is a condition for reducing distortion of a signal caused by interference between adjacent symbols. In addition, k is a constraint condition that means the maximum number of zeros that may exist between 1 and 1, and is a condition for timing recovery.

When designing a modulation code, observe the channel sequence that is the output of the modulation code encoder and add data 0 to 1 at that position. There is a bit flip method that adds a k-restriction condition.

In other words, the bit flip method is a method of adding a k-restraint condition by applying an error to a channel sequence. In this method, an error is applied to a channel sequence, which is a sequence before being recorded on the recording medium, so that an error is included in the sequence recorded on the recording medium.

Therefore, if a bit flip occurs frequently in such a bit flip method, it is difficult to restore the original data during demodulation, and there is a limit in improving the recording density even when the bit flip is possible. In particular, this problem becomes more serious because modulation codes for a recording system have an error propagation characteristic in which a bit error causes multiple bit errors in decoding due to the design.

Accordingly, the present invention is to solve the above problems, an object of the present invention is to provide a demodulation method, a demodulation device, a recording method and a recording device that can easily restore the original data, improve the recording density have.

In order to achieve the above object, a data modulation method according to the present invention includes generating a channel sequence for an input sequence, determining whether a run length limit (RLL) condition is violated, and a run length limit condition. In the case of violating the bit sequence, performing a bit flip at a position before the violation of the run length constraint occurs among the bits included in the channel sequence.

Performing a bit flip may include determining a bit flip position such that there is no error propagation in decoding.

In determining the bit flip position, the bit flip position may be determined based on the violation position of the run length constraint and the length of the codeword.

In determining the bit flip position, the bit flip position may be determined based on the remainder of the violation position divided by the length of the codeword.

The run length constraint is a condition for the maximum number of zeros existing between 1 and 1 in the channel sequence, and bit flipping may be performed by converting 0 bits of a specific position into 1 bit.

The method may further include setting a run length constraint based on the statistical check of the number of bit flips.

In the step of generating a channel sequence for the input sequence, a channel sequence for the input sequence may be generated using a modulation table.

The modulation table may include at least one state, code words corresponding to the input code, and information designating the next state.

The modulation table may generate a channel sequence in which the minimum number of 0s between 1 and 1 is 1, the maximum number of 1s between 0 and 0 is infinity, and the repeated minimum transition run (RMTR) is 2.

Meanwhile, the data modulator according to the present invention determines whether an encoder and a run length constraint for generating a channel sequence for an input sequence are violated, and if the run length constraint is violated, a bit included in the channel sequence. And a bit flipper for performing a bit flip at a position before the violation of the middle run length constraint.

The bit flipper may determine the bit flip position so that there is no error propagation in decoding.

The bit flipper may determine the bit flip position based on the location of the violation of the run length constraint and the length of the codeword.

The bit flipper may determine the bit flip position based on the remainder of the violation position divided by the length of the codeword.

The run length constraint is a condition for the maximum number of zeros existing between 1 and 1 in the channel sequence, and the bit flipper may convert the 0 bits of a specific position into 1 bit.

The encoder can set run length constraints based on a statistical check of the number of bit flips.

The encoder may generate a channel sequence for the input sequence using the modulation table.

The modulation table may include at least one state, code words corresponding to the input code, and information designating the next state.

The modulation table may generate a channel sequence in which the minimum number of 0s between 1 and 1 is 1, the maximum number of 1s between 0 and 0 is infinity, and the repeated minimum transition run (RMTR) is 2.

Meanwhile, the data recording method according to the present invention includes generating a channel sequence for an input sequence, determining whether a run length constraint is violated, and when a run length constraint is violated, a run among bits included in the channel sequence. And performing a bit flip at a position before the violation of the length constraint condition to generate the modulated data and storing the modulated data on the recording medium.

On the other hand, the data recording apparatus according to the present invention includes a modulator for modulating data, and an optical unit for irradiating light onto the recording medium to record the modulated data generated by the modulator on the recording medium.

The present invention does not require an auxiliary table for adding a k-restriction condition, can facilitate the change of the k-restriction condition by bit flip, and has an effect that there is no error propagation by bit flip.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. In the present specification, the recording apparatus means any device capable of recording data or reproducing the recorded data using a recording medium. In the present specification, the recording medium means any medium in which data is recorded or can be recorded, and specifically, an optical disc may be used.

1 is a block diagram of a data recording apparatus according to an embodiment of the present invention. Hereinafter, a data recording apparatus according to an embodiment of the present invention will be described with reference to FIG. 1. As shown, the recording apparatus according to the embodiment of the present invention includes a modulator 100 and an optical unit 200.

The modulator 100 modulates input data to generate modulated data, and the optical unit 200 records the modulated data generated by the modulator 100 on the recording medium 300. In this case, the optical unit 200 may be configured as an optical pick up.

As shown in FIG. 1, the modulator 100 includes an encoder 10, a bit flipper 12, and a precoder 14.

2 shows an example of a modulation table that can be used in the encoder 10. In this case, the modulation table of FIG. 2 is a parity complementary code having a constraint of (1, ∞, 2). That is, in the channel sequence generated by the modulation table, at least one zero exists between 1 and 1, and infinite zero may exist. In addition, a replicated minimum transition run (RMTR) becomes two. The modulation table includes at least one register, each register containing a code word corresponding to the input code and information specifying the next register.

When the channel sequence generated by the encoder 10 violates the Run Length Limit (RLL) condition, the bit flipper 12 may violate the run length constraint among the bits included in the channel sequence. The run length constraint is added by performing a bit flip at a position before the generated position. This will be described later.

The precoder 14 converts the data generated by the encoder 10 and the bit flipper 12 into a non return to zero invert (NRZI) signal and transmits the data to the optical unit 200. The optical unit 200 records the modulated data on the recording medium by using the optical pickup.

Hereinafter, a data modulation method according to an embodiment of the present invention will be described in detail. First, a channel sequence corresponding to the input bits is generated using the modulation table illustrated in FIG. 2. As described above, the modulation table of FIG. 2 generates (1, ∞, 2) parity complementary codes.

FIG. 2 illustrates a modulation table in which a code rate of 2/3 is generated, that is, a code word of 3 bits is generated for an input code of 2 bits. In addition, FIG. 2 illustrates a modulation method in the case where the modulation table includes five registers, each divided into five states. However, the present invention is not limited thereto, and the present invention can be applied to using a modulation table of another type.

Referring to FIG. 2, a code word corresponding to an initial input code is output from an initially set state, and a code word for a next input code is sequentially generated by moving to a next state specified in a modulation table.

For example, suppose that the modulation code starts encoding at S1, and when the input sequence of the modulation code encoder is [10 10 10], the channel code for the initial input code [10] according to FIG. 2 is [000]. And the next state is S1. Therefore, the channel code for the next input code [10] also becomes [000]. The channel sequence generated according to this process becomes [000, 000, 000].

Meanwhile, in the channel sequence generated as described above, in order to smoothly restore the timing of the system, it is necessary to add a k-restriction condition to the channel sequence, that is, a maximum number of 0 conditions existing between 1 and 1.

In this embodiment, the k-restriction condition is added using the bit flip method. At this time, it is necessary to select the bit flip position so as not to violate other constraints of the designed modulation code in the process of adding the k-constraint condition.

Bit flip is a method of adding an error to a channel sequence generated before data is written to a recording medium. Therefore, the sequence recorded on the recording medium contains an error. At this time, according to the modulation method according to the embodiment of the present invention, the number of errors generated is equal to the number of flipped bits.

Correction of the error formed by the bit flip is performed by the error correction algorithm of the decoding unit, and the increase in the number of bit flips results in an increase in the additional information of the error correction algorithm, thereby degrading efficiency in decoding. Therefore, it is necessary to limit the number of bit flips to an appropriate number.

In this case, since the number of bit flips increases as the k value is smaller, the k-binding condition may be determined in consideration of this, and the k-binding condition may be set based on a statistical check of the number of bit flips. Also, the determination of the value of k is preferably determined so that the number of bit flips, i.e., the number of errors applied, is within the correction capability of the error correction code. In addition, the k value may be determined depending on the presence or absence of a bit flip position that does not cause error propagation during decoding.

For example, the k value may be set to 7 to 10 for the channel sequence. Hereinafter, the bit flip method will be described with reference to FIGS. 3A to 5C, for example, when k values are 10, 9, and 7.

First, a bit flip method when the k value is 10 will be described with reference to FIGS. 3A to 3C. The channel sequence generated in the modulation table may violate k-constraining condition 10 depending on the relationship between the sequence preceding it and the sequence following it. By performing a bit flip on this channel sequence, the k- constraint condition 10 is added to the generated channel sequence.

3A to 3C illustrate examples of performing a bit flip when K is 10. Referring to FIG. If k is determined as described above, the bit flip position is determined. In this case, the bit flip position for adding k-restraining to the channel sequence may be selected such that there is no error propagation in decoding.

In order not to cause error propagation in decoding, the position of the bit flip may be determined based on the k-constraint violation position and the length of the codeword. More specifically, the location of violation may be determined by dividing the codeword by the remaining values.

For example, if the remaining position divided by the codeword is 0, the bit flip position is 4 bits ahead of the violation position; if the remaining value is 1, the bit flip position is 2 bits ahead of the violation position, If the value is 2, the bit flip position is 3 bits ahead of the violation position.

In FIG. 3A, the violation position of the k-constraining condition 10 is 14. In addition, the codeword length of the modulation table is three. In this case, the remainder obtained by dividing the violation position by the codeword is 2, so the bit flip position is 11, which is 3 bits before the violation position 14. By such a bit flip, the channel sequence becomes a sequence to which the k constraint condition 10 is added. In this case, d and r constraints, that is, the minimum number of conditions 0 and the RMTR condition existing between 1 and 1, satisfy d = 1 and r = 2 without causing error propagation during decoding.

In the case of FIG. 3B, the violation position of the k-constraining condition 10 is 13. Therefore, since the violation position divided by the codeword is 1, the bit flip position is 11, which is two bits before the violation position 13. By such a bit flip, the channel sequence becomes a sequence to which the k constraint condition 10 is added. In this case, bit flipping does not cause error propagation during decoding and satisfies d, r constraints d = 1 and r = 2.

In the case of FIG. 3C, the violation position of the k-constraining condition 10 is 12. Therefore, since the violation position divided by the codeword is 0, the bit flip position is 8 four bits before the violation position 12. By such a bit flip, the channel sequence becomes a sequence to which the k constraint condition 10 is added. In this case, bit flipping does not cause error propagation during decoding and satisfies d, r constraints d = 1 and r = 2.

Hereinafter, the bit flip method when the k value is 9 will be described. The channel sequence generated by the modulation table is violated in k-constraining condition 9 according to the relationship between the sequence located before and the sequence following. Bit flipper 12 adds a k− constraint 9 to the generated channel sequence by performing a bit flip on this channel sequence.

4A to 4C show an example of performing a bit flip when K is 9. A method of performing a bit flip will be described in detail with reference to FIGS. 4A to 4C. As noted above, the bit flip position for adding k-restraints to the channel sequence is chosen such that there is no error propagation in decoding.

First, to add a constraint of k = 9 to the channel sequence, a specific bit flip position is selected that does not cause error propagation in decoding. In order not to cause error propagation in decoding, the position of the bit flip may be determined based on the k-constraint violation position and the length of the codeword.

In FIG. 4A, the violation position of the k-constraining condition 9 is 13. In addition, the codeword length of the modulation table is three. At this time, the violation position is determined by dividing the code word by the remaining values.

For example, if the remaining position divided by the codeword is 0, the bit flip position is 4 bits ahead of the violation position; if the remaining value is 1, the bit flip position is 2 bits ahead of the violation position, If the value is 2, the bit flip position is 3 bits ahead of the violation position.

In the case of FIG. 4A, since the remainder is 1, the bit flip position is 11, which is 2 bits before the violation position 13. By such a bit flip, the channel sequence becomes a sequence to which k constraint condition 9 is added. In this case, d, r constraints d = 1 and r = 2 are satisfied without causing error propagation during decoding.

In the case of FIG. 4B, the violation position of the k-constraining condition 9 becomes 12. Therefore, the remainder is zero, so the bit flip position is 8, four bits before the violation position 12. By such bit flipping, the channel sequence becomes a sequence to which k constraint condition 9 is added. In this case, bit flipping does not cause error propagation during decoding and satisfies d, r constraints d = 1 and r = 2.

In the case of FIG. 4C, the violation position of the k-constraining condition 9 is 11. Therefore, the remainder is 2, so the bit flip position is 8, which is 3 bits before the violation position 11. By such bit flipping, the channel sequence becomes a sequence to which k constraint condition 9 is added. In this case, bit flipping does not cause error propagation during decoding and satisfies d, r constraints d = 1 and r = 2.

Hereinafter, the bit flip method when the k value is 7 will be described. The channel sequence generated by the modulation table described above violates k-constraining condition 7, depending on the relationship between the sequence preceding it and the sequence following it. Bit flipper 12 adds a k- constraint condition 7 to the generated channel sequence by performing a bit flip on this channel sequence.

5A to 5C show an example of performing a bit flip when K is 7. A method of performing a bit flip will be described in detail with reference to FIGS. 5A to 5C. As noted above, the bit flip position for adding k-restraints to the channel sequence is chosen such that there is no error propagation in decoding.

First, to add a constraint of k = 7 to the channel sequence, a specific bit flip position is selected that does not cause error propagation in decoding. In order not to cause error propagation in decoding, the position of the bit flip may be determined based on the k-constraint violation position and the length of the codeword.

In FIG. 5A, the violation position of the k-constraining condition 7 is 11. In addition, the codeword length of the modulation table is three. At this time, the violation position is determined by dividing the code word by the remaining values.

For example, if the remaining value divided by the codeword is 0, the bit flip position is 1 bit ahead of the violation position; if the remaining value is 1, the bit flip position is 2 bits ahead of the violation position, If the value is 2, the bit flip position is 3 bits ahead of the violation position.

In the case of FIG. 5A, since the remainder is 2, the bit flip position is 8, which is 3 bits before the violation position 11. By such a bit flip, the channel sequence becomes a sequence to which the k constraint condition 7 is added. In this case, d, r constraints d = 1 and r = 2 are satisfied without causing error propagation during decoding.

In the case of FIG. 5B, the violation position of the k-constraining condition 7 is 10. FIG. Thus, the remainder is 1, so the bit flip position is 8, two bits before the violation position 10. By such a bit flip, the channel sequence becomes a sequence to which the k constraint condition 7 is added. In this case, bit flipping does not cause error propagation during decoding and satisfies d, r constraints d = 1 and r = 2.

In the case of FIG. 5C, the violation position of the k-constraining condition 7 is 9. Thus, the remainder is zero, so the bit flip position is 8, one bit before the violation position of nine. By such a bit flip, the channel sequence becomes a sequence to which the k constraint condition 7 is added. In this case, bit flipping does not cause error propagation during decoding and satisfies d, r constraints d = 1 and r = 2.

In the above examples, even if a bit flip is performed to convert the channel sequence, it can be seen that the number of errors after decoding is equal to the number of bit flips. Codes generated by the modulation table have many channel sequences that violate k-constraints, but can be converted to channel sequences that satisfy k-constraints, d-constraints, and RMTRs by the method described above. . In addition, the modulation method according to the embodiment of the present invention does not require a separate auxiliary table for adding k-constraints. Therefore, the modulation method according to the present embodiment may have better DC suppression performance.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications and changes can be made within the scope of the claims and the detailed description of the invention and the accompanying drawings, and the present invention is also provided. Naturally, it belongs to the range of.

1 is a block diagram of a data recording apparatus according to an embodiment of the present invention.

2 shows an example of a modulation table for generating a channel sequence in a data modulation method according to an embodiment of the present invention.

3A to 3C are schematic diagrams illustrating a method of performing a bit flip when K is 10.

4A through 4C are schematic diagrams illustrating a method of performing a bit flip in an embodiment of the present invention when K is 9.

5A through 5C are schematic diagrams illustrating a method of performing a bit flip in an embodiment of the present invention when K is 7.

Claims (20)

Generating a channel sequence for the input sequence; Determining whether a run length limit (RLL) condition is violated; And If the run length constraint is violated, performing a bit flip at a position before the violation of the run length constraint occurs among bits included in the channel sequence; Data modulation method comprising a. According to claim 1, The performing of the bit flipping includes determining the bit flip position such that there is no error propagation in decoding. The method of claim 2, And determining the bit flip position based on the violation position of the run length constraint and the length of a codeword. The method of claim 3, wherein And determining the bit flip position based on a remainder obtained by dividing the violation position by the length of the codeword. The method of claim 2, The run length limitation condition is a condition for a maximum number of zeros existing between 1 and 1 in the channel sequence, and the bit flip is performed by converting 0 bits at a specific position into 1 bit. According to claim 1, And setting the run length constraint condition based on a statistical check of the number of bit flips. According to claim 1, Generating a channel sequence for the input sequence using a modulation table in the step of generating a channel sequence for the input sequence. The method of claim 7, wherein And wherein said modulation table comprises information specifying at least one state, a code word corresponding to an input code, and a next state. The method of claim 8, The modulation table is a data modulation method for generating a channel sequence of the minimum number of 0 between 1 and 1 is 1, the maximum number of 1 between 0 and 0 is infinite, the repeated minimum transition run (RMTR) 2. An encoder for generating a channel sequence for the input sequence; And It is determined whether a run length constraint is violated, and when the run length constraint is violated, a bit flip is performed at a position before the violation of the run length constraint among bits included in the channel sequence. Bit flipper Data modulation device comprising a. The method of claim 10, And the bit flipper determines the bit flip position so that there is no error propagation in decoding. The method of claim 11, wherein And the bit flipper determines the bit flip position based on the location of the violation of the run length constraint and the length of the codeword. The method of claim 12, And the bit flipper determines a bit flip position based on a remainder obtained by dividing the violation position by the length of the codeword. The method of claim 10, The run length limitation condition is a condition for a maximum number of zeros existing between 1 and 1 in the channel sequence, and the bit flipper converts 0 bits at a specific position into 1 bit. The method of claim 10, And the encoder sets a run length limitation condition based on a statistical check of the number of bit flips. The method of claim 10, And the encoder generates a channel sequence for the input sequence using the modulation table. The method of claim 16, And the modulation table includes information specifying at least one state, a code word corresponding to an input code, and a next state. The method of claim 17, And the modulation table generates a channel sequence having a minimum number of 0s between 1 and 1, a maximum number of 1s between 0 and 0, and an infinite minimum transition run (RMTR) of 2. Generating a channel sequence for the input sequence; Determining whether a run length constraint is violated; Generating a modulated data by performing a bit flip at a position before a violation of the run length constraint occurs among bits included in the channel sequence when the run length constraint is violated; And Storing the modulated data on a recording medium Data recording method comprising a. A modulator for modulating data; And An optical unit for irradiating light onto the recording medium and recording the modulated data generated by the modulation unit on the recording medium Including, The modulator, An encoder for generating a channel sequence for the input sequence; And It is determined whether a run length constraint is violated, and when the run length constraint is violated, a bit flip is performed at a position before the violation of the run length constraint among bits included in the channel sequence. Bit flipper Data recording device comprising a.

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