KR101430448B1 - Data modulation method, modulator, recording method, and recording apparatus - Google Patents

Abstract

A data modulation method according to the present invention includes the steps of generating a channel sequence for an input sequence, determining whether a run length limit (RLL) condition is violated, and, if the run length restriction condition is violated, And performing a bit flip at a position before the position where the violation of the run length restriction condition occurs among the included bits.

Modulation, encoding, decoding, run length limitation, channel sequence, bit flip

Description

TECHNICAL FIELD [0001] The present invention relates to a data modulation method, a modulation device, a recording method,

The present invention relates to a data modulation method, a modulation apparatus, a recording method, and a recording apparatus, and more particularly, to a method and apparatus for modulating data recorded on an optical recording medium and a recording method and apparatus using the same.

A typical recording system uses a modulation code that is used to reduce distortion of the reproduction signal caused by interference between adjacent symbols in the playback portion of the recording system and to provide smooth timing recovery.

The modulation code at this time can be expressed as (d, k), which is referred to as a run length limit (RLL) code. Here, d is a constraint condition which means a minimum number of 0s that can exist between 1 and 1 of the modulation code, and is a condition for reducing the distortion of the signal caused by the adjacent symbol interferences. Also, k is a constraint meaning a maximum number of 0s that can exist between 1 and 1, and is a condition for timing recovery.

After observing the channel sequence which is the output of the modulation code encoder in the method of adding the k-constraint when designing the modulation code, when the sequence violating the k-constraint is observed, the data 0 is changed to 1 at that position there is a bit flip method in which a k-constraint is added.

That is, the bit flip method adds a k-constraint by imposing an error on the channel sequence. This method is a method in which an error is applied to a channel sequence which is a sequence before being recorded on a recording medium, so that a sequence recorded on a recording medium contains an error.

Therefore, when the bit flip is frequently generated in the bit flip method, it is difficult to recover the original data at the time of demodulation, and there is a limit to the improvement of the recording density even if the bit flip is recoverable. In particular, the modulation codes for the recording system become more serious because, by design characteristic, one bit error in decoding has an error transmission characteristic causing several bits of error.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and it is an object of the present invention to provide a demodulation method, a demodulation device, a recording method, and a recording device that can easily restore original data and improve recording density have.

In order to achieve the above object, a data modulation method according to the present invention includes generating a channel sequence for an input sequence, determining whether a run length limit (RLL) condition is violated, And performing a bit flip at a position ahead of a position where a violation of the run length restriction condition occurs among the bits included in the channel sequence.

Implementing the bit flip may comprise determining a bit flip position such that there is no error propagation in decoding.

In determining the bit flip position, the bit flip position can be determined based on the violation position of the run length restriction condition and the length of the code word.

In determining the bit flip position, the bit flip position may be determined based on the remainder obtained by dividing the violation position by the length of the code word.

The run length restriction condition is a condition for the maximum number of 0s existing between 1 and 1 in the channel sequence, and the bit flip can be formed by converting 0 bit of a specific position into 1 bit.

And setting a run length limiting condition based on statistical checking of the number of bit flip times.

In the step of generating the channel sequence for the input sequence, the modulation table may be used to generate the channel sequence for the input sequence.

The modulation table may include at least one state, a code word corresponding to the input code, and information specifying the next state.

The modulation table is capable of generating a channel sequence with a minimum number of zeros between 1 and 1 being 1, a maximum number of 1s between 0 and 0 being infinite, and a RMTR (repeated minimum transition run) of 2.

Meanwhile, the data modulation apparatus according to the present invention determines whether or not a run length restriction condition is violated by an encoder that generates a channel sequence for an input sequence, and when the run length restriction condition is violated, a bit included in the channel sequence And a bit flipper that performs a bit flip at a position ahead of the position where the violation of the middle run-length restriction condition occurs.

The bit flipper can determine the bit flip position so that there is no error transmission in decoding.

The bit flipper can determine the bit flip position based on the position where the violation of the run length restriction condition occurs and the length of the code word.

The bit flipper can determine the bit flip position based on the remainder of dividing the violation position by the length of the codeword.

The run-length constraint is a condition for the maximum number of 0s between 1 and 1 in the channel sequence, and the bit flipper can convert 0 bits of a specific position into 1 bit.

The encoder can set run length constraints based on statistical checking of the number of bit flips.

The encoder may use the modulation table to generate a channel sequence for the input sequence.

The modulation table may include at least one state, a code word corresponding to the input code, and information specifying the next state.

The modulation table is capable of generating a channel sequence with a minimum number of zeros between 1 and 1 being 1, a maximum number of 1s between 0 and 0 being infinite, and a RMTR (repeated minimum transition run) of 2.

Meanwhile, a data recording method according to the present invention includes a step of generating a channel sequence for an input sequence, a step of determining whether a run length restriction condition is violated, a step of, if a run length restriction condition is violated, Performing bit flipping at a position before a position at which a violation of the length restriction condition occurs to generate modulation data, and storing the modulation data on a recording medium.

On the other hand, the data recording apparatus according to the present invention includes a modulator for modulating data, and an optical unit for irradiating the data onto the recording medium and recording the modulated data generated by the modulator on the recording medium.

The present invention does not require an auxiliary table for adding the k-constraint condition, and can easily change the k-constraint by the bit flip, and has the effect that there is no error transmission by the bit flip.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. In this specification, a recording device refers to any device capable of recording data or reproducing recorded data using a recording medium. The term " recording medium " as used herein means any medium on which data is recorded or can be recorded. Specifically, an optical disk is exemplified.

1 is a block diagram of a data recording apparatus according to an embodiment of the present invention. Hereinafter, a data recording apparatus according to an embodiment of the present invention will be described with reference to FIG. As shown, the recording apparatus according to the embodiment of the present invention includes a modulation unit 100 and an optical unit 200.

The modulation unit 100 modulates the input data to generate modulation data, and the optical unit 200 records the modulation data generated by the modulation unit 100 on the recording medium 300. At this time, the optical unit 200 may be configured as an optical pick-up.

1, the modulation unit 100 includes an encoder 10, a bit flipper 12, and a precoder 14. [

On the other hand, Fig. 2 shows an example of a modulation table usable in the encoder 10. At this time, the modulation table of FIG. 2 is a parity complementary code having a constraint condition of (1,?, 2). That is, the channel sequence generated by the modulation table has at least one 0 between 1 and 1, and there may be 0 of infinity. Also, RMTR (repeated minimum transition run) is 2. The modulation table includes at least one register, and each register includes a code word corresponding to the input code and information specifying the next register.

A bit flipper 12 is a circuit for detecting a violation of a run length restriction condition among bits included in a channel sequence when a channel sequence generated by the encoder 10 is in violation of a run length limit (RLL) condition A bit flip is performed at a position before the generated position to add a run length restriction condition. This will be described later.

The precoder 14 converts the data generated by the encoder 10 and the bit flipper 12 into a NRZI (Non Return to Zero Invert) signal and transmits the signal to the optical unit 200. The optical section 200 records the modulated data on the recording medium using the optical pickup.

Hereinafter, a data modulation method according to an embodiment of the present invention will be described in detail. First, a channel sequence corresponding to input bits is generated using the modulation table illustrated in FIG. As described above, the modulation table of FIG. 2 generates a (1,?, 2) parity complementary code.

FIG. 2 illustrates a modulation table for generating a 3-bit codeword for a code rate of 2/3, that is, for a 2-bit input code. In addition, FIG. 2 illustrates a modulation method in the case where the modulation table includes five registers, each of which is divided into five states. However, the present invention is not limited thereto, and the present invention is also applicable to the use of other types of modulation tables.

Referring to FIG. 2, a code word corresponding to an initial input code is output in an initialized state, and a code word for a next input code is sequentially generated by moving to a next state designated in a modulation table.

For example, if it is assumed that the modulation code starts encoding in S1, and the input sequence of the modulation code encoder is [10 10 10], the channel code for the initial input code [10] And the next state becomes S1. Therefore, the channel code for the next input code [10] is also [000]. The channel sequence generated according to this procedure is [000, 000, 000].

In order to recover the timing of the system smoothly in the channel sequence thus generated, it is necessary to add a k-constraint condition, that is, a maximum number of 0's existing between 1 and 1, to the channel sequence.

In this embodiment, the k-constraint is added using the bit flip method. At this time, it is necessary to select the bit flip position so as not to violate the other constraint condition of the designed modulation code in the process of adding the k-constraint.

A bit flip is a method of adding an error to a channel sequence generated before data is recorded on a recording medium. Therefore, the sequence recorded on the recording medium will contain an error. At this time, according to the modulation method of the embodiment of the present invention, the number of generated errors is equal to the number of flipped bits.

The correction of the error formed by the bit flip is performed by an error correction algorithm of the decoding unit. The increase of the number of bit flips leads to an increase of the additional information of the error correction algorithm. It is therefore necessary to limit the number of bit flips to an appropriate number.

In this case, the smaller the value of k, the more the number of bit flip is increased. Therefore, the k-constraint can be determined in consideration of this, and the k-constraint can be set based on the statistical examination of the bit flip count. It is also preferable that the determination of the k value is determined so that the number of bit flips, that is, the number of errors applied, is within the correction capability of the error correcting code. Also, the value of k may be determined depending on the presence or absence of a bit flip position to prevent error propagation from occurring during decoding.

For example, the k value can be set to 7 to 10 for the above-described channel sequence. Hereinafter, the bit flip method will be described with reference to FIGS. 3A to 5C as an example where k values are 10, 9, and 7, respectively.

First, referring to FIGS. 3A to 3C, a bit flip method in the case of a k value of 10 will be described. The channel sequence generated in the modulation table may be violated to the k-constraint 10 according to the relationship between the sequence preceding it and the sequence following it. By applying a bit flip on this channel sequence, a k-constraint 10 is added to the generated channel sequence.

Figs. 3A to 3C show examples of bit flipping when K is 10. When the k value is determined as described above, the bit flip position is determined. At this time, the bit flip position for adding the k-constraint to the channel sequence can be selected so that there is no error transmission in decoding.

To avoid error propagation in decoding, the position of the bit flip can be determined based on the k-constraint violation position and the length of the codeword. More specifically, the violation position can be determined by the remaining value after dividing the violation position by the code word.

For example, if the remainder value obtained by dividing the violation position by the codeword is 0, the bit flip position is 4 bits before the violation position, and if the remaining value is 1, the bit flip position is 2 bits before the violation position, If the value is 2, the bit flip position is 3 bits ahead of the violation position.

The violation position of k-constraint 10 in Fig. In addition, the length of the code word by the modulation table is 3. At this time, since the remainder obtained by dividing the violation position by the code word is 2, the bit flip position is 11 which is three bits before the violation position 14. By this bit flip, the channel sequence becomes a sequence to which k constraint condition 10 is added. In this case, the d and r constraint conditions, ie, the minimum number of 0's and the RMTR conditions existing between 1 and 1 satisfy d = 1 and r = 2, respectively, without causing error transmission in decoding.

3B, the violation position of the k-constraint 10 is 13. Therefore, since the remainder obtained by dividing the violation position by the code word is 1, the bit flip position is 11, which is two bits before the violation position 13. By this bit flip, the channel sequence becomes a sequence to which k constraint condition 10 is added. In this case, the bit flip does not cause error transmission in decoding, and d and r constraints d = 1 and r = 2 are satisfied.

3C, the violation position of the k-constraint 10 is 12. Therefore, since the remainder obtained by dividing the violation position by the code word is 0, the bit flip position is 8, which is 4 bits before the violation position 12. By this bit flip, the channel sequence becomes a sequence to which k constraint condition 10 is added. In this case, the bit flip does not cause error transmission in decoding, and d and r constraints d = 1 and r = 2 are satisfied.

Hereinafter, the bit flip method when the k value is 9 will be described. The channel sequence generated by the modulation table violates k-constraint 9 according to the relationship between the sequence preceding and following the sequence. The bit flipper 12 adds a k-constraint 9 to the generated channel sequence by performing a bit flip on this channel sequence.

Figs. 4A to 4C show examples in which bit flipping is performed when K is 9. The method of performing the bit flip will be described in detail with reference to Figs. 4A to 4C. As described above, the bit flip position for adding k-constraint to the channel sequence is selected so that there is no error propagation in decoding.

First, in order to add a constraint of k = 9 to the channel sequence, a specific bit flip position which does not cause error transmission upon decoding is selected. To avoid error propagation in decoding, the position of the bit flip can be determined based on the k-constraint violation position and the length of the codeword.

In Fig. 4A, the violation position of k-constraint 9 is 13. In addition, the length of the code word by the modulation table is 3. At this time, the position of the violation is divided by the code word and is determined by the remaining value.

For example, if the remainder value obtained by dividing the violation position by the codeword is 0, the bit flip position is 4 bits before the violation position, and if the remaining value is 1, the bit flip position is 2 bits before the violation position, If the value is 2, the bit flip position is 3 bits ahead of the violation position.

4A, the bit flip position is 11, which is two bits ahead of the violation position 13, since the rest is 1. By this bit flip, the channel sequence becomes a sequence to which k constraint condition 9 is added. In this case, d and r constraints d = 1 and r = 2 are satisfied without causing error transmission during decoding.

In Fig. 4B, the violation position of k-constraint 9 is 12. Therefore, since the remainder becomes 0, the bit flip position becomes 8 which is four bits before the violation position 12. By this bit flip, the channel sequence becomes a sequence to which k constraint condition 9 is added. In this case, the bit flip does not cause error transmission in decoding, and d and r constraints d = 1 and r = 2 are satisfied.

In the case of FIG. 4C, the violation position of k-constraint 9 is 11. Therefore, since the remainder is 2, the bit flip position is 8, which is three bits before the violation position 11. By this bit flip, the channel sequence becomes a sequence to which k constraint condition 9 is added. In this case, the bit flip does not cause error transmission in decoding, and d and r constraints d = 1 and r = 2 are satisfied.

Hereinafter, the bit flip method when the k value is 7 will be described. The channel sequence generated by the above modulation table violates k-constraint 7 according to the relationship between the sequence preceding it and the sequence following it. The bit flipper 12 adds a k-constraint 7 to the generated channel sequence by performing a bit flip on this channel sequence.

Figs. 5A to 5C show an example of bit flipping when K is 7. The method of performing the bit flip will be described in detail with reference to FIGS. 5A to 5C. As described above, the bit flip position for adding k-constraint to the channel sequence is selected so that there is no error propagation in decoding.

First, to add a constraint of k = 7 to the channel sequence, a specific bit flip position that does not cause error propagation in decoding is selected. To avoid error propagation in decoding, the position of the bit flip can be determined based on the k-constraint violation position and the length of the codeword.

In Fig. 5A, the violation position of k-constraint 7 is 11. In addition, the length of the code word by the modulation table is 3. At this time, the position of the violation is divided by the code word and is determined by the remaining value.

For example, if the remainder value obtained by dividing the violation position by the code word is 0, the bit flip position is 1 bit before the violation position, and if the remaining value is 1, the bit flip position is 2 bits before the violation position, If the value is 2, the bit flip position is 3 bits ahead of the violation position.

5A, the bit flip position is 8, which is 3 bits before 11, which is the violation position. By this bit flip, the channel sequence becomes a sequence to which k constraint condition 7 is added. In this case, d and r constraints d = 1 and r = 2 are satisfied without causing error transmission during decoding.

In the case of Fig. 5B, the violation position of k-constraint 7 is 10. Therefore, since the remainder becomes 1, the bit flip position becomes 8 which is two bits before the violation position 10. By this bit flip, the channel sequence becomes a sequence to which k constraint condition 7 is added. In this case, the bit flip does not cause error transmission in decoding, and d and r constraints d = 1 and r = 2 are satisfied.

In the case of FIG. 5C, the violation position of k-constraint 7 is 9. Therefore, since the remainder becomes 0, the bit flip position becomes 8 which is one bit ahead of the violation position 9. By this bit flip, the channel sequence becomes a sequence to which k constraint condition 7 is added. In this case, the bit flip does not cause error transmission in decoding, and d and r constraints d = 1 and r = 2 are satisfied.

In the above examples, even if a bit flip is performed to convert a channel sequence, it can be confirmed that the number of errors after decoding is the same as the number of bit flips. Although the code generated by the modulation table includes many channel sequences that violate the k-constraint, it is possible to convert the channel sequence into the k-constraint, the d-constraint, and the channel sequence satisfying the RMTR . Further, according to the modulation method according to the embodiment of the present invention, a separate auxiliary table for adding the k-constraint condition is not required. Therefore, the modulation method according to the present embodiment can have better DC suppression performance.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Of course.

1 is a block diagram of a data recording apparatus according to an embodiment of the present invention.

2 shows an example of a modulation table for generating a channel sequence in the data modulation method according to the embodiment of the present invention.

3A to 3C are schematic diagrams illustrating a method of performing a bit flip when K is 10;

4A to 4C are schematic views illustrating a method of performing bit flipping in the embodiment of the present invention when K is 9;

5A to 5C are schematic diagrams illustrating a method of performing bit flipping in the embodiment of the present invention when K is 7;

Claims (20)

Generating a channel sequence for an input sequence; Determining whether a run length limit (RLL) condition is violated; And Performing a bit flip at a position ahead of a position where a violation of the run length restriction condition occurs among bits included in the channel sequence when the run length restriction condition is violated; Wherein the position of the bit flip is determined based on the violation position of the run length restriction condition and the length of the code word. delete delete The method according to claim 1, And determining the bit flip position based on a remainder obtained by dividing the violation position by the length of the code word. The method according to claim 1, Wherein the run length limiting condition is a condition for a maximum number of 0s existing between 1 and 1 in the channel sequence, and the bit flip is a 0 bit of a specific position is converted into 1 bit. The method according to claim 1, And setting the run length limitation condition based on a statistical check of the number of bit flip times. The method according to claim 1, Wherein generating a channel sequence for the input sequence uses a modulation table to generate a channel sequence for an input sequence. 8. The method of claim 7, Wherein the modulation table comprises at least one state, a code word corresponding to an input code, and information specifying a next state. 9. The method of claim 8, Wherein the modulation table generates a channel sequence having a minimum number of 0s between 1 and 1 is 1, a maximum number of 1s between 0 and 0 is infinite, and a RMTR (repeated minimum transition run) is 2. [ An encoder for generating a channel sequence for an input sequence; And Determines whether the run length restriction condition is violated or not, and when the run length restriction condition is violated, performs a bit flip at a position before the occurrence of the violation of the run length restriction condition among the bits included in the channel sequence Wherein the bit flipper determines a position to perform the bit flip based on a violation position of the run length restriction condition and a length of a code word. delete delete 11. The method of claim 10, Wherein the bit flipper determines a bit flip position based on a remainder obtained by dividing the violation position by the length of the code word. 11. The method of claim 10, The run length limiting condition is a condition for a maximum number of 0s existing between 1 and 1 in the channel sequence, and the bit flipper converts a 0 bit of a specific position into 1 bit. 11. The method of claim 10, Wherein the encoder sets a run length limiting condition based on statistical checking of the number of bit flip times. 11. The method of claim 10, Wherein the encoder uses a modulation table to generate a channel sequence for an input sequence. 17. The method of claim 16, Wherein the modulation table comprises at least one state, a code word corresponding to an input code, and information specifying a next state. 18. The method of claim 17, Wherein the modulation table generates a channel sequence having a minimum number of zeros between 1 and 1 equal to 1, a maximum number of 1s between 0 and 0 being infinite, and a repeated minimum transition run (RMTR) equal to two. Generating a channel sequence for an input sequence; Determining whether the run length restriction condition is violated; Performing bit flip at a position ahead of a position at which a run length restriction condition occurs, of the bits included in the channel sequence, when the run length restriction condition is violated, to generate modulation data; And And storing the modulation data on a recording medium, Wherein the step of generating the modulation data determines a position to perform the bit flip based on the violation position of the run length restriction condition and the length of the code word. A modulator for modulating data; And An optical unit for irradiating data onto a recording medium and recording the modulated data generated by the modulating unit onto the recording medium; Lt; / RTI > Wherein the modulator comprises: An encoder for generating a channel sequence for an input sequence; And Determines whether the run length restriction condition is violated or not, and when the run length restriction condition is violated, performs a bit flip at a position before the occurrence of the violation of the run length restriction condition among the bits included in the channel sequence Wherein the bit flipper determines a position to perform the bit flip based on a violation position of the run length restriction condition and a length of a code word.

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