KR20090025743A - Method for manufacturing circuit pattern-embedded printed circuit board of micro bump on pad structure - Google Patents

Abstract

A method for manufacturing a circuit pattern-embedded printed circuit board of a micro bump on a pad structure is provided to improve the micro short in the micro circuit pattern by embedding the circuit pattern inside the insulating layer. A conductive seed metal is formed on the surface of the first material. An outer layer circuit pattern including a solder ball land that is sub-layer is formed on one side of the first material(S1). A conductive micro bump is formed in the location of solder ball land(S2). The conductive micro bump passes through an insulating layer(S3). The conductive seed metal is formed in the second material. The outer layer circuit pattern including the wire bonding part which is the upper layer is formed in one side of the second material(S4). The first material and the second material are laminated(S5). The first material and the second material are separated(S6). The seed layer is removed using the micro-etching method(S7). The pad for connecting the outside is exposed by coating the solder resist to the upper layer and the sub-layer(S8). The nickel and gold plating layer is formed on the solder ball land region and a wire bonding region(S9).

Description

Method for manufacturing circuit pattern-embedded printed circuit board of Micro bump on pad structure}

The present invention relates to a printed circuit board manufacturing method in which a circuit pattern using a conductive micro bump is embedded in a surface of a substrate.

The conventional structure of a printed circuit board using a conductive bump is a structure in which an upper layer and a lower layer are conductive by using a bump instead of a through hole by a drill and copper plating.

That is, in the manufacturing process according to the related art, first, a plurality of conductive bumps are formed on the surface of the copper foil, which is the lower layer, and the bump ends are exposed to allow the bumps to penetrate the insulating layer of the prepreg so as to be easily connected to the upper layer. A new copper foil is placed on the top layer and thermally pressed to conduct it. Next, circuits are formed on the upper and lower layers, respectively, and solder resist is applied to protect the circuits. The external connection pads open the solder resist by exposure and then form nickel and gold plating layers on both sides simultaneously to facilitate the assembly process.

However, the conventional technology is that the solder borland and the circuit patterns formed on the outer layer are attached to the surface of the insulating layer, so that the surface is bent by the thickness of the circuit pattern, so that the chip is broken or deformed, especially in the thin chip mounting or the multilayer chip mounting package mounting. There is a disadvantage.

As shown in FIG. 1, a conductive paste is printed on the solder borland 3 to form a uniform conical bump 4 having a predetermined height in the upper layer U and the lower layer L, and insulation of the prepreg as a core layer is formed thereon. The copper foil is laminated on the pointed portion of the bump 4 through the layer 1 to form a B2it structure.

After this, the outer circuit patterns (2) and (5) are formed through a pattern image process, and the circuits are protected by the solder resist (8) on the upper layer (U) and the lower layer (L), and only the pads for external connection are exposed. Nickel and gold plating layers 7 and 9 are formed to process the outer shape.

The present invention provides a technique for manufacturing a printed circuit board having a structure in which the circuit pattern is embedded on the surface of the substrate by using a conductive micro bumps to solve the problems of the conventional method described above.

As a means for solving the above object (a) forming a conductive seed layer on the first substrate and forming an outer layer circuit pattern including a solder ball land as a lower layer by pattern plating on one side;

(b) forming a conductive micro bump in the solder ball land, which is the lower layer formed in step (a);

(c) stacking a prepreg insulating layer as a core layer on the first substrate and penetrating the micro bumps;

(d) forming an outer layer circuit pattern including a wire bonding part as an upper layer by pattern plating on one side after forming the conductive seed layer on a second substrate;

(e) after the steps (c) and (d), align and match the bonding positions of the micro bumps with the upper and lower layers, and stacking the prepreg insulating layer, which is the core layer, by thermal compression;

(f) separating the first substrate and the second substrate;

(g) etching and removing the conductive seed layer of the upper and lower layers by microetching;

(h) applying the upper layer and the lower layer with solder resist and exposing an external connection pad;

(i) forming a nickel / gold plating layer in the solder borland region and the wire bonding region, which are the pads for external connection exposed to the upper and lower layers.

In addition, only the upper layer is embedded in the insulating layer, and the first base layer further includes a form protruding on the surface of the insulating layer formed by a subtractive method, and the upper layer and the lower layer further include a multilayer formed in the inner layer. It is characterized by including.

In addition, in the step (f), when the nickel / gold plating layer is formed on the independent circuit pattern by an electric method in an independent circuit pattern, the entire surface of the outer layer is masked after the step (f), and the pad portion for external connection is performed. After exposing only the nickel-gold plating layer is formed and the masking is peeled off, further comprising the steps (g) and (h).

According to the present invention, it can be distinguished from the conventional method of manufacturing a circuit by a subtractive method, and circuit patterns are embedded in an insulating layer, and a specific position of an exposed circuit pattern is exposed on an insulating layer surface for external connection. It can be used as a pad to manufacture an ideal printed circuit board that can fundamentally solve micro short in improving surface flatness and realizing fine circuit pattern.

According to one aspect of the invention,

(a) forming an outer layer circuit pattern including a solder ball land as a lower layer by pattern plating on one side after forming the conductive seed layer on the first substrate;

(b) forming a conductive micro bump in the solder ball land, which is the lower layer formed in step (a);

(c) stacking a prepreg insulating layer as a core layer on the first substrate and penetrating the micro bumps;

(d) forming an outer layer circuit pattern including a wire bonding part as an upper layer by pattern plating on one side after forming the conductive seed layer on a second substrate;

(e) after the steps (c) and (d), match the bonding positions of the micro bumps to the upper layer and the lower layer and stack the prepreg insulating layer, which is the core layer, by thermal compression;

(f) separating the first substrate and the second substrate;

(g) etching and removing the conductive seed layer of the upper and lower layers by microetching;

(h) applying the upper layer and the lower layer with solder resist and exposing an external connection pad;

(i) forming a nickel / gold plating layer in the solder ball land region and the wire bonding region, which are the pads for external connection.

In addition, only the upper layer is embedded in the insulating layer, and the first base layer further includes a form protruding on the surface of the insulating layer formed by a subtractive method, and the upper layer and the lower layer further include a multilayer formed in the inner layer. It is characterized by including.

 In addition, in the step (f), when the nickel / gold plating layer is formed on the independent circuit pattern by an electric method in an independent circuit pattern, the entire surface of the outer layer is masked after the step (f), and the pad portion for external connection is performed. After exposing only the nickel-gold plating layer is formed and the masking is peeled off, further comprising the steps (g) and (h).

Hereinafter, with reference to the accompanying drawings to describe the present invention in detail.

2 is a cross-sectional view of a printed circuit board having a circuit pattern embedded in a micro bump on pad structure according to an embodiment of the present invention, and FIG. 3 is a flowchart of a manufacturing method according to the present invention.

Referring to FIG. 2, the outer circuit pattern 22 and the solder ball land 23 formed of the pattern plating constituting the prepreg insulating layer 21, the conductive micro bumps 24, and the lower layer B, which are core layers, Solder resist 28, nickel-gold plating (solder borland region) 29, outer circuit pattern 25 formed by pattern plating constituting upper layer T, wire bonding portion 26, solder resist ( 28, nickel-gold plating (wire bonding area) 27 is shown.

Referring to FIG. 3 with reference to FIG. 2,

After forming an ultrathin conductive seed layer such as chemical copper on the surface of the first substrate, the outer circuit pattern 22 including the solder ball land 23, which is the lower layer B, was patterned on one side (S1). By forming the conductive micro bumps 24 in the solder ball lands 23 of the same type (S2) and then through the insulating layer 21 of the prepreg as a core layer (S3).

On the other hand, the outer circuit pattern 25 including the wire bonding portion 26, which is the upper layer (T) by forming a conductive seed layer of ultrathin, such as chemical copper on the surface of the second substrate in the same manner and pattern-coated on one side (S4), the bonding position of the micro bumps 24 to the upper layer (T) and the lower layer (B) is matched and thermally compressed to laminate the insulating layer 21 composed of the prepreg as the core layer (S5). ).

That is, the first substrate and the second substrate are located at the outermost sides of the upper layer T and the lower layer B.

With the seed layer leaving the seed layer After separating only the second substrate (S6), the seed layer is removed by micro etching (S7), and an external connection pad for coating and mounting the upper layer (T) and the lower layer (B) with a solder resist (28). Exposed (S8) to form a nickel-gold plating (27), (29) (S9) layer in the solder ball land region and the wire bonding region which is the external connection pad.

The first substrate and the second substrate of the above (S1), (S2), (S3) and (S4) preferably use a release substrate having strong heat deformation, hygroscopicity and chemical resistance and are easily separated.

In addition, the (S5), (S6), and (S7) are embedded in the prepreg insulating layer 21 in which the outer circuit patterns 22 and 25 forming the upper layer T and the lower layer B are core layers. After the first substrate and the second substrate are separated from the prepreg insulating layer 21, which is a core layer, the seed layers of the upper layer T and the lower layer B are exposed to expose the circuit pattern surface including the seed layer. Micro-etching is completed to the outer circuit patterns 22 and 25 including the solder ball lands 23 and the wire bonding portion 26.

In addition, when an independent circuit pattern is formed to form a nickel, gold-plated (27), (29) layer on the independent circuit pattern by an electrical method, after the step (S6) masking the entire upper layer (T) and lower layer (B). And exposing the external connection pad and then performing the step S9 first instead of the step S7, and then peeling the masking to perform the step S7 and the step S8.

On the other hand, after the step (S9) is the same as the conventional process by the external processing.

As described above, preferred embodiments of the present invention have been described, but the present invention is not limited to the above-described embodiments, and the present invention is not limited to the scope of the present invention as claimed in the following claims. Anyone with knowledge of the present invention will have the methodology of the present invention to the extent that various modifications can be made.

1 is a cross-sectional view showing a printed circuit board using a conductive bump according to the prior art.

Figure 2 is a cross-sectional view showing a printed circuit board with a circuit pattern of a conductive micro bump structure in accordance with an embodiment of the present invention.

3 is a flow chart showing a manufacturing process according to an embodiment of the present invention.

** Main Names of Drawings **

1: insulation layer 2, 5: outer circuit pattern 3: solder borland

4: bump 6: wire bonding part 7, 9: nickel and gold plating

21: insulating layer 22: outer layer circuit pattern of the lower layer 23: solder borland

24: micro bump 25: the outer layer circuit pattern of the upper layer 26: wire bonding portion

27: nickel-gold plating layer (wire bonding region) 28: solder resist

29: nickel-gold plated layer (solder borland region)

Claims (4)

(a) forming an outer layer circuit pattern including a solder ball land as a lower layer by pattern plating on one side after forming the conductive seed layer on the first substrate; (b) forming a conductive micro bump in the solder ball land, which is the lower layer formed in step (a); (c) stacking a prepreg insulating layer as a core layer on the first substrate and penetrating the micro bumps; (d) forming an outer layer circuit pattern including a wire bonding part as an upper layer by pattern plating on one side after forming the conductive seed layer on a second substrate; (e) after the steps (c) and (d), match the bonding positions of the micro bumps to the upper layer and the lower layer and stack the prepreg insulating layer, which is the core layer, by thermal compression; (f) separating the first substrate and the second substrate; (g) etching and removing the conductive seed layer of the upper and lower layers by microetching; (h) applying the upper layer and the lower layer with solder resist and exposing an external connection pad; (i) forming a nickel / gold plating layer in the solder ball land region and the wire bonding region, which are the pads for external connection; and a micro-bump on pad, wherein a circuit pattern is embedded in the insulating layer on the upper and lower layers. Method of manufacturing a printed circuit board having a built-in circuit pattern. The method of claim 1, Only the upper layer is embedded in the insulating layer, and the first base layer is formed by a subtractive method and further includes a form protruding on the surface of the insulating layer. Substrate manufacturing method. The method of claim 1, The upper layer and the lower layer is a circuit pattern embedded printed circuit board manufacturing method of the micro-bump on pad structure, characterized in that it further comprises a multi-layer formed on the inner layer. The method of claim 1, In step (f), when the nickel / gold plating layer is formed on the independent circuit pattern by an electric method because of an independent circuit pattern, the entire surface of the outer layer is masked after step (f), and only the pad for external connection is exposed. And forming the nickel and gold plating layers, and then peeling masking to further include the steps (g) and (h).

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