KR20090024530A - Thin film transistor array substrate for liquid crystal display device and method of manufacturing the same - Google Patents

Abstract

A thin film transistor array substrate for a liquid crystal display device and a method of manufacturing the same are provided to reduce a light shielding area defined by a light shielding pattern which prevents light leakage. A gate line(102a) and a data line(108d) are intersected on a substrate. The gate line and the data line define a pixel region. A TFT is formed in the intersection of the data line and the gate line. A pixel electrode(111) is connected to the TFT. A light shielding pattern(102b) is overlapped with the edge of the pixel electrode. A drain electrode pattern is adjacent to a source electrode pattern. The drain electrode pattern is overlapped with the gate line. The drain electrode pattern adjacent to the source electrode pattern is laminated by a drain electrode(108c) and a semiconductor layer.

Description

Thin Film Transistor Array Substrate for Liquid Crystal Display Device and method of manufacturing the same

The present invention relates to a liquid crystal display device and a method for manufacturing the same, and more particularly, to a thin film transistor array substrate for a liquid crystal display device and a method for manufacturing the same.

In general, a liquid crystal display device displays an image by adjusting a light transmittance of a liquid crystal having dielectric anisotropy using an electric field.

Such a liquid crystal display device includes a color filter array substrate on which a black matrix to prevent light leakage and color filter layers of R, G, and B are formed to realize color, and a gate wiring and a data wiring defining unit pixels. A thin film transistor formed at an intersection point and a thin film transistor array substrate having pixel electrodes formed thereon.

This thin film transistor array substrate for liquid crystal display devices will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a thin film transistor array substrate for a liquid crystal display according to the related art.

First, as shown in FIG. 1, a thin film transistor substrate of a liquid crystal display device includes a gate wiring 112a and a data wiring 118a that vertically cross each other with a gate insulating film interposed therebetween to define a pixel region. At the intersection point, the thin film transistor TFT stacked with the gate electrode 112c, the gate insulating film (not shown), the semiconductor layer (not shown), and the source / drain electrodes 118b and 118c passes through the protective film (not shown). The light blocking pattern 112b is formed to overlap the edge of the pixel electrode 120 connected to the drain electrode 118c and formed in the entire pixel area.

In this case, the light shielding pattern 112b is formed of an opaque metal film such as the gate wiring 112a, is formed on the same layer as the gate wiring 112a, and the boundary portion is formed to overlap the edge of the pixel electrode 120. Together with the black matrix (not shown) of the color filter array substrate, light incident from the backlight, which is a light source of the liquid crystal display, is blocked to prevent light leakage.

However, although the shading pattern 112b has an effect of preventing light leakage, the shading area is increased by the area where the shading pattern is formed, and thus the opening area is reduced.

In order to solve the above problems, the present invention is to provide a thin film transistor array substrate for a liquid crystal display device and a method of manufacturing the same to reduce the light blocking area defined by the light shielding pattern to prevent light leakage to increase the aperture ratio.

A thin film transistor array substrate for a liquid crystal display device according to an embodiment of the present invention for achieving the above object is formed on the substrate to cross the gate wiring and data wiring to define a pixel region, the gate wiring and data wiring A thin film transistor formed at an intersection and formed of a gate electrode, a source electrode pattern, and a drain electrode pattern, a pixel electrode connected to the thin film transistor, and a light shielding pattern formed to overlap an edge of the pixel electrode; The drain electrode pattern may be formed to be adjacent to the source electrode pattern and overlap the gate wiring.

The drain electrode pattern formed to be adjacent to the source electrode pattern is stacked with the drain electrode and the semiconductor layer, and the drain electrode pattern formed to overlap the gate wiring is formed with the semiconductor layer.

The light shielding pattern is formed of an opaque metal film.

A method of manufacturing a thin film transistor array substrate for a liquid crystal display device includes forming a gate wiring, a gate electrode, and a light shielding pattern on a substrate, and a first insulating layer, a second conductive layer, and a third conductive layer on the substrate on which the light shielding pattern is formed. And forming a source electrode pattern and a drain electrode pattern by patterning the second conductive layer and the third conductive layer, wherein the drain electrode pattern is formed to be adjacent to the source electrode pattern. Forming a second insulating film having a contact hole with the drain electrode pattern exposed on the substrate on which the source electrode pattern and the drain electrode pattern are formed; and overlapping the contact hole on the second insulating film. And forming the pixel electrode via.

The drain electrode pattern formed to be adjacent to the source electrode pattern is stacked with the third conductive layer and the second conductive layer, and the drain electrode pattern formed to overlap the gate wiring is formed with the second conductive layer.

Patterning the second conductive layer and the third conductive layer to form a source electrode pattern and a drain electrode pattern, wherein the drain electrode pattern is formed to be adjacent to the source electrode pattern, and is formed to overlap the gate wiring. Forming a photoresist pattern by forming a photoresist on the third conductive layer, performing a photolithography process using a diffraction exposure mask, and forming the photoresist pattern using the photoresist pattern as a mask. And etching the third conductive layer.

The diffraction exposure mask includes a diffraction exposure portion disposed in a region where a drain electrode pattern overlapping the gate line is to be formed.

The thin film transistor array substrate for a liquid crystal display device and the method of manufacturing the same according to the present invention have an effect of increasing the opening area by moving the light shielding pattern toward the gate wiring by forming a drain electrode pattern overlapping the gate wiring.

In addition, according to the present invention, a thin film transistor array substrate for a liquid crystal display and a method of manufacturing the same may be formed by forming a drain electrode pattern overlapping the gate wiring only with a semiconductor layer, thereby reducing parasitic capacitance of the drain electrode pattern overlapping the gate wiring. It works.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

2 is a plan view illustrating a thin film transistor array substrate for a liquid crystal display device according to the present invention, and FIGS. 3A to 3E are cross-sectional views taken along line III-III 'and line IV-IV' of FIG. 2.

As shown in FIG. 2 and FIG. 3E, the thin film transistor array substrate for liquid crystal display according to the present invention crosses each other with a gate insulating film 104 interposed therebetween on the lower substrate 100 to define a pixel region. The thin film transistor formed of the gate electrode 102c, the gate insulating film 104, the semiconductor layer 106b, and the source electrode / drain electrodes 108b and 108c at each of the gate wiring 102a and the data wiring 108d and the intersection thereof. And a pixel electrode 111 connected to the drain electrode 108c and formed over the pixel region, and a light shielding pattern 102b so as to overlap the edge of the pixel electrode 111.

The light shielding pattern 102b is formed of an opaque metal film such as the gate wiring 102a, is formed on the same layer as the gate wiring 102a, and is positioned so that the edge portion overlaps with the edge of the pixel electrode 111. The light incident from the backlight, which is a light source of the liquid crystal display, together with the black matrix of the color filter array substrate, which is not the opposite substrate, is blocked to prevent light leakage.

Meanwhile, the source electrode 108b is branched from the data line 108d, and is defined as a source electrode pattern together with the semiconductor layer 106b formed under the source electrode 108b, and the drain electrode 108c is the source electrode 108b. ) And a semiconductor layer 106b formed under the drain electrode 108c and defined as the drain electrode pattern 130. In this case, the drain electrode pattern 130 may be formed by stacking the drain electrode 108c and the semiconductor layer 106b or using only the semiconductor layer 106b. In other words, in the drain electrode pattern 130 of the drain electrode pattern 130, the drain electrode 108c and the semiconductor layer 106b are stacked, and the drain electrode pattern 130 overlapping the gate wiring 102a is formed. 130 is formed only the semiconductor layer 106b.

At this time, the drain electrode pattern 130 overlapping the gate wiring 102a is moved to a position closer to the gate wiring 102a than the conventional drain electrode pattern 118c as shown in FIG. 4. That is, while the conventional drain electrode pattern 118c is disposed at a predetermined interval from the gate wiring 102a, the drain electrode pattern 130 of the present invention overlaps with the gate wiring 102a. The drain electrode pattern 130 is disposed at a position closer to the gate wiring 102a than the conventional drain electrode pattern 118c. Therefore, the light shielding pattern 102b of the present invention moves more in the direction in which the gate wiring 102a is formed than the conventional light shielding pattern 112b due to the movement of the drain electrode pattern 130. The opening area defined by the light shielding pattern 102b of the present invention is increased more than the opening area defined by 112b).

In addition, the drain electrode pattern 130 overlapped with the gate wiring 102a is formed only of the semiconductor layer 106b, so as to reduce the parasitic capacitance of the drain electrode pattern 130 overlapping with the gate wiring 102a. As a result, the parasitic of the drain electrode pattern 130 when the drain electrode pattern 130 overlapped with the gate wiring 102a is formed only with the semiconductor layer 106c than when it is formed with the drain electrode 108c and the semiconductor layer 106c. The capacitance is further reduced.

On the other hand, during the process of forming the drain electrode pattern 130, in which only the semiconductor layer 106c is formed on one side, the semiconductor layer and the source / drain conductive layer are patterned by using the diffraction exposure of the diffraction exposure mask. Here, a halftone mask in which the diffraction exposure portion of the diffraction exposure mask is replaced by the halftone transmission portion may be used instead of the diffraction exposure mask. Hereinafter, only the diffraction exposure mask will be described.

The method of forming the drain electrode pattern 130 will be described with reference to FIGS. 3A through 3E as in the method of forming the thin film transistor of the thin film transistor array substrate.

3A to 3E are sectional views taken along the line III-III 'of the process flowchart showing the method of forming the thin film transistor, and sectional views along the line IV-IV' of Figs. 3A to 3E illustrate the method of forming the drain electrode pattern 130; One process flow chart.

As shown in FIG. 3A, a gate wiring 102a, a gate electrode 102c, and a light shielding pattern 102b are formed on the insulating substrate 100. The gate wiring 102a, the gate electrode 102c, and the light shielding pattern 102b are formed on the insulating substrate 100 by a deposition method such as a sputtering method, and then a photolithography process using a first mask. It is formed by patterning.

Subsequently, as shown in FIG. 3B, the gate insulating film 104 and the second conductive layer, which are first insulating films, are formed on the insulating substrate 100 on which the gate wiring 102a, the gate electrode 102c, and the light shielding pattern 102b are formed. The phosphorus semiconductor layer 106a and the third conductive layer 108a are sequentially formed.

Next, as shown in FIG. 3C, a photoresist pattern 20 defining a source electrode pattern and a drain electrode pattern is formed on the insulating substrate 100. The photoresist pattern 20 is formed by forming a photoresist on the third conductive layer 108a and then arranging the second mask 22 to perform a photo process. Here, the second mask 22 is a diffraction exposure area 22c which consists of a transmission area 22a for passing all the light, a plurality of slits for transmitting a part of the light and blocking a part of the light, and a blocking area 22b for blocking the light. A diffraction exposure mask is used. In this case, the diffraction exposure area 22c corresponds to a region where a source electrode (108b of FIG. 3D) and a drain electrode (108c of FIG. 3D) of the drain electrode pattern are defined, particularly a gate of the drain electrode pattern. The area also overlaps with the wiring. Therefore, the thickness of the photoresist pattern formed in the diffraction exposure region 22c is lower than the thickness of the photoresist pattern formed in the blocking region 22b.

Subsequently, as shown in FIG. 3D, a source electrode pattern and a drain electrode pattern are formed on the insulating substrate 100.

The source electrode pattern is defined by the source electrode 108b and the semiconductor layer 106b formed thereunder, and the drain electrode pattern 130 is defined by being laminated with the drain electrode 108c and the semiconductor layer 106b formed thereunder. Alternatively, only the semiconductor layer 106b is defined. In other words, the drain electrode pattern 130 formed between the source electrode 108b of the drain electrode pattern 130 is formed by stacking the drain electrode 108c and the semiconductor layer 106b formed below the gate electrode 102a. Only the semiconductor layer 106b is formed in the drain electrode pattern 130 formed in the overlapped region.

The source electrode pattern and the drain electrode pattern are formed by etching the semiconductor layer 106a and the third conductive layer 108a using the photoresist pattern 20 formed on the third conductive layer 108a as a mask. In other words, the photoresist pattern formed in the blocking region and the diffraction exposure region is etched with a mask to pattern the semiconductor layer 106a, and at the same time, the third conductive layer 108a formed on the semiconductor layer 106a is patterned to form a source electrode. 108b and drain electrode 108c are formed. At this time, the photoresist pattern 20 formed by the diffraction exposure area 22c disposed in the region overlapping with the gate wiring 102a is etched using a mask, and the third conductive layer () is formed in the region overlapping with the gate wiring 102a. 108a is removed, and only the semiconductor layer 106b remains.

Next, as shown in FIG. 3E, the passivation layer 110, which is a second insulating layer having a contact hole exposing the drain electrode 108c, is formed on the insulating substrate 100 on which the source electrode pattern and the drain electrode pattern are formed. do.

The passivation layer 110 having the contact hole is formed by depositing a passivation layer on the insulating substrate 100 on which the drain electrode 108c is formed and patterning the same by a photolithography process using a third mask.

Subsequently, the pixel electrode 111, which is a transparent conductive layer, is formed on the passivation layer 110 having the contact hole. The pixel electrode 111 is formed by depositing a fourth conductive layer of a transparent material on an insulating substrate on which the passivation layer 110 is formed and patterning the same by a photolithography process using a fourth mask. The pixel electrode 111 is connected to the drain electrode 108c via the contact hole.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a plan view illustrating a thin film transistor array substrate for a liquid crystal display according to the related art.

2 is a plan view illustrating a thin film transistor array substrate for a liquid crystal display according to the present invention.

3A to 3E are cross-sectional views taken along lines III-III 'and IV-IV' of FIG. 2.

4 is a detailed view of the light blocking pattern and the drain electrode pattern according to the related art and the light blocking pattern and the drain electrode pattern according to the present invention.

Claims (7)

A gate wiring and a data wiring crossing each other on the substrate to define a pixel region; A thin film transistor formed at an intersection of the gate line and the data line and formed of a gate electrode, a source electrode pattern, and a drain electrode pattern; A pixel electrode connected to the thin film transistor; A light blocking pattern formed to overlap an edge of the pixel electrode; And the drain electrode pattern is formed to be adjacent to the source electrode pattern and overlaps with the gate wiring. According to claim 1, The drain electrode pattern formed to be adjacent to the source electrode pattern is stacked with a drain electrode and a semiconductor layer, and the drain electrode pattern formed to overlap the gate wiring is formed with a semiconductor layer. Board. The method of claim 1, wherein the light shielding pattern is A thin film transistor array substrate for liquid crystal display device, characterized in that formed of an opaque metal film. Forming a gate wiring, a gate electrode, and a light shielding pattern on the substrate; Forming a first insulating layer, a second conductive layer, and a third conductive layer on the substrate on which the light blocking pattern is formed; Patterning the second conductive layer and the third conductive layer to form a source electrode pattern and a drain electrode pattern, wherein the drain electrode pattern is formed to be adjacent to the source electrode pattern and overlaps with the gate wiring; , Forming a second insulating film having a contact hole exposing the drain electrode pattern on the substrate on which the source electrode pattern and the drain electrode pattern are formed; And forming a pixel electrode on the second insulating layer via the contact hole. The method of claim 4, wherein The drain electrode pattern formed to be adjacent to the source electrode pattern is stacked with the third conductive layer and the second conductive layer, and the drain electrode pattern formed to overlap the gate wiring is formed with a second conductive layer. A method of manufacturing a thin film transistor array substrate for a display device. The method of claim 4, wherein the second conductive layer and the third conductive layer are patterned to form a source electrode pattern and a drain electrode pattern, wherein the drain electrode pattern is formed to be adjacent to the source electrode pattern. Forming to overlap Forming a photoresist on the third conductive layer; Forming a photoresist pattern by performing a photo process on the photoresist using a diffraction exposure mask; And etching the second conductive layer and the third conductive layer using the photoresist pattern as a mask. The method of claim 6, wherein the diffraction exposure mask is And a diffraction exposure portion disposed in a region where a drain electrode pattern overlapping the gate wiring is to be formed.

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