KR101419224B1 - Thin Film Transistor Array Substrate for Liquid Crystal Display Device and method of manufacturing the same - Google Patents

Abstract

A thin film transistor array substrate for a liquid crystal display according to the present invention includes a thin film transistor formed at an intersection of a gate wiring and a data wiring and a light shielding pattern formed on the same layer as the gate wiring and overlapping the edge of the pixel electrode The thin film transistor includes a gate electrode; A semiconductor layer; A source electrode; Drain electrode, wherein the source electrode is formed of a double layer including a first patterned layer made of a part of the semiconductor layer and a second patterned layer on the first patterned layer, Wherein a portion of the drain electrode overlaps with the gate wiring, and a portion of the drain electrode overlapping the gate wiring overlaps the gate electrode of the second pattern layer, 3 pattern layer.

Shielding pattern, opening area

Description

[0001] The present invention relates to a thin film transistor array substrate for a liquid crystal display device and a method of manufacturing the thin film transistor array substrate.

The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly to a thin film transistor array substrate for a liquid crystal display device and a manufacturing method thereof.

In general, a liquid crystal display displays an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field.

Such a liquid crystal display device includes a color filter array substrate on which R, G, and B color filter layers for implementing a black matrix and colors for preventing light leakage are formed, a gate wiring and a data wiring for defining unit pixels, And a thin film transistor array substrate on which pixel electrodes are formed.

The thin film transistor array substrate for a liquid crystal display device will be specifically described with reference to the accompanying drawings.

1 is a plan view showing a conventional thin film transistor array substrate for a liquid crystal display device.

1, a thin film transistor substrate of a liquid crystal display device includes a gate wiring 112a and a data wiring 118a which are perpendicular to each other with a gate insulating film interposed therebetween to define a pixel region, A pixel electrode 120 formed in each pixel region and connected to the thin film transistor, and a light shielding pattern 112b overlapping the edge of the pixel electrode 120. The thin film transistor (TFT) .
The thin film transistor includes a gate electrode 112c connected to the gate wiring 112a and a semiconductor layer (not shown) formed so as to overlap a part of the gate electrode 112c on a gate insulating film (not shown) And source / drain electrodes 118b and 118c formed to be spaced apart from each other on a semiconductor layer (not shown). The pixel electrode 120 is connected to the drain electrode 118c through a protective film (not shown) covering the source / drain electrodes 118b and 118c.

At this time, the light shielding pattern 112b is formed of an opaque metal film such as the gate wiring 112a in the same layer as the gate wiring 112a, and the boundary portion overlaps the edge of the pixel electrode 120. [ The light-shielding pattern 112b blocks light incident from a backlight, which is a light source of a liquid crystal display, together with a black matrix (not shown) of the color filter array substrate to prevent light leakage at the periphery of the pixel region.

 However, when the light shielding pattern 112b is included, there is a problem that the light shielding at the outskirts of the pixel area can be more easily prevented, while the opening area is further reduced by the area corresponding to the light shielding pattern 112b in the pixel area .

In order to solve the above problems, the present invention provides a thin film transistor array substrate for a liquid crystal display device and a method of manufacturing the same, which can increase the aperture ratio by reducing a light shielding region defined as a light shielding pattern for preventing light leakage.

According to an aspect of the present invention, there is provided a thin film transistor array substrate for a liquid crystal display, including: a gate wiring and a data wiring which are formed on a substrate so as to intersect with each other to define a pixel region; A pixel electrode formed in each of the pixel regions and connected to the thin film transistor, and a light shielding pattern formed on the same layer as the gate wiring and overlapping the edge of the pixel electrode. The thin film transistor includes: a gate electrode formed on the substrate and connected to the gate wiring; A semiconductor layer formed on the gate insulating layer to cover at least part of the gate electrode, the light shielding pattern, and the gate electrode; A source electrode connected to the data line and including a part of the semiconductor layer; And a drain electrode spaced apart from the source electrode, the drain electrode including another portion of the semiconductor layer. The source electrode is formed of a double layer including a first patterned layer made of a part of the semiconductor layer and a second patterned layer formed on the first patterned layer, And a third pattern layer formed at a different portion apart from the pattern layer, wherein a part of the drain electrode overlaps with the gate wiring, and a part of the drain electrode overlapping with the gate wiring is formed in the third pattern layer And is formed as a single layer.
The drain electrode may further include a fourth pattern layer formed on a part of the third pattern layer surrounded by the second pattern layer of the source electrode and spaced apart from the gate wiring.

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A method of manufacturing a thin film transistor array substrate for a liquid crystal display according to an embodiment of the present invention includes the steps of patterning a first conductive layer on a substrate to form gate wirings in one direction, gate electrodes branched in the gate wirings, Forming a first insulating film, a second conductive layer, and a third conductive layer on the entire surface of the substrate so as to cover the gate wiring, the gate electrode, and the shielding pattern; 2 conductive layer and the third conductive layer to form a data line in a direction crossing the gate line, a semiconductor layer overlapping a part of the gate line, a source electrode branched in the data line, Forming a drain electrode spaced apart from the source electrode, forming a second insulating film on the entire surface of the first insulating film, Forming a contact hole exposing a part of the drain electrode by patterning a second insulating film; forming a pixel electrode, which is connected to the drain electrode through the contact hole and whose edge overlaps with the light- On the pixel region of the pixel electrode.
In the step of forming the data line, the semiconductor layer, the source electrode, and the drain electrode, the semiconductor layer is formed of the second conductive layer, and each of the data line and the source electrode is formed in the second and / And a third pattern layer made of a third conductive layer, wherein the drain electrode includes a third pattern layer made of the second conductive layer, and a part of the drain electrode is overlapped with the gate wiring, And a part of the drain electrode overlapping the gate wiring is formed as a single layer of the third pattern layer.

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A thin film transistor array substrate for a liquid crystal display and a method of manufacturing the same according to the present invention include a drain electrode biased toward a gate wiring side so as to overlap a gate wiring. As a result, as the drain electrode is shifted toward the gate wiring side, the region corresponding to the light shielding pattern in the pixel region is reduced, and the opening region of each pixel region is increased.
The source electrode is formed of a double layer including a first pattern layer made of a part of the semiconductor layer and a second pattern layer on the first pattern layer.
On the other hand, the drain electrode may be formed as a single layer of the third patterned layer made of another part of the semiconductor layer. Alternatively, at least a part of the drain electrode overlapping with the gate wiring is formed as a single layer of the third pattern layer, and the remaining part of the region is formed as a double layer including the third pattern layer and the fourth pattern layer on the third pattern layer .
If the region of the drain electrode overlapping with the gate wiring is formed as a single layer of the third pattern layer, as compared with the case where the drain electrode and the gate wiring are formed of the double layer of the third and fourth pattern layers, There is an effect that the generated parasitic capacitance can be reduced.

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Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

FIG. 2 is a plan view showing a thin film transistor array substrate for a liquid crystal display according to the present invention, and FIGS. 3A to 3E are sectional views taken on line III-III 'and line IV-IV' in FIG.

2 and 3E, the thin film transistor array substrate for a liquid crystal display according to the present invention includes a gate wiring 102a and a data wiring 108d which cross each other on a lower substrate 100 and define a pixel region, A thin film transistor formed at an intersection between the gate wiring 102a and the data wiring 108d, a pixel electrode 111 formed in the pixel region and connected to the thin film transistor, And a light-shielding pattern 102b formed to overlap the edge of the pixel electrode 111. [
The gate wiring 102a and the light shielding pattern 102b are formed on the lower substrate 100 so as to be spaced apart from each other and are covered with a gate insulating film 104 formed on the entire surface of the lower substrate 100. [ The data wiring 108d is formed so as to intersect the gate wiring 102 on the gate insulating film 104. [ That is, the gate wiring 102a and the data wiring 108d are formed so as to cross each other with the gate insulating film 104 therebetween.

The light shielding pattern 102b is formed of an opaque metal film such as a gate wiring 102a and is positioned such that the boundary portion overlaps the edge of the pixel electrode 111. [
2 and 3E, the liquid crystal display device includes a color filter array substrate (not shown) opposite to the thin film transistor array substrate, and the color filter array substrate has a plurality of And a black matrix (not shown). Thus, the light-shielding pattern 102b overlapping the edge of the pixel electrode 111 blocks light incident from a backlight which is a light source of the liquid crystal display device together with a black matrix (not shown), thereby preventing light leakage at the periphery of the pixel region .
The thin film transistor includes a gate electrode 102c connected to the gate wiring 102a and a semiconductor layer 106b formed on the gate insulating film 104 covering the gate electrode 102c and overlapped with a part of the gate electrode 102c, A source electrode 108b connected to the data line 108d and a drain electrode 108c spaced apart from the source electrode 108b.
The gate electrode 102c is formed on the same layer as the gate wiring 102a, that is, on the lower substrate 100, and is branched at the gate wiring 102a.
The source electrodes 106c and 108b include a first pattern layer 106c formed of a part of the semiconductor layer 106b which is in contact with the data line 108d and a second pattern layer 108b on the first pattern layer 106c Layer.
The drain electrode 130 includes a third pattern layer 106d made of another part of the semiconductor layer 106b spaced apart from the second pattern layer 108b of the source electrode. Here, a part of the third pattern layer 106d overlaps the gate wiring 102a.
The drain electrode 130 may be formed as a single layer of the third pattern layer 106d.
Alternatively, the drain electrode 130 may further include a fourth pattern layer 108c formed on another portion of the third pattern layer 106d surrounded by the second pattern layer 108b of the source electrode. Here, the fourth pattern layer 108c is spaced apart from the second pattern layer 108b of the source electrode. In addition, the fourth pattern layer 108c is spaced apart from the gate wiring 102a so as not to overlap the gate wiring 102a, unlike the third pattern layer 106d.
Further, although not shown in detail in the drawings, the semiconductor layer 106b is formed with the data line 108d, the source electrode 108b and the drain electrode 108c, so that the data line 108d is also connected to the source electrode 106c , And 108b.
As described above, according to the embodiment of the present invention, the drain electrodes 106d and 108c are formed biased to the gate wiring 102a side so as to overlap with the gate wiring 102a.
That is, as shown in Fig. 4, the conventional drain electrode 118c (shown by a dotted line in Fig. 4) is spaced apart from the gate wiring 102a by a predetermined distance. This is because, if the drain electrode 118c and the gate wiring 102a overlap, unnecessary parasitic capacitance can be generated. Therefore, like the drain electrode 118c, the pixel electrode (120 in FIG. 1) connected to the drain electrode 118c and the light shielding pattern 112b overlapping the edge of the pixel electrode 120 are also separated from the gate wiring 112a The area corresponding to the light shielding pattern 112b in the pixel area is difficult to be reduced.
On the other hand, the drain electrode 130 according to the embodiment of the present invention includes a third pattern layer 106d that overlaps with the gate wiring 102a. At this time, the region of the drain electrode 130 overlapping the gate wiring 102a is formed as a single layer of the third pattern layer 106d, which is another part of the semiconductor layer 106b. Accordingly, compared with the case where the region overlapping the gate wiring 102a in the drain electrode 130 is formed as a double layer including the third and fourth pattern layers 106d and 108c, the drain electrode 130 and the gate wiring The parasitic capacitances generated in the regions where the first electrodes 102a and the second electrodes 102a overlap each other can be reduced.
As described above, at least a part of the drain electrode 130 according to the embodiment of the present invention overlaps with the gate wiring 130, and the drain electrode 130 is shifted to the gate wiring 102a side from the conventional drain electrode 118c The parasitic capacitance with the gate wiring 102a can be prevented from increasing greatly.
As the drain electrode 130 is shifted toward the gate wiring 102a, the pixel electrode 111 and the light shielding pattern 112b are also shifted toward the gate wiring 102a. That is, the light-shielding pattern 112b according to the embodiment of the present invention can be located closer to the gate wiring 102a side than the conventional light-shielding pattern 102b, Since the area can be reduced, the opening area of each pixel area is increased as compared with the conventional one.

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Meanwhile, the drain electrode 130 is formed to expose the third pattern layer 106d in a region overlapping at least the gate wiring 102a. The drain electrode 130 may be formed using diffraction exposure of a diffraction exposure mask. Here, instead of the diffraction exposure mask, a half tone mask in which the diffraction exposure unit of the diffraction exposure mask is replaced with a halftone transmission unit is applied. Hereinafter, only the diffraction exposure mask will be described.

The method of forming the drain electrode 130 will be described with reference to FIGS. 3A to 3E as well as the method of forming the thin film transistor of the thin film transistor array substrate.

Sectional views taken along line III-III 'in FIGS. 3A to 3E are process flow diagrams showing a method of forming a thin film transistor, and sectional views taken along a line IV-IV' in FIGS. 3A to 3E show a method of forming the drain electrode 130 Fig.

A gate wiring 102a, a gate electrode 102c and a light shielding pattern 102b are formed on an insulating substrate 100 as shown in Fig. The gate wiring 102a, the gate electrode 102c and the light shielding pattern 102b may be formed by forming a first conductive layer on the insulating substrate 100 through a vapor deposition method such as a sputtering method on the insulating substrate 100, 1 mask using a photolithography process using a mask as shown in FIG. 2, the gate wiring 102a is formed in one direction on the insulating substrate 100, the gate electrode 102c is formed by branching from the gate wiring 102a, and the light shielding pattern 102b is formed Is spaced apart from the gate wiring 102a and the gate electrode 102c and is formed to overlap with the edge of the pixel electrode (111 in Fig. 2).
A first insulating film, that is, a gate insulating film 104, is formed on the entire surface of the insulating substrate 100 so as to cover the gate wiring 102a, the gate electrode 102c, and the shielding pattern 102b.

Next, as shown in FIG. 3B, a second conductive layer 106a and a third conductive layer 108a are sequentially formed on the first insulating layer 104. Next, as shown in FIG. Here, the second conductive layer 106a is formed of a semiconductor material so as to be a semiconductor layer that selectively forms a channel. The third conductive layer 108a is formed of a conductive material such as a metal.

Next, as shown in FIG. 3C, a photoresist (not shown) is formed on the third conductive layer 108a and a photolithography process is performed on the photoresist (not shown) using the second mask 22 Whereby a photoresist pattern 20 is formed.
The second mask 22 includes a transmissive area 22a through which light is entirely passed, a diffraction exposure area 22c composed of a plurality of slits that transmit a part of the light and block a part of the light, and a blocking area 22b ) Is used as a diffraction exposure mask.
The blocking region 22b of the second mask 22 corresponds to the second pattern layer 108b of the source electrode and the fourth pattern layer 108c of the drain electrode 130. [ And, although not separately shown, the shielding region 22b of the second mask 22 corresponds more to the data wiring (108d in Fig. 2).
The diffraction exposure region 22c of the second mask 22 is formed in the region between the second pattern layer 108b of the source electrode and the fourth pattern layer 108c of the drain electrode 130, And corresponds to a part of the region where the third pattern layer 106d is exposed. That is, the diffraction exposure area 22c of the second mask 22 corresponds to the area where only the third conductive layer 108a is removed and the second conductive layer 106a remains. A portion of the drain electrode 130 corresponding to the diffraction exposure region 22c of the second mask is a region where the third pattern layer 106d is exposed to the outside without being covered with the fourth pattern layer 108c, At least a part of which overlaps the gate wiring 102a.
The photoresist pattern 20 is formed to have a first thickness in a region corresponding to the blocking region 22b of the second mask 22 and is formed in a region corresponding to the diffraction exposure region 22c of the second mask 22. [ 1, and may be removed in a region corresponding to the transmissive region 22a of the second mask 22. In this case,

3D, the second and third conductive films 106a and 108a are subjected to differential patterning by using the photoresist pattern 20 to form the data wiring 108d on the first insulating film 104. Then, A semiconductor layer 106b, source electrodes 106c and 108b, and drain electrodes 106d and 108c, respectively.

The source electrode includes a first pattern layer 106c formed of a part connected to the data line 108d of the semiconductor layer 106b and a second pattern layer 106c composed of a third conductive film 108a on the first pattern layer 106c 108b.
The data wiring 108d is formed of a double layer of the second and third conductive films 106a and 108c, like the source electrodes 106c and 108b.
The drain electrode 130 may be formed as a single layer of the third pattern layer 106d, which is another portion of the semiconductor layer 106b spaced apart from the second pattern layer 108b of the source electrode. Here, at least a part of the third pattern layer 106d overlaps the gate wiring 102a.
Alternatively, the drain electrode 130 may further include a fourth pattern layer 108c formed on another portion of the third pattern layer 106d surrounded by the second pattern layer 108b of the source electrode. Here, the fourth pattern layer 108c is spaced apart from the second pattern layer 108b of the source electrode, is spaced apart from the gate wiring 102a, and does not overlap the gate wiring 102a.
The second mask 22 includes the diffraction exposure region 22c corresponding to the drain electrode 130 when the drain electrode 130 is formed as a single layer of the third pattern layer 106d.
A part of the drain electrode 130 overlapping at least the gate wiring 102a is formed as a single layer of the third pattern layer 106d and the remaining part of the drain electrode 130 is formed as a part of the third and fourth pattern layers 106d and 108c The second mask 22 is not covered with the blocking region 22b corresponding to the fourth pattern layer 108c and the fourth pattern layer 108c of the drain electrode 130, 3 pattern layer 106d. The diffraction exposure area 22c corresponds to the three-pattern layer 106d.
The steps of forming the data line, the source electrode, and the drain electrode are as follows. First, the photoresist pattern 20 is formed, and then the second and third conductive films 106a And 108a are etched to form a data wiring, a source electrode, and a drain electrode, respectively, as a double layer. Subsequently, the photoresist pattern 20 is ashed, the diffraction exposure region is removed, and only the third conductive film 108a is etched in a state where only the blocking region is left, thereby forming the third conductive film 108a between the source electrode and the drain electrode And part of the third conductive film 108a overlapping with the gate wiring 102a in the drain electrode is removed.

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3E, a protective layer 110 is formed on the insulating substrate 100 on which the source and drain electrodes are formed. The protective layer 110 is a second insulating layer having a contact hole exposing the drain electrode 108c.

The passivation layer 110 having the contact hole is formed by depositing a passivation layer on the insulating substrate 100 on which the drain electrode 108c is formed, and then patterning the passivation layer by a photolithography process using a third mask.

The pixel electrode 111, which is a transparent conductive layer, is formed on the passivation layer 110 on which the contact hole is formed. The pixel electrode 111 is formed by depositing a fourth conductive layer of a transparent material on an insulating substrate on which the passivation layer 110 is formed, and then patterning the fourth conductive layer by a photolithography process using a fourth mask. The pixel electrode 111 is connected to the drain electrode 108c via the contact hole.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

1 is a plan view showing a conventional thin film transistor array substrate for a liquid crystal display

2 is a plan view showing a thin film transistor array substrate for a liquid crystal display according to the present invention.

Figs. 3A to 3E are cross-sectional views taken on line III-III 'and line IV-IV'

Fig. 4 is a diagram showing the details of the position of the light-shielding pattern and the drain electrode in the prior art,

Claims (7)

A gate wiring and a data wiring which are formed on the substrate so as to cross each other and define a pixel region, A thin film transistor formed at an intersection of the gate wiring and the data wiring, A pixel electrode formed in each of the pixel regions and connected to the thin film transistor, And a light shielding pattern formed on the same layer as the gate wiring and overlapping the edge of the pixel electrode, The thin film transistor A gate electrode formed on the substrate and connected to the gate wiring; A semiconductor layer formed on the gate insulating layer to cover at least part of the gate electrode, the light shielding pattern, and the gate electrode; A source electrode connected to the data line and including a part of the semiconductor layer; And a drain electrode spaced apart from the source electrode, the drain electrode including another portion of the semiconductor layer, Wherein the source electrode is formed of a double layer including a first pattern layer made of a part of the semiconductor layer and a second pattern layer formed on the first pattern layer, Wherein the drain electrode includes a third pattern layer formed of another portion of the semiconductor layer spaced apart from the second pattern layer of the source electrode, A part of the drain electrode overlaps with the gate wiring, And a part of the drain electrode overlapping with the gate wiring is formed as a single layer of the third pattern layer. The method according to claim 1, Wherein the drain electrode further comprises a fourth pattern layer formed on a part of the third pattern layer surrounded by the second pattern layer of the source electrode and being spaced apart from the gate wiring. The light-emitting device according to claim 1, wherein the light- Wherein the transparent conductive film is formed of an opaque metal film. Patterning a first conductive layer on a substrate to form a gate wiring in one direction, a gate electrode branched in the gate wiring, and a shielding pattern spaced apart from the gate wiring; Forming a first insulating layer, a second conductive layer, and a third conductive layer on the entire surface of the substrate so as to cover the gate wiring, the gate electrode, and the shielding pattern; A second conductive layer and a third conductive layer formed on the first conductive layer, the second conductive layer, and the third conductive layer to form a data line in a direction crossing the gate line, a semiconductor layer overlapping a part of the gate electrode, And forming a drain electrode spaced from the source electrode, Forming a second insulating film on the entire surface of the first insulating film, Patterning the second insulating film to form a contact hole exposing a part of the drain electrode; And forming a pixel electrode connected to the drain electrode through the contact hole and having an edge overlapping the light shielding pattern in the pixel region on the second insulating film, In the step of forming the data line, the semiconductor layer, the source electrode, and the drain electrode, The semiconductor layer is formed of the second conductive layer, Each of the data line and the source electrode is formed of a double layer of first and second pattern layers made of the second and third conductive layers, Wherein the drain electrode comprises a third pattern layer of the second conductive layer, A part of the drain electrode overlaps with the gate wiring, And a part of the drain electrode overlapping with the gate wiring is formed as a single layer of the third pattern layer. 5. The method of claim 4, In the step of forming the data line, the semiconductor layer, the source electrode, and the drain electrode, Wherein the drain electrode further comprises a fourth pattern layer made of the third conductive layer on a part of the third pattern layer surrounded by the second pattern layer of the source electrode, Wherein the fourth pattern layer is spaced apart from the gate wiring. 6. The method of claim 5, The step of forming the data line, the semiconductor layer, the source electrode, and the drain electrode includes Forming a photoresist on the third conductive layer; Forming a photoresist pattern by performing a photolithography process using a diffraction exposure mask; And etching the second conductive layer and the third conductive layer using the photoresist pattern as a mask. 7. The exposure apparatus according to claim 6, wherein the diffraction exposure mask And a diffraction exposure unit corresponding to a region between the second pattern layer of the source electrode and the fourth pattern layer of the drain electrode and a part of the drain electrode overlapping with the gate wiring. A method of manufacturing a thin film transistor array substrate.

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