KR20090022077A

KR20090022077A - Liquid crystal display device

Info

Publication number: KR20090022077A
Application number: KR1020070087132A
Authority: KR
Inventors: 송인덕
Original assignee: 엘지디스플레이 주식회사
Priority date: 2007-08-29
Filing date: 2007-08-29
Publication date: 2009-03-04

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to high brightness by preventing light leakage in a pixel area. In particular, the present invention relates to preventing light leakage generated in the drain contact hole portion of the high definition model.

In the present invention, a storage on common type liquid crystal display device requiring a separate capacitor electrode is characterized in that the pixel is designed so that the common wiring and the drain contact hole are not exposed to the display area.

In detail, a portion corresponding to the first and second vertical portions of the common wiring vertically branched parallel to the data lines and extending to the display area is shielded by a black matrix configured on the color filter substrate, and the first and second vertical portions are shielded. By shielding the horizontal portion of the common wiring and the drain contact hole with the black matrix while the horizontal portion connecting the portions together is designed to bypass the drain electrode along the edge of the pixel region, an opaque metal does not exist in the display region. It is characterized in that the pixel design to avoid.

Such a configuration has an advantage of improving image quality by preventing light leakage in the common wiring and the drain contact hole.

Description

Liquid Crystal Display Device

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the liquid crystal may be artificially applied to control the direction of the molecular arrangement.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

In addition, the liquid crystal display includes a color filter substrate on which a common electrode is formed, an array substrate on which a pixel electrode is formed, and a liquid crystal filled between the two substrates, and the liquid crystal display is a vertical electric field that extends up and down between the common and pixel electrodes. By the method of driving the liquid crystal, it is excellent in characteristics such as transmittance and aperture ratio.

In general, the pixel electrode of the array substrate forms a liquid crystal capacitor together with the common electrode of the color filter substrate, and the voltage applied to the liquid crystal capacitor is not maintained until the next signal comes in and leaks away.

Therefore, in order to maintain the applied voltage, the storage capacitor must be connected to the liquid crystal capacitor.

In general, the storage capacitor may be formed in two ways, in which electrodes for the storage capacitor are separately formed and connected to the common electrode, and a portion of the n−1 th gate wiring is connected to the electrode of the storage capacitor of the n th pixel. There is a way to use it.

The former is called a storage on common method or an independent storage capacitor method, and the latter is called a storage on gate or a prior gate method.

The storage-on-gate method has an advantage of not requiring external storage wiring since the storage signal is applied using a gate wiring, but has a disadvantage of receiving signal interference due to coupling with the gate signal.

On the other hand, the storage-on-common method has an advantage that there is no interference with the gate signal and sufficient storage capacity can be secured. However, the common wiring is additionally formed, which reduces the aperture ratio due to light leakage. .

FIG. 1 is a plan view illustrating a unit pixel of a conventional array substrate for a liquid crystal display device.

As shown in the drawing, a plurality of gate lines 52 are spaced in one direction on the substrate 50 in parallel with the plurality of gate lines 52, and the common lines are spaced apart from each of the gate lines 52. 80 is configured.

A plurality of data wires 60 are formed in a direction perpendicular to the gate wires 52, and the area defined by the vertical cross of the gate wires 52 and the data wires 60 is referred to as a pixel area P. FIG. do.

In this case, the common wiring 80 passes through the first and second vertical portions 80a and 80b spaced apart from each other in parallel with the data wirings 60 on both sides, and passes through the central portion of the pixel region P. It includes a horizontal portion (80c) connecting the two vertical portions (80a, 80b) into one.

The thin film transistor T is formed at the intersection of the gate line 52 and the data line 60. The thin film transistor T may include a gate electrode 54 extending from the gate line 52, a semiconductor layer (not shown) partially overlapping the gate electrode 54, and a portion of the thin film transistor T on the semiconductor layer. A portion of the gate electrode 54 overlaps with the area of the gate electrode 54, and includes a source electrode 62 extending from the data line 60, and a drain electrode 64 spaced apart from the source electrode 62.

In this case, the semiconductor layer includes an active layer 84 made of pure amorphous silicon (a-Si: H), and an impurity amorphous silicon (n + a−) doped with group 3 or group 5 elements on the active layer 84. Ohmic contact layer (not shown) made of Si: H).

The pixel electrode 70 in contact with the drain electrode 64 through the drain contact hole CH1 exposing a part of the drain electrode 64 is configured to correspond to the pixel region P. Referring to FIG.

In general, the pixel electrode 70 is made of one selected from a transparent conductive metal material including indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin oxide (ITZO). do.

In this case, a storage capacitor Cst is formed using the common wiring 80 as a first electrode and a portion of the pixel electrode 70 overlapping the common wiring 80 as a second electrode.

Hereinafter, a liquid crystal display according to the related art will be described in detail with reference to the accompanying drawings.

2A and 2B are cross-sectional views taken along the lines IIa-IIa and IIb-IIb of FIG. 1, and include an opposingly bonded array and a color filter substrate and a liquid crystal layer interposed between the two substrates. It is sectional drawing which shows the liquid crystal panel. 3 is a plan view schematically illustrating a unit pixel of a liquid crystal display according to the related art.

As shown in FIGS. 2A, 2B, and 3, the color filter substrate 10 and the array substrate 50, which are divided into the display area AA and the non-display area NAA, are opposed to each other. The liquid crystal layer 30 is interposed between the substrate 10 and the array substrate 50 with a constant cell gap. In this case, the color filters, the array substrates 10 and 50, and the liquid crystal layer 30 form a liquid crystal panel 5.

Although not shown in detail in the drawings, the two substrates 10 and 50 are bonded by a seal pattern (not shown) made of a material such as a thermosetting resin along the outermost edge. In addition, a backlight 90 serving as a light source is disposed on the rear surface of the array substrate 50.

A black matrix 12 is formed below the transparent substrate 1 of the color filter substrate 10 to block light incident to the non-display area NAA, and a color is formed below the black matrix 12. A color filter layer 14 including sequentially patterned R, G, and B sub color filters 14a, 14b, and 14c, a common electrode 18 formed of a transparent conductive metal under the color filter layer 14, and The upper alignment layer 25 configured to uniformly align the liquid crystal 32 is disposed below the common electrode 18.

Although not shown in the drawings, an overcoat layer (not shown) may be further configured to planarize each layer between the black matrix 12 and the color filter layer 14.

In addition, a gate wiring 52 and a gate electrode 54 extending from the gate wiring 52 are spaced apart from the transparent substrate 2 of the array substrate 50 in parallel with the gate wiring 52. The common wiring 80 penetrating through the central portion of the pixel region P is positioned.

A gate insulating film 45 is formed on the gate electrode 54, the gate wiring 52, and the common wiring 80, and a semiconductor layer on which the gate electrode 54 and a portion thereof overlap. 86 is located.

The semiconductor layer 86 includes an active layer 84 made of pure amorphous silicon (a-Si: H) and an ohmic contact layer 85 made of impurity amorphous silicon layer (n + a-Si: H). On the semiconductor layer 86, a data line 60 defining a pixel region P perpendicularly intersecting with the gate line 52, and extending from the data line 60, the semiconductor layer 86, A portion of the source electrode 62 overlapping with each other and a drain electrode 64 spaced apart from the source electrode 62 are positioned.

In this case, the gate electrode 54, the gate insulating layer 45, the semiconductor layer 86, and the source and drain electrodes 62 and 64 positioned at the intersection of the gate line 52 and the data line 60 are included. This is called a thin film transistor (T).

The passivation layer 55 is formed on the thin film transistor T as one selected from a group of inorganic insulating materials including silicon oxide and silicon nitride. The common wiring 80 described above connects the first and second vertical portions 80a and 80b spaced apart from each other and parallel to the data lines 60 on both sides, and the first and second vertical portions 80a and 80b. And a horizontal portion 80c penetrating the central portion of the pixel region P.

On the passivation layer 55, a pixel electrode 70 made of a transparent conductive metal including indium tin oxide and indium zinc oxide is formed on the passivation layer 55. It is configured to correspond to. In addition, a lower alignment layer 26 is formed on the pixel electrode 70 to uniformly align the liquid crystal 32.

In the above-described storage on common method, the overlapping area between the pixel electrode 70 and the common line 80 is maximized to maximize storage capacity, and the coupling capping between the pixel electrode 70 and the data line 60 is performed. In order to prevent cross talk due to capacitance, the first and second vertical portions 80a and 80b may be partially overlapped with the pixel electrode 70 and the data line 60 in plan view. Doing.

In addition, the black matrix 12 formed on the color filter substrate 10 does not completely shield the common wiring 80 and the drain contact hole CH2, and a part of the common wiring 80 and the drain contact hole ( A portion of CH1) is designed to be exposed to the display area AA so as to minimize a decrease in the aperture ratio.

However, in a state where a step is generated between each of the wirings sequentially stacked on the array substrate 50, the upper and lower alignment layers 25 and 26 are formed and a rubbing process is performed using a rubbing cloth (not shown). In particular, the first stepped portion F corresponding to the first and second vertical portions 80a and 80b of the common wiring, and the second stepped portion G corresponding to the horizontal portion 80c, are described in terms of the step by each wiring. This results in the liquid crystals 32 located at) not having a uniform angle.

In the first and second stepped portions (F, G), due to the generation of the foreground line due to the non-uniformity of the liquid crystal alignment, the liquid crystal 32 is impossible to control, causing light leakage.

Further problematic is that when the data line 60 and the source and drain electrodes 62 and 64 are formed of a material such as molybdenum or molybdenum alloy, it is necessary to expose a portion of the drain electrode 64 to this portion. In the process of removing the corresponding protective film 55 and the gate insulating film 45 by a dry etching process, molybdenum vulnerable to the dry etching process is removed together with the protective film 55 and the gate insulating film 45. The drain electrode 64 formed of the aforementioned material is designed to be in side contact with the pixel electrode 70 made of a transparent conductive material.

In this case, the liquid crystal display device, which is a light-receiving display device, implements a desired image by irradiating the liquid crystal panel 5 with light from the backlight 90 positioned on the rear surface of the array substrate 50.

However, in the above-described configuration, since a part of the drain electrode 64 corresponding to the drain contact hole CH1 is removed by the dry etching process, the light from the backlight 90 penetrates as it is, causing light leakage. do.

In this case, the above-mentioned light leakage is negligible in the medium sized model or more, such as a TV or a notebook, but the high quality model, especially the small model of 7 inches or less, is acting as a culprit of deterioration of image quality.

Detailed description of the high-definition model described above may vary depending on the resolution, but the pixel per inch (ppi), defined as the number of pixels per inch according to each model, is 80-130 ppi for TVs, 80-130 ppi for laptops, The small model is designed for 140-220 ppi.

In this case, unlike a large-sized model such as a TV or a notebook, the small contact model has a number of pixels per inch of 140 to 220 ppi, and the area of the drain contact hole CH1 occupies about 20 in the area of each pixel area P. It is close to ~ 40%. This is due to the limitation of the resolution of the exposure equipment. In particular, in the small model, it is difficult to reduce the area of the drain contact hole CH1 due to the high resolution of ppi.

For this reason, in the case of a high-definition model, the area occupied by the drain contact hole in the pixel area is large, and unlike a large model such as a TV or a notebook, even if a little light leaks in the drain contact hole part, the image quality is greatly affected. There is a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to improve image quality by preventing light leakage with a pixel design without an opaque conductive metal in a display area.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a plurality of gate wirings arranged in one direction on the first substrate, the first and second substrates being divided into a display area and a non-display area; The thin film transistor through a plurality of data lines defining a pixel area vertically crossing the plurality of gate lines, a thin film transistor configured at an intersection point of the gate line and the data line, and a drain contact hole exposing a portion of the thin film transistor. A pixel electrode connected to the gate electrode; a common wiring spaced in parallel with the gate wiring; and the thin film transistor, a gate, and a data wiring formed under the second substrate and corresponding to the non-display area on the first substrate. A black matrix shielding all portions of the common wiring and the drain contact hole, and a lower portion of the black matrix And a liquid crystal layer interposed between the first and second substrates, a seal pattern formed along the outermost edges of the first and second substrates, and a common electrode formed under the color filter layer. It features.

In this case, the pixel is designed such that an opaque metal does not exist in the display area through which light is transmitted except for the black matrix.

The common line may include a horizontal portion spaced apart in parallel with the gate line along an edge of the pixel region, and first and second vertical portions vertically branched in parallel with the plurality of data lines in the horizontal portion. In this case, the horizontal portion is configured to bypass the lower portion of the drain contact hole.

The common wiring may be made of the same material as the gate wiring, and the data wiring and the source and drain electrodes may be made of molybdenum or molybdenum alloy.

Therefore, in the present invention, the image quality can be improved by designing a pixel such that an opaque metal does not exist in the display area while minimizing a decrease in the aperture ratio.

In addition, the high-definition model has the effect of improving the image quality and yield through preventing light leakage in the contact hole portion.

--- Example ---

The present invention is characterized by providing a pixel design capable of blocking the generation of light leakage by shielding with a black matrix so that an opaque metal does not exist in the display area. In particular, it is characterized by preventing light leakage generated in the drain contact hole portion of the high resolution model.

Hereinafter, a liquid crystal display according to the present invention will be described with reference to the accompanying drawings.

4 is a plan view illustrating unit pixels of an array substrate for a liquid crystal display according to the present invention.

As shown in the drawing, a plurality of gate lines 152 are spaced in one direction on the substrate 150 in parallel with the plurality of gate lines 152, and the common lines are spaced apart from each of the gate lines 152. Configure 180.

A plurality of data wires 160 are formed in a direction perpendicular to the gate wires 152. The area defined by the vertical cross of the gate wires 152 and the data wires 160 is referred to as a pixel area P. FIG. do.

The thin film transistor T is formed at the intersection of the gate line 152 and the data line 160. The thin film transistor T may include a gate electrode 154 extending from the gate line 152, a semiconductor layer (not shown) partially overlapping the gate electrode 154, and a portion of the thin film transistor T on the semiconductor layer. A portion of the gate electrode 154 overlaps with the gate electrode 154, and includes a source electrode 162 extending from the data line 160, and a drain electrode 164 spaced apart from the source electrode 162.

The semiconductor layer includes an active layer 184 made of pure amorphous silicon (a-Si: H), and an impurity amorphous silicon (n + a-Si: doped with Group 3 or Group 5 elements on the active layer 184). And an ohmic contact layer (not shown) made of H).

In this case, the common line 180 may include a horizontal portion 180c spaced apart from the gate line 152 along the edge of the pixel region P, and the data lines 160 on both sides of the horizontal portion 180c. First and second vertical portions 180a and 180b that are vertically branched in parallel. In this case, the horizontal portion 180c is configured to bypass the drain electrode 164 to correspond to the pixel region P so as to overlap the drain electrode 164 in a plane.

The pixel electrode 170, which is in contact with the drain electrode 164 through the drain contact hole CH2 exposing a portion of the drain electrode 164, is configured to correspond to the pixel region P. Referring to FIG. In general, the pixel electrode 170 is made of one selected from a transparent conductive metal material including indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin oxide (ITZO). can do.

Here, even when the drain electrode 164 is made of molybdenum or molybdenum alloy, light leakage in the drain contact hole CH2 may be blocked by the horizontal part 180c disposed below the drain electrode 164. Therefore, there is an advantage that the opening ratio can be minimized.

In this case, a storage capacitor Cst is formed using the common wiring 180 as a first electrode and a portion of the pixel electrode 170 overlapping the common wiring 180 as a second electrode.

In the above-described configuration, the black is disposed on the color filter substrate (not shown) in order not to expose the drain contact hole CH2 and the common wiring 180 formed to correspond to the pixel region P to the display region AA. The drain contact hole CH2 and the common wiring 180 are shielded by a matrix, which will be described in detail with reference to the accompanying drawings.

5A and 5B are respective cross-sectional views taken along the lines Va-Va and Vb-Vb of FIG. 4, and include, in detail, an opposingly bonded array and a color filter substrate and a liquid crystal layer interposed between the two substrates. It is sectional drawing which shows the liquid crystal panel. 6 is a plan view schematically illustrating a unit pixel of a liquid crystal display according to the present invention.

As shown in FIGS. 5A, 5B, and 6, the color filter substrate 110 and the array substrate 150 divided into the display area AA and the non-display area NAA are opposed to each other. The liquid crystal layer 130 has a constant cell gap between the substrate 110 and the array substrate 150.

Although not shown in detail in the drawings, both substrates 110 are formed by a seal pattern (not shown) including one selected from a material including a thermosetting resin or an ultraviolet curable resin along outermost edges of the color filter and the array substrates 110 and 150. , 150) are bonded.

In this case, the color filter and the array substrates 110 and 150 and the liquid crystal layer 130 are referred to as a liquid crystal panel 105. The backlight 190 serving as a light source is positioned on the rear surface of the array substrate 150.

A black matrix 112 is provided below the transparent substrate 101 of the color filter substrate 110 to shield light incident to the non-display area NAA, and a color is formed below the black matrix 112. A color filter layer 114 including sequentially patterned R, G, and B sub color filters 114a, 114b, and 114c, a common electrode 118 formed of a transparent conductive metal under the color filter layer 114, and The upper alignment layer 125 configured for uniform alignment of the liquid crystal 132 is sequentially disposed below the common electrode 118.

Although not shown in the drawings, an overcoat layer (not shown) may be further configured between the black matrix 112 and the color filter layer 114 for planarization of each layer.

In addition, a gate wiring 152, a gate electrode 154 extending from the gate wiring 152, and the gate wiring 152 are spaced apart from each other on the transparent substrate 102 of the array substrate 150. The common line 180 is positioned along the edge of the pixel area P.

A gate insulating layer 145 is formed on the gate electrode 154, the gate wiring 152, and the common wiring 180, and a semiconductor layer on which the gate electrode 154 and a portion thereof overlap. 186 is located.

The semiconductor layer 186 includes an active layer 184 made of pure amorphous silicon (a-Si: H), and an ohmic contact layer 185 made of impurity amorphous silicon layer (n + a-Si: H). On the semiconductor layer 186, the data line 160 vertically intersects the gate line 152 and defines the pixel region P. The data line 160 extends from the data line 160. Partly overlapped source electrode 162 and the drain electrode 164 spaced apart from the source electrode 162 is located.

In this case, the gate electrode 154, the gate insulating layer 145, the semiconductor layer 186, and the source and drain electrodes 162 and 164 may be formed to form a thin film transistor T.

On the thin film transistor T, the passivation layer 155 is formed of one selected from the group of inorganic insulating materials including silicon oxide (SiO ₂ ) and silicon nitride (SiNx).

The common wire 180 described above connects the first and second vertical parts 180a and 180b spaced apart from each other to be parallel to the data wires 160 on both sides, and the first and second vertical parts 180a and 180b as one. And a horizontal portion 180c spaced apart from and parallel to the gate line 152 along the edge of the pixel region P.

At this time, in the present invention, the horizontal portion 180c is configured to bypass the edge of the pixel region P, particularly the lower portion of the drain electrode 164, and corresponds to the lower portion of the color filter substrate 110. The black matrix 112 may be designed to shield the non-display area NAA, particularly the drain contact hole CH2 and the first and second vertical portions 180a and 180b.

This configuration can provide a pixel design in which the horizontal line 180c does not exist in the display area AA because the common wire 180 bypasses the edge of the pixel area P instead of penetrating the center part. By shielding the horizontal portion 180c and the first and second vertical portions 180a and 180b with the black matrix 112, light leakage from the stepped portion may be prevented.

In addition, the opening ratio is configured to bypass the horizontal portion 180c to the lower portion of the drain contact hole CH2 and to shield the horizontal portion 180c and the drain contact hole CH2 portion with the black matrix 112. There is an advantage that can prevent the source of light leakage while minimizing this infringement.

In addition, the passivation layer 155 may include a pixel electrode 170 made of a transparent conductive metal including indium tin oxide (In-Tin-Oxide) and indium zinc oxide (In-Zn-Oxide). It constitutes corresponding to P). In addition, a lower alignment layer 126 is formed on the pixel electrode 170 to uniformly align the liquid crystal 132.

In this case, in the above-described configuration, the common wiring 180 is configured to overlap a portion of the pixel electrode 170 along the edge of the pixel region P, and thus the pixel electrode 170 and the common wiring ( The overlapped area between the two layers 180 can be secured at a level comparable to that of the related art, and a cross formed by the coupling cap between the pixel electrode 70 and the data line 60 through the first and second vertical portions 180a and 180b. Torque can be prevented.

In summary, in the present invention, in order to prevent the common wiring 180 and the drain contact hole CH2 from being exposed to the display area AA, portions corresponding to the first and second vertical portions 180a and 180b are disposed. A horizontal portion 180c is shielded with a black matrix 112 formed on the color filter substrate 110 and connects the first and second vertical portions 180a and 180b into one, along the edge of the pixel region P. The pixel is designed so that an opaque metal does not exist in the display area AA.

Therefore, the present invention has an advantage of minimizing image quality defects by blocking light leakage in the drain contact hole part while minimizing intrusion of the aperture ratio.

However, the present invention is not limited to the above embodiments, and it will be apparent that various modifications and changes can be made without departing from the spirit and spirit of the present invention.

1 is a plan view showing a unit pixel of a conventional array substrate for a liquid crystal display device.

2A and 2B are cross-sectional views taken along the lines IIa-IIa and IIb-IIb of FIG. 1, respectively.

3 is a plan view schematically illustrating a unit pixel of a liquid crystal display according to the related art.

4 is a plan view showing unit pixels of an array substrate for a liquid crystal display according to the present invention;

5A and 5B are cross-sectional views taken along the lines Va-Va and Vb-Vb of FIG. 4, respectively.

6 is a plan view schematically illustrating a unit pixel of a liquid crystal display according to the present invention;

* Explanation of symbols for the main parts of the drawings *

112: black matrix 150: substrate

152: gate wiring 154: gate electrode

160: data wiring 162: source electrode

164: drain electrode 170: pixel electrode

180: common wiring 184: active layer

CH2: Drain contact hole P: Pixel area

AA: display area NAA: non-display area

Claims

In the first and second substrates divided into a display area and a non-display area,

A plurality of gate lines arranged in one direction on the first substrate;

A plurality of data lines defining a pixel area vertically crossing the plurality of gate lines;

A thin film transistor configured at an intersection point of the gate line and the data line;

A pixel electrode connected to the thin film transistor through a drain contact hole exposing a portion of the thin film transistor;

Common wiring spaced apart in parallel with the gate wiring;

A black matrix formed under the second substrate and shielding all of the thin film transistor, the gate and the data wiring, the common wiring, and the drain contact hole formed corresponding to the non-display area on the first substrate;

A color filter layer formed under the black matrix;

A common electrode formed under the color filter layer;

A seal pattern formed along outermost edges of the first and second substrates;

Liquid crystal layer interposed between the first and second substrate

Liquid crystal display comprising a.

The method of claim 1,

And a pixel design such that an opaque metal does not exist in the display area through which light is transmitted except for the black matrix.

The method of claim 1,

The common line may include a horizontal portion spaced apart in parallel with the gate line along an edge of the pixel region, and first and second vertical portions vertically branched in parallel with the plurality of data lines in the horizontal portion. Liquid crystal display device.

The method of claim 3, wherein

And the horizontal portion bypasses the drain contact hole.

The method of claim 1,

And the common wiring is made of the same material as the gate wiring.

The method of claim 1,

And the data line and the source and drain electrodes are made of molybdenum or molybdenum alloy.