KR20090016089A - Method for forming emitter layer of silicon solar cell - Google Patents

Abstract

A method for forming an emitter layer of a silicon solar cell is provided to improve efficiency of the solar cell by removing a dead layer selectively after forming the emitter layer by an impurity diffusion process. A silicon semiconductor substrate(201) doped with p-type impurity is prepared. An n-type impurity oxide film(202) is formed in a substrate surface. The n-type impurity included in the n-type impurity oxide film is diffused to the inside through the substrate surface. An emitter layer(203) composed of the n-type silicon semiconductor layer is formed on an upper part of the substrate with a predetermined thickness. A dead layer doped with the n-type impurity is selectively removed by using etchant. The etchant is made by mixing the nitric acid, the hydrofluoric acid, the acetic acid and the water in a volume ratio of 10:0.1 to 0.01:1-3:5-10.

Description

Method for forming emitter layer of silicon solar cell

  The present invention relates to a solar cell manufacturing method, and more particularly, to a method of forming an emitter layer of a silicon solar cell so as to improve the efficiency of the solar cell.

Recently, as the prediction of depletion of existing energy sources such as oil and coal is increasing, interest in alternative energy to replace them is increasing. Among them, solar cells are particularly attracting attention because they are rich in energy resources and have no problems with environmental pollution.

Solar cells are classified into solar cells that generate steam required to rotate turbines using solar heat, and solar cells that convert photons into electrical energy using the properties of semiconductors. It refers to a solar cell (hereinafter referred to as a solar cell).

Solar cells are largely classified into silicon solar cells, compound semiconductor solar cells, and tandem solar cells according to raw materials. Of these three types of solar cells, silicon solar cells are the mainstream in the solar cell market.

1 is a cross-sectional view showing the basic structure of a silicon solar cell. Referring to the drawings, a silicon solar cell includes a substrate 101 made of a p-type silicon semiconductor and an emitter layer 102 made of an n-type silicon semiconductor, and a diode is provided at an interface between the substrate 101 and the emitter layer 102. Similarly, pn junctions are formed.

When sunlight is incident on a solar cell having the above structure, electrons and holes are generated in a silicon semiconductor doped with impurities by a photovoltaic effect. For reference, electrons are generated as carriers in the emitter layer 102 made of n-type silicon semiconductor, and holes are generated as carriers in the substrate 101 made of p-type silicon semiconductor. Electrons and electrons generated by the photovoltaic effect are attracted to the n-type silicon semiconductor and the p-type silicon semiconductor, respectively, and move to the electrodes 103 and 104 bonded below the substrate 101 and the emitter layer 102, respectively. When the electrodes 103 and 104 are connected by wires, current flows.

The output characteristics of the solar cell are evaluated by measuring the output current-voltage curve of the solar cell. The maximum output Pm is defined as the point where the product Ip × Vp of the output current Ip and the output voltage Vp becomes maximum on the output current-voltage curve, and the total light energy incident on the solar cell (S × I: S is The element area, I, is defined as the conversion efficiency η divided by the intensity of light irradiated to the solar cell. To increase the conversion efficiency η, increase the short-circuit current Isc (output current when V = 0 on the output current-voltage curve) or open voltage Voc (output voltage when I = 0 on the output current-voltage curve) or output current. Increase the fill factor, which represents the square of the voltage curve. The closer the fidelity value is to 1, the closer the output current-voltage curve is to the ideal square and the higher the conversion efficiency η.

Among the three factors that determine the efficiency of the solar cell, the open-voltage behavior is closely related to the doping concentration of the n-type impurity when the n-type impurity is diffused on the surface of the p-type silicon semiconductor substrate to form the emitter layer. For reference, the doping profile of the n-type impurity has the highest surface of the emitter layer and decreases according to the Gaussian distribution or the error function as it enters the inside of the emitter layer.

In the related art, an impurity was excessively doped in forming an emitter layer to increase the open voltage of a solar cell. In this case, the top layer portion of the emitter layer (hereinafter referred to as the 'dead layer') causes the concentration of the doped n-type impurity to increase beyond the solid solubility in the silicon semiconductor. For reference, the dead layer has a thickness of about 50 ~ 200 nm. As a result, there is a problem that the mobility of the carrier is reduced near the emitter layer surface and the scattering effect with excessive impurities increases the recombination rate of the carrier and the lifetime of the carrier is also reduced.

In order to solve the above problems, the emitter layer is formed by a diffusion process subject to excessive doping of impurities and then adversely affects the performance of the solar cell by wet etching using a mixture of nitric acid and hydrofluoric acid or CF ₄ plasma etching. Emitter etch-back processes have been proposed to remove layers.

However, the mixture of nitric acid and hydrofluoric acid or CF ₄ plasma has a disadvantage in that the etching selectivity for the dead layer is not excellent and the etching speed is high. Therefore, the conventional emitter etch-back process has limitations in process reproducibility and stability in removing dead layers having a very thin thickness.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, by forming an emitter layer by an impurity diffusion process, and then selectively removing the dead layer using a wet etchant having high etching selectivity to the dead layer. An object of the present invention is to provide an emitter layer forming method capable of improving the efficiency of a battery.

According to an aspect of the present invention, there is provided a method of forming an emitter layer of a silicon solar cell, comprising: preparing a silicon semiconductor substrate of a first conductivity type; Forming an emitter layer on the substrate by diffusing impurities of a second conductivity type opposite to the first conductivity type onto a surface of the silicon semiconductor substrate; And a dead layer on top of the emitter layer and doped with a second conductivity type impurity above the solid solubility in the silicon semiconductor by nitric acid (HNO ₃ ), hydrofluoric acid (HF), acetic acid (CH ₃ COOH) and water H ₂ O) is characterized in that it comprises the step of selectively removing using an etchant mixed in a volume ratio of 10: 0.1 ~ 0.01: 1 ~ 3: 5 ~ 10.

In the present invention, the impurity doping concentration of the dead layer is 10 ²⁰ atoms / cm ³ or more.

Preferably, the substrate is a silicon semiconductor substrate doped with p-type impurities, and the emitter layer is a silicon semiconductor layer doped with n-type impurities.

Preferably, the etchant has a faster etching rate for the dead layer than the etching rate for the emitter layer other than the dead layer. The etching rate for the dead layer is 0.08 ~ 0.12 um / sec, the etching rate for the emitter layer other than the dead layer is 0.01 ~ 0.03um / sec.

According to the present invention, after the emitter layer is formed by the impurity diffusion process in the manufacture of the silicon solar cell, by selectively removing the top dead layer, the carrier recombination rate can be reduced to increase the life of the carrier. As a result, the opening voltage of the solar cell is increased to improve the efficiency of the solar cell. In addition, since the carriers generated through light absorption in the dead layer are directly recombined, selective removal of the dead layer may prevent light absorption in the dead layer and increase carrier generation through light absorption in other regions. As a result, the short-circuit current of the solar cell is increased to improve the efficiency of the solar cell.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, the terms or words used in this specification and claims should not be construed as being limited to the common or dictionary meanings, and the inventors should properly introduce the concept of terms to explain their own invention in the best way possible. It should be interpreted as meanings and concepts in accordance with the technical spirit of the present invention based on the principle that it can be defined. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiments of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

1 to 5 are cross-sectional views illustrating a method of forming an emitter layer of a silicon solar cell according to a preferred embodiment of the present invention.

Referring to FIG. 2, first, a substrate 201 made of a p-type silicon semiconductor is prepared and loaded into a diffusion furnace. Here, the substrate 201 is a single crystal, polycrystalline or amorphous silicon semiconductor substrate. Then, an n-type impurity source is injected into the diffusion path together with oxygen gas to form an oxide film 202 containing n-type impurity on the upper surface of the substrate 201 to a constant thickness by a thermal oxidation reaction.

Preferably, the n-type impurity oxide film 202 is a P ₂ O ₅ film and is formed to a thickness of about 30 to 50 nm. The n-type impurity source is POCl ₃ and is injected into the diffusion furnace using nitrogen gas as the carrier gas. However, the present invention is not limited to the type of n-type impurity source and n-type impurity oxide film 202.

Referring to FIG. 3, after the n-type impurity oxide film 202 is formed on the surface of the substrate 201, the temperature of the diffusion path is increased to 800 to 850 degrees to form an n-type impurity contained in the oxide film 202. Drive-in to the top surface of 201). In this case, the diffusion time is maintained for 30 to 60 minutes so that a sufficient amount of n-type impurities can be diffused to the substrate 201. Then, the n-type impurity contained in the n-type impurity oxide film 202 diffuses into the inside through the surface of the substrate 201, so that the emitter layer 203 made of the n-type silicon semiconductor layer with a predetermined thickness on the substrate 201. Is formed.

Referring to FIG. 4, after completion of the n-type impurity drive-in, the n-type impurity oxide film 202 remaining on the surface of the substrate 201 is removed using dilute hydrofluoric acid and the substrate 201 is cleaned with pure water. . This completes the diffusion process of the n-type impurity for forming the emitter layer 203.

The concentration of the n-type impurity implanted into the emitter layer 203 through the above-described n-type impurity diffusion process is the highest on the surface of the emitter layer 203 and enters the interior of the emitter layer 203 as a Gaussian distribution or error function. Accordingly. In addition, since the process conditions are controlled so that a sufficient amount of n-type impurities may be diffused during the diffusion process, a dead layer doped with n-type impurities at a concentration of solid solubility or higher exists in the uppermost portion of the emitter layer 203.

6 is a graph showing the concentration of the doped n-type impurities from the surface of the emitter layer 203 toward the substrate 201 after the diffusion process of the n-type impurities is completed. In the graph, the horizontal axis is the depth of the point where the concentration of the n-type impurity is measured based on the surface of the emitter layer 203, and the vertical axis is the n-type impurity concentration of the measurement point.

Referring to FIG. 6, the concentration of the n-type impurity near the surface of the emitter layer 203 is highest and the concentration of the n-type impurity decreases toward the substrate 201, particularly in the silicon semiconductor near the surface (the dotted box portion). It can be seen that there is a dead layer doped with n-type impurities above the solid solubility at. The concentration of the n-type impurity contained in the dead layer varies depending on the type of the n-type impurity. When the n-type impurity is phosphorus (P), it is 10 ²⁰ atom / cm ³ or more.

Referring to FIG. 5, after the n-type impurity diffusion process is performed as described above, the emitter layer 203 may be formed by using an etchant whose etching rate is changed according to the concentration of impurities doped in the emitter layer 203. Selectively remove the dead layer on the top.

Preferably, the etchant comprises a mixture of nitric acid (HNO ₃ ), hydrofluoric acid (HF), acetic acid (CH ₃ COOH) and water (H ₂ O) in a volume ratio of 10: 0.1 ~ 0.01: 1 ~ 3: 5 ~ 10. As such, the etch rate for the dead layer is faster than the etch rate for the emitter layer 203 other than the dead layer. That is, the etching rate for the dead layer is 0.08 ~ 0.12um / sec, the etching rate for the emitter layer 203 other than the dead layer is 0.01 ~ 0.03um / sec. Due to such an etching rate difference, when the etching process is performed using the etching solution, the dead layer doped with n-type impurities at a concentration higher than the solid solubility in the silicon semiconductor may be selectively removed at the beginning of the etching process. On the other hand, it is apparent that the etch rate of the dead layer described above may be partially changed by the volume ratio of the etching solution composition, the type and concentration of the diffused impurities, and the like.

Nitric acid among the materials mixed in the etchant oxidizes the surface of the dead layer. And hydrofluoric acid etch the portion oxidized by nitric acid. The hydrofluoric acid tends to selectively etch the crystallographic structural defects of the silicon semiconductor, and the oxidation of the silicon semiconductor by nitric acid tends to be activated as the doping concentration of the n-type impurity increases. Therefore, as the nitric acid is contained in the etchant, the dead layer may be uniformly etched. And the more the hydrofluoric acid is contained in the etchant can increase the etching speed of the dead layer.

In the composition of the etchant, if the hydrofluoric acid content is higher than the upper limit, the uniformity of the oxide film etching is deteriorated and the retardability of the dead layer removal process is inferior due to the fast etching rate. When the amount of hydrofluoric acid is less than the lower limit, the oxide etching rate is too slow or the oxide etching is hardly generated.

In addition, water and acetic acid in the material contained in the etchant serves to delay the etching rate of the oxide film by hydrofluoric acid. And acetic acid functions to accelerate the oxidation of the silicon semiconductor by nitric acid. Thus acetic acid helps to shape the uniformity of etching by complementing the function of nitric acid.

In the composition of the etchant, when the content of water and acetic acid is larger than the upper limit, the etching rate of the oxide film by hydrofluoric acid is too slow or hardly etch occurs. If the content of water and acetic acid is less than the lower limit, it is difficult to ensure reproducibility of the dead layer removal process due to the rapid etching rate of the oxide film by hydrofluoric acid.

7 is a graph illustrating the etching thickness (Y-axis) according to the etching time (X-axis) when the etching process is performed using the etchant according to the present invention, and FIG. 8 is the etching time (X-axis). It is a graph which measured and showed the etching rate (Y-axis) along. In FIG. 8, the solid line is calculated and shown as 'total etching thickness / total etching elapsed time', and the dotted line is a graph illustrating the calculation of 'a change in etching thickness / a change in etching elapsed time'.

Referring to FIG. 7, it can be seen that the dead layer is rapidly etched to a depth of 0.300 μm where the doping concentration of the n-type impurity is high, but the emitter layer 203 is slowly etched at a depth of 0.300 μm or more. 8, after about 3 seconds after the start of etching, the dead layer having a high concentration of n-type impurity is etched at a fast etching rate of 0.1 μm / sec, after 3 seconds have elapsed, that is, after the removal of the dead layer is completed. It can be seen that the emitter layer 203 is removed at a slow etching rate of about 0.01 to 0.03 um / sec.

Therefore, when the etching process is performed using the etchant according to the present invention, only the dead layer may be selectively removed in the initial stage of etching. In addition, since the etching rate is clearly different according to the doping degree of the n-type impurity, reproducibility and stability of the dead layer removal process can be secured.

For example, referring to the graphs of FIGS. 7 and 8, when the etching time is set to 3 seconds or more, the dead layer may be removed. In addition, since the etching speed is significantly reduced in the section of 3 seconds or more, the process margin associated with the setting of the etching end point is increased, thereby ensuring process reproducibility and stability.

Meanwhile, the embodiment described above is related to the case where the emitter layer is formed by injecting n-type impurities into the p-type silicon semiconductor substrate. However, it will be apparent to those skilled in the art that the present invention may be applied to the case of forming an emitter layer by injecting p-type impurities into an n-type silicon semiconductor substrate.

As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto and is intended by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents of the claims to be described.

The following drawings attached to this specification are illustrative of the preferred embodiments of the present invention, and together with the detailed description of the invention serves to further understand the technical spirit of the present invention, the present invention is a matter described in such drawings It should not be construed as limited to.

1 is a cross-sectional view showing a schematic structure of a silicon solar cell according to the prior art.

2 to 5 are process cross-sectional views sequentially illustrating a method of forming an emitter layer of a silicon solar cell according to an exemplary embodiment of the present invention.

FIG. 6 is a graph illustrating the concentration of the doped n-type impurity while going from the surface of the emitter layer to the substrate after the diffusion process of the n-type impurity is completed.

7 is a graph illustrating an etching thickness (Y-axis) measured according to an etching time (X-axis) when an etching process is performed using the etchant according to the present invention.

8 is a graph illustrating an etching rate (Y-axis) according to an etching time (X-axis) when an etching process is performed using the etching solution according to the present invention.

<Main reference number in drawing>

201: substrate 202: n-type impurity oxide film

203: emitter layer

Claims (5)

Preparing a silicon semiconductor substrate of a first conductivity type; Forming an emitter layer on the substrate by diffusing impurities of a second conductivity type opposite to the first conductivity type onto a surface of the silicon semiconductor substrate; And A dead layer of nitric acid, hydrofluoric acid, acetic acid, and water in a volume ratio of 10: 0.1 to 0.01: 1 to 3: 5 to 10 is present on top of the emitter layer and doped with n-type impurities above solid solubility in a silicon semiconductor. Emitter layer forming method of a silicon solar cell comprising the step of selectively removing using a mixed etchant. The method of claim 1, wherein the impurity doping concentration of the dead layer is 10 ²⁰ atom / cm ³ or more.  The method of claim 1, And the silicon semiconductor substrate is a silicon semiconductor substrate doped with p-type impurities, and the emitter layer is a silicon semiconductor layer doped with n-type impurities. The method of claim 1, The etchant is a method of forming an emitter layer of a silicon solar cell, characterized in that the etching rate for the dead layer is faster than the etching rate for the emitter layer other than the dead layer. The method of claim 4, wherein Etch rate for the dead layer is 0.08 ~ 0.12 um / sec, Method for forming an emitter layer of a silicon solar cell, the etching rate for the emitter layer other than the dead layer is 0.01 ~ 0.03um / sec.

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