KR100199372B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR100199372B1 KR100199372B1 KR1019960050627A KR19960050627A KR100199372B1 KR 100199372 B1 KR100199372 B1 KR 100199372B1 KR 1019960050627 A KR1019960050627 A KR 1019960050627A KR 19960050627 A KR19960050627 A KR 19960050627A KR 100199372 B1 KR100199372 B1 KR 100199372B1
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- polysilicon layer
- layer
- doped polysilicon
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 85
- 229920005591 polysilicon Polymers 0.000 claims abstract description 85
- 238000000034 method Methods 0.000 claims abstract description 41
- 238000005530 etching Methods 0.000 claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000009792 diffusion process Methods 0.000 claims abstract description 3
- 238000010438 heat treatment Methods 0.000 claims description 14
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 7
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 7
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 4
- 239000011259 mixed solution Substances 0.000 claims description 4
- 125000000896 monocarboxylic acid group Chemical group 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 239000000243 solution Substances 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 66
- 206010010144 Completed suicide Diseases 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 제조방법을 제공하는 것으로, 실리콘기판상에 패턴화된 도프 및 언도프 폴리실리콘층을 형성하고, 이 도프 및 언도프 폴리실리콘층의 식각 선택비를 이용하여 게이트 전극의 하부는 좁고 상부는 넓게 형성하므로써 게이트 전극의 채널길이를 짧게 형성할 수 있고, 워드라인 형성시 저항을 감소시킴과 동시에 공정마진을 크게 확보할 수 있고, 건식확산 공정으로 얕은 접합깊이를 갖는 접합영역을 용이하게 형성할 수 있는 효과가 있다.The present invention provides a method of fabricating a semiconductor device comprising forming a patterned doped and undoped polysilicon layer on a silicon substrate and etching the lower portion of the gate electrode using the etch selectivity ratio of the doped and undoped polysilicon layer, The channel length of the gate electrode can be shortened by forming the gate electrode narrower and the upper portion of the gate electrode can be shortened. In addition, the resistance of the word line can be reduced and the process margin can be secured. In the dry diffusion process, There is an effect that it can be easily formed.
Description
본 발명은 언도프 및 도프 폴리실리콘층의 식각비를 이용하여 짧은 채널길이를 갖는 게이트 전극을 형성할 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device capable of forming a gate electrode having a short channel length using an etch ratio of undoped and doped polysilicon layers.
일반적으로 반도체 소자는 기가 디램(Giga DRAM)급의 초고집적 회로소자에서 채널 길이가 0.15㎛ 이하의 N모스 트랜지스터가 요구되고, 소스 및 드레인 접합영역 또한 0.06㎛ 이하의 깊이가 요구되고 있다. N모스 트랜지스터 선폭의 미세화와 소자의 고집적화에 따라 워드라인(Word Line)의 총길이도 길어지고, 소스 및 드레인 접합영역의 깊이 또한 얕아져서 워드라인 및 콘택의 저항증가로 인하여 소자의 속도저하를 초래하므로써 고집적화에 따른 소자의 고속화에 결정적인 영향을 준다. 이러한 문제를 해결하기 위하여 실리사이드(Silicide) 게이트 및 실리사이드 게이트 구조를 이용한 소자의 고속화를 이루려는 연구가 진행되고 있다.In general, a semiconductor device requires an N-MOS transistor having a channel length of 0.15 mu m or less in an ultra-high-integration circuit device of the Giga DRAM class, and the source and drain junction regions are also required to have a depth of 0.06 mu m or less. As the line width of the N-MOS transistor is miniaturized and the device is highly integrated, the total length of the word line is lengthened and the depth of the source and drain junction regions becomes shallow, thereby causing a decrease in the speed of the device due to an increase in resistance of the word line and the contact. It has a decisive influence on the speed-up of the device due to the high integration. In order to solve such a problem, studies are being conducted to realize a high speed device using a silicide gate and a silicide gate structure.
본 발명은 실리콘 기판상에 패턴화된 도프 및 언도프 폴리실리콘층의 식각 선택비를 이용하여 게이트 전극의 하부는 좁고 상부는 넓게 형성하며, 건식 확산공정으로 얕은 접합영역을 형성할 수 있는 반도체 소자의 제조방법을 제공하는 것을 그 목적으로 한다.The present invention relates to a semiconductor device capable of forming a shallow junction region by forming a lower portion of the gate electrode narrower and an upper portion larger by using the etch selectivity ratio of the doped and undoped polysilicon layer patterned on the silicon substrate, And a method for producing the same.
상술한 목적을 실현하기 위한 본 발명의 제1실시예는 필드산화막이 형성된 실리콘기판상에 게이트 산화막, 도프 폴리실리콘층, 언도프 폴리실리콘층 및 텅스텐 실리사이드층을 순차적으로 형성하는 단계와, 상기 단계로부터 텅스텐 실리사이드층, 언도프 폴리실리콘층, 도프 폴리실리콘층 및 게이트 산화막을 순차적으로 식각하여 게이트 전극을 형성하는 단계와, 상기 단계로부터 저농도 접합영역을 형성한 후 제1열처리 공정을 실시하는 단계와, 상기 단계로부터 도프 폴리실리콘층 및 언도프폴리실리콘층의 식각 선택비를 이용한 식각공정으로 도프 폴리실리콘층의 측벽을 소정부분 식각한 후 제2열처리 공정을 실시하는 단계와, 상기 단계로부터 실리콘기판의 전체 상부면에 고농도 불순물 이온을 주입하여 언도프 폴리실리콘층을 도프 폴리실리콘층으로 변환시키는 동시에 소스 및 드레인 접합영역을 형성하는 단계와, 상기 단계로부터 노출된 게이트 산화막을 제거하는 단계로 이루어진다.In order to achieve the above-mentioned object, a first embodiment of the present invention is a method of manufacturing a field oxide film, comprising: sequentially forming a gate oxide film, a doped polysilicon layer, an undoped polysilicon layer and a tungsten silicide layer on a silicon substrate having a field oxide film formed thereon; Forming a gate electrode by sequentially etching a tungsten suicide layer, an undoped polysilicon layer, a doped polysilicon layer, and a gate oxide film; performing a first heat treatment process after forming the low concentration junction region from the above step; Etching the sidewalls of the doped polysilicon layer by a predetermined etching process using an etch selectivity ratio of the doped polysilicon layer and the undoped polysilicon layer, and then performing a second heat treatment process; High-concentration impurity ions are implanted into the entire upper surface of the undoped polysilicon layer, Forming source and drain junction regions while at the same time and converted into the layer, a step of removing the gate oxide layer exposed through the step.
또한 상술한 목적을 달성하기 위한 본 발명의 제2실시예는 필드산화막이 형성된 실리콘기판상에 게이트 산화막, 도프 폴리실리콘층, 언도프 폴리실리콘층 및 텅스텐 실리사이드층을 순차적으로 형성하는 단계와, 상기 단계로부터 텅스텐 실리사이드층, 언도프 폴리실리콘층, 도프 폴리실리콘층 및 게이트 산화막을 순차적으로 식각하여 게이트 전극을 형성하는 단계와, 상기 단계로부터 실리콘기판에 열처리 공정을 실시하는 단계와, 상기 단계로부터 도프 및 언도프 폴리실리콘층의 식각 선택비를 이용한 식각공정으로 도프 폴리실리콘층의 측벽을 소정부분 식각하는 단계와, 상기 단계로부터 노출된 게이트 산화막을 제거하는 단계와, 상기 단계로부터 언도프 폴리실리콘층을 도프 폴리실리콘층으로 변환시키는 동시에 확산된 저농도 접합 영역을 형성하는 단계와, 상기 단계로부터 실리콘기판의 전체 상부면에 고농도 불순물 이온을 주입하여 소스 및 드레인 접합영역을 형성하는 단계로 이루어진다.According to another aspect of the present invention, there is provided a method of manufacturing a field oxide film, comprising: sequentially forming a gate oxide layer, a doped polysilicon layer, an undoped polysilicon layer, and a tungsten silicide layer on a silicon substrate on which a field oxide layer is formed; Forming a gate electrode by sequentially etching a tungsten suicide layer, an undoped polysilicon layer, a doped polysilicon layer, and a gate oxide film from the step of forming a gate electrode, performing a heat treatment process on the silicon substrate from the step, And etching the sidewalls of the doped polysilicon layer in an etch process using an etch selectivity ratio of the undoped polysilicon layer, removing the exposed gate oxide film from the polysilicon layer, To a doped polysilicon layer and at the same time to form a diffused low concentration junction region Comprising the steps of: sex, by implanting high-concentration impurity ions on the entire upper surface of the silicon substrate from the step a step of forming the source and drain junction regions.
제1a도 내지 제1d도는 본 발명의 제1실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도.FIGS. 1A to 1D are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention; FIGS.
제2a도 내지 제2e도는 본 발명의 제2실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도.FIGS. 2A to 2E are sectional views of a device for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention. FIG.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
1, 11 : 실리콘기판 2, 12 : 필드산화막1, 11: silicon substrate 2, 12: field oxide film
3, 13 : 게이트 산화막 4, 14 : 도프 폴리실리콘층3, 13: gate oxide film 4, 14: doped polysilicon layer
5, 15 : 언도프 폴리실리콘층 6, 16 : 텅스텐 실리사이드층5, 15: undoped polysilicon layer 6, 16: tungsten silicide layer
7A : 저농도 접합영역 7B, 17B : 확산된 저농도 접합영역7A: low concentration junction region 7B, 17B: diffused low concentration junction region
7, 17 : 소스 및 드레인 접합영역7, 17: source and drain junction regions
먼저 본 발명의 제1실시예에 따른 반도체 소자의 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.First, a method of manufacturing a semiconductor device according to a first embodiment of the present invention will be described in detail with reference to the accompanying drawings.
제1a도 내지 제1d도는 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도로서, 제1a도는 필드산화막(2)이 형성된 실리콘기판(1)상에 게이트 산화막(3), 도프 폴리실시콘층(4), 언도프 폴리실리콘층(5) 및 텅스텐 실리사이드층(6)을 순차적으로 형성한 상태를 도시한다. 도프 및 언도프 폴리실리콘층(4 및 5)은 비정질 또는 다결정 폴리실리콘으로 이루어지며, 도프 폴리실리콘층(4)은 10 내지 1000Å의 두께로 형성되고, 언도프 폴리실리콘층(5)은 10 내지 500Å의 두깨로 형성된다.1A to 1D are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device, wherein a gate oxide film 3, a doped poly-cone cone layer 4 ), An undoped polysilicon layer 5, and a tungsten silicide layer 6 are sequentially formed. Doped and undoped polysilicon layers 4 and 5 are made of amorphous or polycrystalline polysilicon and the doped polysilicon layer 4 is formed to a thickness of 10 to 1000 Angstroms and the undoped polysilicon layer 5 is formed of an amorphous or polycrystalline polysilicon, 500A < / RTI >
제1b도는 텅스텐 실리사이드층(6), 언도프 폴리실리콘층(5), 도프 폴리실리콘층(4) 및 게이트 산화막(3)을 순차적으로 식각하여 게이트 전극을 형성한 후 게이트 전극을 마스크로 이용한 저농도의 불순물 주입으로 저농도 접합영역(7A)을 형성하고, 제1열처리 공정을 실시한 상태를 도시한다. 게이트 전극을 형성하기 위한 패턴 공정은 아이라인 스텝퍼(I-Line Stepper) 또는 엑시머 레이져 리소그래피를 이용하여 실시되며, 형성되는 게이트 전극의 채널은 0.2 내지 0.25㎛의 길이를 갖는다. 그리고, 제1열처리 공정은 도프 폴리실리콘층(4) 내에 함유된 인(P)을 활성화 시키는데 상기 도프 폴리실리콘층(4)이 비정질 실리콘으로 이루어진 경우에는 600 내지 750℃의 온도조건에서 실시하여 활성화 시킨다.1b shows the formation of the gate electrode by sequentially etching the tungsten suicide layer 6, the undoped polysilicon layer 5, the doped polysilicon layer 4 and the gate oxide film 3, Concentration bonding region 7A is formed by the impurity implantation in the first heat treatment step and the first heat treatment step is performed. The patterning process for forming the gate electrode is performed using an i-line stepper or excimer laser lithography, and the channel of the formed gate electrode has a length of 0.2 to 0.25 mu m. The first heat treatment step activates phosphorus (P) contained in the doped polysilicon layer 4. When the doped polysilicon layer 4 is made of amorphous silicon, it is activated at a temperature of 600 to 750 ° C to activate .
제1c도는 도프 폴리실리콘층(4) 및 언도프 폴리실리콘층(5)의 식각 선택비를 이용한 식각공정으로 도프 폴리실리콘층(4)의 측벽을 소정부분 식각한 후 제2열처리 공정을 실시한 상태를 도시한다. 식각공정은 HNO3: CH3COOH : HF : 순수의 비율이 30 : 3 : 0.25 내지 1 : 15인 혼합용액을 이용하여 실시된다. 다른 방법으로는 140 내지 180℃의 온도조건에서 인산용액을 이용하여 7 내지 9초간 실시된다. 이때, 도프 폴리실리콘층(4)의 측벽은 0.05 내지 0.1㎛정도 제거된다. 그리고, 저농도 접합영역(7A)은 제2열처리 공정에 의해 식각된 도프 폴리실리콘층(4) 부분까지 확산 되도록하여 확산된 저농도 접합영역(7B)을 형성한다.1C shows a state in which a sidewall of the doped polysilicon layer 4 is partially etched by an etching process using an etch selectivity ratio of the doped polysilicon layer 4 and the undoped polysilicon layer 5 and then subjected to a second heat treatment process / RTI > The etching process is carried out using a mixed solution having a ratio of HNO 3 : CH 3 COOH: HF: pure water of 30: 3: 0.25 to 1:15. Alternatively, the reaction is carried out at a temperature of 140 to 180 DEG C for 7 to 9 seconds using a phosphoric acid solution. At this time, the side walls of the doped polysilicon layer 4 are removed by about 0.05 to 0.1 mu m. The low concentration junction region 7A is diffused to the portion of the doped polysilicon layer 4 etched by the second heat treatment process to form the low concentration junction region 7B which is diffused.
제1d도는 실리콘기판(1)의 전체 상부면에 고농도 불순물 이온을 주입하여 언도프 폴리실리콘층(5)을 도프 폴리실시콘층(5A)으로 변환시키는 동시에 소스 및 드레인 접합영역(7)을 형성한 후 노출된 게이트 산화막(3)을 제거한 상태를 도시한다. 노출된 게이트 산화막(3)은 100 : 1 비율의 HF 식각액을 사용하여 10 내지 100초간 실시되므로써 제거된다.1d shows a state in which the high concentration impurity ions are implanted into the entire upper surface of the silicon substrate 1 to convert the undoped polysilicon layer 5 into the doped polycrystalline cone layer 5A and to form the source and drain junction regions 7 And the gate oxide film 3 is removed after the gate oxide film 3 is removed. The exposed gate oxide film 3 is removed by performing HF etching with a ratio of 100: 1 for 10 to 100 seconds.
이후 공정으로 실리콘기판(1)의 전체 상부면에 층간절연막을 형성한 후 게이트 전극, 소스 및 드레인 전극에 각각 접속되는 금속배선을 형성하여 트랜지스터를 완성한다.Subsequently, an interlayer insulating film is formed on the entire upper surface of the silicon substrate 1, and then a metal interconnection connected to the gate electrode, the source and the drain electrode is formed to complete the transistor.
다음으로 본 발명의 제2실시예에 따른 반도체 소자의 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.Next, a method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described in detail with reference to the accompanying drawings.
제2a도 내지 제2e도는 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도로, 제2a도는 필드산화막(12)이 형성된 실리콘기판(11)상에 게이트 산화막(13), 도프 폴리실리콘층(14), 언도프 폴리실리콘층(15) 및 텅스텐 실리사이드층(16)을 순차적으로 형성한 상태를 도시한다. 도프 및 언도프 폴리실리콘층(14 및 15)은 비정질 또는 다결정 폴리실리콘으로 이루어지며, 도프 폴리실리콘층(14)은 10 내지 1000Å의 두께로 형성되고, 언도프 폴리실리콘층(15)은 10 내지 500Å의 두께로 형성된다.2A to 2E are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device. A gate oxide film 13, a doped polysilicon layer 14 (not shown) are formed on a silicon substrate 11 on which a field oxide film 12 is formed, ), An undoped polysilicon layer 15, and a tungsten silicide layer 16 are sequentially formed. Doped and undoped polysilicon layers 14 and 15 are made of amorphous or polycrystalline polysilicon and the doped polysilicon layer 14 is formed to a thickness of 10 to 1000 Angstroms, Lt; / RTI >
제2b도는 텅스텐 실리사이드층(16), 언도프 폴리실리콘층(15), 도프 폴리실리콘층(14) 및 게이트 산화막(13)을 순차적으로 식각하여 게이트 전극을 형성한 후 열처리 공정을 실시한 상태에서 도시한다. 게이트 전극을 형성하기 위한 패턴공정은 아이라인 스텝퍼(I-Line Stepper) 또는 엑시머 레이져 리소그래피를 이용하여 실시되며, 형성되는 게이트 전극의 채널은 0.2 내지 0.25㎛의 길이를 갖는다. 그리고, 열처리 공정은 도프 폴리실리콘층(14) 내에 함유된 인(P)을 활성화 시키는데 상기 도프 폴리실리콘층(14)이 비정질 실리콘으로 이루어진 경우에는 600 내지 750℃의 온도조건에서 실시하여 활성화 시킨다.2B shows a state in which a gate electrode is formed by successively etching the tungsten suicide layer 16, the undoped polysilicon layer 15, the doped polysilicon layer 14 and the gate oxide film 13, do. The patterning process for forming the gate electrode is performed using an i-line stepper or excimer laser lithography, and the channel of the formed gate electrode has a length of 0.2 to 0.25 mu m. The annealing process activates phosphorus (P) contained in the doped polysilicon layer 14. When the doped polysilicon layer 14 is made of amorphous silicon, it is activated at a temperature of 600 to 750 ° C to activate the doped polysilicon layer.
제2c도는 도프 폴리실리콘층(14) 및 언도프 폴리실리콘층(15)의 식각 선택비를 이용한 식각공정으로 도프 폴리실리콘층(14)의 측벽을 소정부분 식각한 후 노출된 게이트 산화막(13)을 제거한 상태를 도시한다. 식각공정은 HNO3: CH3COOH : HF : 순수의 비율이 30 : 3 : 0.25 내지 1 : 15인 혼합용액을 이용하여 실시된다. 다른 방법으로는 140 내지 180℃의 온도조건에서 인산용액을 이용하여 7 내지 9초간 실시된다. 이때, 도프 폴리실리콘층(4)의 측벽은 0.05 내지 0.1㎛정도 제거된다. 그리고 노출된 게이트 산화막(13)은 100 : 1 비율의 HF 식각액을 사용하여 10 내지 10초간 실시되므로써 제거된다.FIG. 2c shows the gate oxide film 13 exposed after the side walls of the doped polysilicon layer 14 are partially etched by an etching process using the etch selectivity ratio of the doped polysilicon layer 14 and the undoped polysilicon layer 15, Is removed. The etching process is carried out using a mixed solution having a ratio of HNO 3 : CH 3 COOH: HF: pure water of 30: 3: 0.25 to 1:15. Alternatively, the reaction is carried out at a temperature of 140 to 180 DEG C for 7 to 9 seconds using a phosphoric acid solution. At this time, the side walls of the doped polysilicon layer 4 are removed by about 0.05 to 0.1 mu m. Then, the exposed gate oxide film 13 is removed by performing the etching using a HF etchant in a ratio of 100: 1 for 10 to 10 seconds.
제2d도는 800 내지 870℃의 온도 및 4 내지 5Torr의 압력조건에서 PH3가스를 플로우 시켜 언도프 폴리실리콘층(15)을 도프 폴리실리콘층(15A)으로 변환시키는 동시에 확산된 저농도 접합영역(17B)을 형성한 상태를 도시한다.2d shows the flow of the PH 3 gas at a temperature of 800 to 870 ° C and a pressure of 4 to 5 Torr to convert the undoped polysilicon layer 15 into the doped polysilicon layer 15A and simultaneously to form the diffused low concentration junction regions 17B ) Are formed on the substrate.
제2e도는 실리콘기판(11)의 전체 상부면에 고농도 불순물 이온을 주입하여 소스 및 드레인 접합영역(17)을 형성한 상태를 도시한다.2E shows a state in which the source and drain junction regions 17 are formed by implanting high-concentration impurity ions into the entire upper surface of the silicon substrate 11. [
이후 공정으로 실리콘기판(11)의 전체 상부면에 층간절연막을 형성한 후 게이트 전극, 소스 및 드레인 전극에 각각 접속되는 금속배선을 형성하여 트랜지스터를 완성한다.After that, an interlayer insulating film is formed on the entire upper surface of the silicon substrate 11, and then a metal interconnection connected to the gate electrode, the source and the drain electrode is formed to complete the transistor.
상술한 바와같이 본 발명에 의하면 실리콘기판상에 패턴화된 도프 및 언도프 폴리실리콘층을 형성하고, 이 도프 및 언도프 폴리실리콘층의 식각 선택비를 이용하여 게이트 전극의 하부는 좁고 상부는 넓게 형성하므로써 게이트 전극의 채널길이를 짧게 형성할 수 있고, 워드라인 형성시 저항을 감소시킴과 동시에 공정마진을 크게 확보할 수 있고, 건식확산 공정으로 얕은 접합깊이를 갖는 접합용역을 용이하게 형성할 수 있는 탁월한 효과가 있다.As described above, according to the present invention, a patterned doped and undoped polysilicon layer is formed on a silicon substrate, and a lower portion of the gate electrode is narrowed by using an etch selectivity ratio of the doped and undoped polysilicon layer, It is possible to shorten the channel length of the gate electrode, to reduce the resistance in forming the word line, to secure a large process margin, and to easily form a junction service with a shallow junction depth by the dry diffusion process There is an excellent effect.
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