KR20090012458A - Method for copyback programming non volatile memory device - Google Patents

Method for copyback programming non volatile memory device Download PDF

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Publication number
KR20090012458A
KR20090012458A KR1020070076283A KR20070076283A KR20090012458A KR 20090012458 A KR20090012458 A KR 20090012458A KR 1020070076283 A KR1020070076283 A KR 1020070076283A KR 20070076283 A KR20070076283 A KR 20070076283A KR 20090012458 A KR20090012458 A KR 20090012458A
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node
data
register
sensing node
voltage
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KR1020070076283A
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Korean (ko)
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김영주
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주식회사 하이닉스반도체
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Publication of KR20090012458A publication Critical patent/KR20090012458A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/14—Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory

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Abstract

A copyback program method of a nonvolatile memory device according to an embodiment of the present invention includes reading data from a first memory cell to a sensing node, applying a voltage applied to the sensing node to first and second registers, and Storing a high level or low level voltage at a first node of the second register according to a voltage applied to the second register, and applying a voltage stored at a first node of the second register to the sensing node And programming a second memory cell according to a voltage applied from the first node to the sensing node.

Description

Method for copyback programming of nonvolatile memory device

The present invention relates to a copyback program method of a nonvolatile memory device, and more particularly, to a copyback program method through a page buffer having an improved structure to reduce chip area.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

The nonvolatile memory device typically includes a memory cell array having cells in which data is stored in a matrix form, and a page buffer for writing a memory to a specific cell of the memory cell array or reading a memory stored in a specific cell. . The page buffer may include a pair of bit lines connected to a specific memory cell, a register for temporarily storing data to be written to the memory cell array, or a register for reading and temporarily storing data of a specific cell from the memory cell array, a voltage of a specific bit line or a specific register. It includes a sensing node for sensing a level, a bit line selection unit for controlling the connection of the specific bit line and the sensing node.

On the other hand, the page buffer includes a plurality of numbers to be connected to each memory cell, and occupies most of the core area of the nonvolatile memory device. Thus, reducing the amount of specific transistors used in the page buffer can be seen as a significant contribution to reducing the overall chip size.

An object of the present invention is to provide a copyback program method of a nonvolatile memory device that can operate normally without specific transistors included in a page buffer of the nonvolatile memory device.

In accordance with another aspect of the present invention, a copyback program method of a nonvolatile memory device includes reading data from a first memory cell and applying the data to a sensing node, wherein voltages applied to the sensing node are first and second. Applying to a register, storing a high level or low level voltage at a first node of the second register according to a voltage applied to the second register, and a voltage stored at a first node of the second register. And applying a second memory cell according to the voltage applied to the sensing node and the voltage applied to the sensing node from the first node.

According to the above configuration, a normal copyback program method may be provided even through a nonvolatile memory device in which the number of transistors is significantly reduced.

1 is a circuit diagram illustrating a conventional nonvolatile memory device.

The nonvolatile memory device includes a memory cell array 110, a bit line selector 120, a first register 130, a second register 140, and a sensing node precharge unit 150.

The memory cell array 110 includes a plurality of cell strings. Each cell string includes a series of memory cells MC1 through MCn, a drain select transistor DST, and a source select transistor SST. The drain select transistor DST is connected between the memory cell MC1 and a bit line (eg, BLe), and the source select transistor SST is connected between the memory cell MCn and the common source line CSL. In the memory cell array 110, an even bit line BLe represents an even bit line and an odd bit line BLO represents an odd bit line.

The bit line selector 120, the first register 130, the second register 140, and the sensing node precharge unit 150 form a page buffer.

The bit line selector 120 includes an NMOS transistor N126 connecting the even bit line BLe and the sensing node SO in response to a first bit line select signal BSLe, and a second bit line select signal. And an NMOS transistor N128 connecting the odd bit line BLo and the sensing node SO in response to BSLo.

In addition, the bit line selector 120 connects the even bit line BLe and the control signal input terminal in response to a control signal input terminal for applying a control signal VIRPWR having a specific level and a first discharge signal DISCHe. And an NMOS transistor N124 for connecting the odd bit line BLo and a control signal input terminal in response to a second discharge signal DISCHo.

The first register 130 is connected to a first latch 132 including two inverters IV130 and IV132 and a first node QAb of the first latch, and responds to a voltage level of the sensing node SO. And an NMOS transistor N131 that is turned on, and is connected between the NMOS transistor N131 and a ground power source and turned on in response to a first read signal READ_R.

In addition, the first register may include a first data input transistor N134, a data input / output terminal YA, and a second latch of the first latch connected between the data input / output terminal YA and the first node QAb of the first latch. And a second data input transistor N135 connected between the nodes QA. Accordingly, low level data is applied to the first node when the high level first data input signal DI_L is applied, and low level data is applied to the second node when the high level second data input signal nDI_L is applied. do.

The NMOS transistor N133 selectively connects the second node and the ground terminal in response to the first reset signal RST_L. Therefore, low level data is applied to the second node when the high level first reset signal RST_L is applied.

In addition, the PMOS transistor P131 is turned on according to the voltage level of the second node QA. The PMOS transistor P131 transfers a power supply voltage as a verification signal nWDO_L when the second node is at a low level.

Also, a copyback transistor N138 is turned on according to the copyback signal CPBK and is connected between the first node QAb and the sensing node SO. Accordingly, the copyback transistor N138 transfers the data stored in the first node to the sensing node SO when the copyback signal CPBK is input.

In addition, the inverter IV134 inverts the data stored in the first node and transmits it to the sensing node, and the NMOS transistor N136 transferring the output signal of the inverter IV134 to the sensing node according to the first program signal PGM_L. And an NMOS transistor N137 transferring the output signal of the inverter IV134 to the input / output terminal YA according to the first output signal PBDO_L.

The second register 140 is connected to the second latch 142 composed of two inverters IV140 and IV142 and the first node QBb of the second latch and responds to the voltage level of the sensing node SO. And an NMOS transistor N141 that is turned on, and is connected between the NMOS transistor N141 and a ground power source and turned on in response to a second read signal READ_L.

The second register may include a first data input transistor N144, a second data input / output terminal YA and a second latch connected between the data input / output terminal YA and the first node QBb of the second latch. And a second data input transistor N145 connected between the nodes QB. Therefore, when the high level first data input signal DI_R is applied, the low level data is applied to the first node, and when the high level second data input signal nDI_R is applied, the low level data is applied to the second node. Is approved.

The NMOS transistor N143 selectively connects the second node and the ground terminal in response to a second reset signal RST_R. Therefore, low level data is applied to the second node when the high level second reset signal RST_R is applied.

In addition, the PMOS transistor P141 is turned on according to the voltage level of the second node QB. The PMOS transistor P141 transfers a power supply voltage as a verification signal nWDO_L when the second node QB is at a low level.

In addition, an NMOS transistor transferring an output signal of the inverter IV144 to a sensing node according to an inverter IV144 that inverts and stores the data stored in the first node QBb to the sensing node and a second program signal PGM_R. N146 and an NMOS transistor N147 which transfers the output signal of the inverter IV144 to the input / output terminal YA according to the second output signal PBDO_R.

The operation of the nonvolatile memory device will now be described.

2 is a waveform diagram illustrating various control signals applied during a program operation of the conventional nonvolatile memory device.

First, a high level first reset signal RST_L is applied to the first register 130 to apply low level data to the second node QA.

Next, a low level precharge signal PRECHb is applied to the sensing node precharge unit 150 to precharge the sensing node to a high level.

Next, the first read signal READ_L is applied to apply the ground voltage to the first node QAb. Accordingly, low level data is stored in the first node QAb and high level data is stored in the second node QA. Through this, the first node is initialized.

Next, high level or low level data is stored in the second node QA according to the application of the first data input signal DI_L or the second data input signal nDI_L.

The data input as described above is applied to the sensing node according to the input of the first program signal PGM_L, and accordingly, whether or not the data is programmed is determined. Typically, when the low level data is stored in the second node, the low level data is applied to the sensing node to be the program target. When the high level data is stored in the second node, the high level data is also applied to the sensing node to erase the object. do.

3 is a waveform diagram illustrating various control signals applied during a copyback operation of the conventional nonvolatile memory device.

The copyback operation is an operation of reading data stored in a specific page of a memory cell array in a page unit, storing the data in a page buffer, and programming the data stored in the page buffer in another page.

Therefore, a read operation (CopyBack READ) for reading data from a specific page of the memory cell array and a program (CopyBack PGM) for programming the read data to another page are included.

In the read operation, first, a low level precharge signal is applied to the sensing node precharge unit 150 to precharge the sensing node to a high level. Next, a high level first bit line selection signal BSLe is applied. When the cell to be read is programmed, the precharged level is maintained as it is, but when the cell is to be erased, it is transitioned to the low level. In this case, when the first read signal READ_L is applied, low level data is applied to the first node according to whether the corresponding cell is programmed. Typically, when the cell is programmed, low level data is applied to the first node QAb, and when erased, high level data is applied to the first node QAb.

Next, a high level copyback signal CPBK is applied to apply data stored in the first node QAb of the first register to the first node of the second register through the sensing node.

When the high level copyback signal CPBK is applied, the NMOS transistor N138 is turned on so that data stored in the first node QAb is applied to the sensing node, which is applied to the NMOS transistor N141 of the second register. Is approved. In this case, when the corresponding cell is programmed and low level data is stored in the first node QAb, the low level data is applied to the gate of the NMOS transistor N141. However, when the corresponding cell is erased and the high level data is stored in the first node QAb, the high level data is applied to the gate of the NMOS transistor N141.

On the other hand, the second read signal READ_R is applied. Since the data applied to the gate of the NMOS transistor N141 is different depending on whether a specific cell is programmed, the second read signal READ_R is stored in the first node QBb of the second register. The data will also be different. That is, when the corresponding cell is programmed and low level data is stored in the first node QAb of the first register, low level data is applied to the gate of the NMOS transistor N141, and accordingly, the NMOS transistor N141 is provided. ) Is not turned on, so the previously stored high level data is retained.

However, when the corresponding cell is erased and the high level data is stored in the first node QAb of the first register, the high level data is applied to the gate of the NMOS transistor N141. Accordingly, the NMOS transistor N141 is applied. ) Is turned on so that the low level data is stored in the first node QBb of the second register.

Data stored in the first node QBb of the second register is inverted through the inverter IV144 and applied to the sensing node according to the input of the second program signal PGM_R to be programmed in the target cell.

Previously, when low level data is stored in the first node QBb of the second register, the low level data is inverted through the inverter IV144 and thus the high level data is stored in the sensing node, and thus the object is erased. In addition, when the high level data is stored in the first node QBb of the second register, the high level data is inverted through the inverter IV144 and the low level data is stored in the sensing node, thereby being a program target.

The above contents can be summarized as the following table.

division SO on reading QAb SO at copyback signal input QBb SO during copyback program Program cell H L L H L Erase cell L H H L H

As described above, the nonvolatile memory device performs a program, erase, read and verify operation, a copyback operation, and the like using the page buffer. At this time, the command is executed mainly in units of pages. The size of the page buffer is large, such as 512 bytes and 2 KBytes, and occupies a substantial portion of the chip. Therefore, if the number of switching elements used in the unit page buffer circuit is reduced, the size of the entire chip can be reduced.

4 is a diagram illustrating a nonvolatile memory device in which the number of switching elements used in a page buffer is reduced according to an exemplary embodiment of the present invention.

The nonvolatile memory device includes a memory cell array 410, a bit line selector 420, a first register 430, a second register 440, and a sensing node precharge unit 450.

In the nonvolatile memory device used in the present invention, the configuration of the first register 430 and the second register 440 is different.

The first register 430 is connected to a first latch 432 including two inverters IV430 and IV432 and a first node QAb of the first latch, and responds to a voltage level of the sensing node SO. And an NMOS transistor N431 that is turned on, and is connected between the NMOS transistor N431 and a ground power source and turned on in response to a first read signal READ_R.

In addition, the first register includes a first data input transistor N434, a data input / output terminal YA, and a second latch of the first latch connected between the data input / output terminal YA and the first node QAb of the first latch. A second data input transistor N435 is connected between the nodes QA. Accordingly, low level data is applied to the first node when the high level first data input signal DI_L is applied, and low level data is applied to the second node when the high level second data input signal nDI_L is applied. do.

The NMOS transistor N433 selectively connects the second node and the ground terminal in response to the first reset signal RST_L. Therefore, low level data is applied to the second node when the high level first reset signal RST_L is applied.

In addition, the PMOS transistor P431 is turned on according to the voltage level of the second node QA. The PMOS transistor P431 transfers a power supply voltage as a verification signal nWDO_L when the second node is at a low level.

On the other hand, unlike the first resistor of Figure 1 is characterized in that it does not include a copyback transistor. Except for the copyback transistor, normal copyback operation is possible. A detailed copyback operation will be described later.

In addition, the inverter IV434 inverting the data stored in the first node and transferring the data to the sensing node and the NMOS transistor N436 transferring the output signal of the inverter IV434 to the sensing node according to the first program signal PGM_L. And an NMOS transistor N437 transferring the output signal of the inverter IV434 to the input / output terminal YA according to the first output signal PBDO_L.

The second register 440 is connected to the second latch 142 including two inverters IV440 and IV442 and the first node QBb of the second latch and responds to the voltage level of the sensing node SO. And an NMOS transistor N441 that is turned on, and is connected between the NMOS transistor N441 and a ground power source and turned on in response to a second read signal READ_L.

In addition, the second register may include a first data input transistor N444 and a second input / output terminal 444 connected between the data input / output terminal YA and the first node QBb of the second latch. The second data input transistor N445 is connected between the nodes QB. Accordingly, low level data is applied to the first node when the high level first data input signal DI_R is applied, and low level data is applied to the second node when the high level second data input signal nDI_R is applied. do.

In addition, the NMOS transistor N443 selectively connects the second node and the ground terminal in response to a second reset signal RST_R. Therefore, low level data is applied to the second node when the high level second reset signal RST_R is applied.

In addition, the PMOS transistor P441 is turned on according to the voltage level of the second node QB. The PMOS transistor P441 transfers a power supply voltage as the verification signal nWDO_L when the second node QB is at a low level.

Unlike the first register, an inverter for inverting data stored in the first node QBb and transferring the data to the sensing node is not included. Therefore, the data stored in the first node QBb is transferred to the sensing node without being inverted.

In addition, the NMOS transistor N446 transferring data stored in the first node QBb to the sensing node according to the second program signal PGM_R and the data of the second node QB according to the second output signal PBDO_R. It includes an NMOS transistor (N447) for transmitting to the input and output terminal (YA).

The operation of the nonvolatile memory device will now be described.

5 is a waveform diagram illustrating various control signals applied during a program operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

First, a high level first reset signal RST_L is applied to the first register 430 to apply low level data to the second node QA.

Next, a low level precharge signal PRECHb is applied to the sensing node precharge unit 450 to precharge the sensing node to a high level.

Next, the first read signal READ_L is applied to apply the ground voltage to the first node QAb. Accordingly, low level data is stored in the first node QAb and high level data is stored in the second node QA. Through this, the first node is initialized.

Next, high level or low level data is stored in the second node QA according to the application of the first data input signal DI_L or the second data input signal nDI_L.

The data input as described above is applied to the sensing node according to the input of the first program signal PGM_L, and accordingly, whether or not the data is programmed is determined. Typically, when the low level data is stored in the second node, the low level data is applied to the sensing node to be the program target. When the high level data is stored in the second node, the high level data is also applied to the sensing node to erase the object. do.

The overall program operation is almost the same as in FIG. That is, even if there is no copyback transistor, normal program operation is possible.

6 is a waveform diagram illustrating various control signals applied during a copyback operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

First, the second register is initialized. To this end, low level data is applied to the second node QB by applying a second reset signal RST_R to the second register. Therefore, high level data is stored in the first node QBb.

Next, data stored in the first memory cell, that is, the source page, is read and applied to the sensing node. To this end, a low level precharge signal is applied to the sensing node precharge unit 450 to precharge the sensing node to a high level.

In addition, the voltage level of the cell to be read is evaluated by applying the high level first bit line selection signal BSLe. When the cell to be read is programmed, the precharged level is maintained as it is. In the case of being erased, the signal transitions to the low level.

Next, the voltage applied to the sensing node is applied to the first and second registers.

Next, the voltage applied to the first register is stored in the first register. To this end, when the first read signal READ_L is applied, low or high level data is stored in the first node QAb of the first register according to whether the corresponding cell is programmed.

When the cell is programmed, low level data is applied to the first node QAb, and when erased, high level data is maintained as it is at the first node QAb.

Next, the voltage applied to the second register is stored in the second register.

In the present invention, instead of using the copyback transistor, a copyback operation is performed using data applied to the sensing node.

As a result of performing the above operation, high level or low level data is applied to the sensing node according to whether the corresponding cell is programmed and stored in the second register.

To this end, the second read signal READ_R is applied to the second register. The data applied to the sensing node is changed according to whether or not a specific cell is programmed, and thus is applied to the gate of the NMOS transistor N441. Since the data is different, the data stored in the first node QBb of the second register is also different. That is, when the corresponding cell is programmed and a high level voltage is applied to the sensing node, a high level voltage is applied to the gate of the NMOS transistor N441, and accordingly, the NMOS transistor N441 is turned on so that the ground voltage is increased. Is applied to the first node QBb.

However, when the corresponding cell is erased and a low level voltage is applied to the sensing node, a low level voltage is applied to the gate of the NMOS transistor N441, and accordingly, the NMOS transistor N441 is not turned on. The high level data stored in the first node QBb of the register is retained.

Next, the voltage stored at the first node of the second register is applied to the sensing node. To this end, the high level second program signal PGM_R is input and data stored in the first node QBb is directly applied to the sensing node. The copyback program operation is performed according to the voltage level applied to the sensing node. That is, when the low level voltage is applied to the sensing node, the corresponding cell is the program target, and when the high level voltage is applied to the sensing node, the cell is the erasing target.

The above process is summarized as follows.

division SO when copyback is read QAb SO during copyback program Program cell H L L Erase cell L H H

Next, a second memory cell, that is, a target memory cell, is programmed according to the voltage applied from the first node to the sensing node.

In this manner, data stored in the first memory cell is programmed as it is in the second memory cell.

1 is a circuit diagram illustrating a conventional nonvolatile memory device.

2 is a waveform diagram illustrating various control signals applied during a program operation of the conventional nonvolatile memory device.

3 is a waveform diagram illustrating various control signals applied during a copyback operation of the conventional nonvolatile memory device.

4 is a diagram illustrating a nonvolatile memory device in which the number of switching elements used in a page buffer is reduced according to an exemplary embodiment of the present invention.

5 is a waveform diagram illustrating various control signals applied during a program operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

6 is a waveform diagram illustrating various control signals applied during a copyback operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

Claims (3)

Reading and applying data of the first memory cell to the sensing node; Applying a voltage applied to the sensing node to first and second registers; Storing a high level or low level voltage in a first node of the second register according to a voltage applied to the second register; Applying a voltage stored at a first node of the second register to the sensing node; And programming a second memory cell according to a voltage applied from the first node to the sensing node. The copy of the nonvolatile memory device of claim 1, wherein applying the voltage stored at the first node of the second register to the sensing node comprises applying a second program signal of a high level. One hundred program method. The method of claim 1, wherein the applying of the voltage stored at the first node of the second register to the sensing node maintains the voltage level stored at the first node as it is to be applied to the sensing node. How to program a copyback of a volatile memory device.
KR1020070076283A 2007-07-30 2007-07-30 Method for copyback programming non volatile memory device KR20090012458A (en)

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