KR20090007979A - Method of forming pattern of semiconductor device - Google Patents

Abstract

A pattern formation method of a semiconductor device is provided to use a dual mask pattern having different widths, thereby forming a pattern of a line width narrower than a resolution of an exposure process and reducing a pitch of the pattern. A first mask pattern having a first width on a base film(110) formed on a substrate(100) is formed. A surface film(150) is formed in the surface of the first mask pattern. A second mark pattern(140) having a second width as being covered by the surface film is formed. The surface film is removed. The base film is etched by using a mask pattern having the second width. The second width is smaller than the first width. The first mask pattern and the second mask pattern comprise polysilicon. The surface film comprises oxide. The mask pattern is formed by oxidizing the surface of the first mask pattern.

Description

Pattern Forming Method of Semiconductor Device {METHOD OF FORMING PATTERN OF SEMICONDUCTOR DEVICE}

1 to 4 are cross-sectional views illustrating a method of forming a pattern of a semiconductor device in accordance with a first embodiment of the present invention.

5 to 9 are cross-sectional views illustrating a method of forming a pattern of a semiconductor device in accordance with a second embodiment of the present invention.

10 to 15 are cross-sectional views illustrating a method of forming a pattern of a semiconductor device in accordance with a third embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100, 200: semiconductor substrate 110, 210: base film

115, 215: objective pattern 120, 220: lower mask film

125, 225: lower mask pattern 130: first mask pattern

135, 235: spacer film 137: compensation film

140: second mask pattern 144: third mask pattern

146: etching mask pattern 150, 250: surface film

233: first sub mask pattern 236: second sub mask pattern

240: mask pattern

The present invention relates to a method for forming a pattern of a semiconductor device, and more particularly to a method for forming a pattern of a semiconductor device that can reduce the line width.

As the electronic industry develops, high integration semiconductor devices are required to manufacture high-capacity, ultra-high speed electronic devices. In order to highly integrate semiconductor devices, design rules of semiconductor devices are decreasing. That is, in order to form many elements in a narrow area, the pitch which is the width | variety of the formed pattern and the space | interval between patterns becomes narrow.

The pattern may be formed by a photolithography process. However, there is a limit in the photolithography process in order to form a fine pattern because the design rule of the semiconductor device is drastically reduced.

In order to overcome the limitations of the photolithography process, a pattern formation method for performing a double exposure process has been proposed. This is to perform a photolithography process twice to form a series of patterns. First, a first hard mask film and a second hard mask film are sequentially formed on the base film. A first mask pattern is formed on the first hard mask layer by performing a patterning process on the second hard mask using a first photolithography process. Subsequently, a second mask pattern is formed between the first mask patterns by performing a patterning process on the first hard mask layer using a second photolithography process. A fine pattern may be formed by performing an etching process on the base layer using the first and second mask patterns.

However, the process also has a limitation in forming an ultrafine pattern having a width of less than 40 nm. If two exposure processes are performed, problems may occur in the alignment of the first exposure process and the second exposure process. For example, the inter-pattern spacing may be non-uniform due to misalignment, and an inter-pattern bridge may be formed. If the spacing between the patterns is nonuniform, the repeated cells may have different characteristics, which may cause device malfunction. When the inter-pattern bridge is formed, adjacent patterns connected by the bridge may be shorted to cause malfunction of the device.

In addition, as the line width of the pattern becomes fine, the profile of the pattern may not be uniformly formed. Therefore, it may cause a defect of the semiconductor device to reduce the reliability of the device, it may be difficult to reduce the design rule.

Accordingly, an object of the present invention for solving the above problems is to provide a method of forming a pattern of a semiconductor device that can achieve high integration.

According to another aspect of the present invention, there is provided a method of forming a pattern of a semiconductor device, the method including: forming a first mask pattern having a first width on a base film formed on a substrate; Forming a surface layer to form a second mask pattern in contact with the surface layer and having a second width, removing the surface layer, and etching the base layer using the mask pattern having the second width; Can be.

In example embodiments, the second width may be smaller than the first width.

According to another embodiment, the method may further include forming a lower mask layer on the base layer.

In example embodiments, the first mask pattern and the second mask pattern may include polysilicon, and the surface layer may include an oxide.

According to another embodiment, the forming of the second mask pattern may include oxidizing a surface of the first mask pattern.

According to another embodiment, the step of oxidizing may include a thermal oxidation process using oxygen gas.

According to another embodiment, the method may include conformally forming a spacer layer on the second mask pattern and the base layer after removing the surface layer, and the second mask pattern adjacent to and adjacent to the spacer layer. The method may further include forming a third mask pattern interposed therebetween and removing the spacer layer exposed between the second mask pattern and the third mask pattern.

According to another embodiment, the second mask pattern and the third mask pattern may have the same width.

In example embodiments, the forming of the third mask pattern may include forming a mask layer on the spacer layer and planarizing the mask layer to expose the spacer layer on the second mask pattern. have.

The forming of the first mask pattern may include forming a first mask layer on the base layer, patterning the first mask layer to form a first sub mask pattern, and forming the first mask pattern. Conformally forming a spacer film on the sub mask pattern and the base film, forming a second sub mask pattern in contact with the spacer film and interposed between the adjacent first sub mask patterns and the first sub mask The method may include removing the spacer layer exposed between the pattern and the second sub mask pattern.

In example embodiments, the forming of the second sub mask pattern may include forming a second mask layer on the spacer layer and planarizing the second mask layer to expose the spacer layer on the first sub mask pattern. It may include a step.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following examples and can be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Elements of the same reference number may be used singularly or plurally.

1 to 4, a method of forming a pattern of a semiconductor device according to a first embodiment of the present invention will be described.

Referring to FIG. 1, a base film 110 may be formed on a semiconductor substrate 100. For example, the base layer 110 may include a metal material and / or an insulating material. A lower mask layer 120 may be further formed on the base layer 110. A first mask layer (not shown) may be formed on the lower mask layer 120. For example, the first mask layer may include polysilicon. By patterning the first mask layer, a first mask pattern 130 having a first width w1 may be formed. For example, a photolithography process may be performed to pattern the first mask layer. The photolithography process may include forming a photoresist film on the first mask film, selectively exposing and developing the photoresist film, and using the photoresist pattern thus formed to form the first mask. The film can be etched. The first width w1 may be a minimum line width that can be achieved in the exposure process.

Referring to FIG. 2, an oxidation process may be performed on the first mask pattern 130. For example, the oxidation process may be a thermal oxidation process using oxygen gas. When the oxidation process is performed, the silicon oxide film may be grown in the outward and inward directions of the surface of the first mask pattern 130. That is, the surface of the first mask pattern 130 is oxidized to form a second mask pattern 140 made of polysilicon and a surface film 150 made of silicon oxide surrounding the surface of the second mask pattern 140. Can be formed. The second mask pattern 140 may have a second width w2 that is narrower than the first width w1.

During the oxidation process, oxidation of the base layer 110 may be prevented by the lower mask layer 120. Alternatively, the lower mask layer 120 may not be formed when an easily removable oxide film may be formed on the surface of the lower layer during the oxidation process. For example, the lower mask layer 120 may include an oxide layer.

Referring to FIG. 3, the surface film 150 may be removed. When the etching process is performed using the second mask pattern 140, the surface layer 150 may be removed.

For example, the etching process may be an isotropic etching or anisotropic etching process. Alternatively, the etching process may include both isotropic etching and anisotropic etching. For example, when isotropic etching is performed, the surface layer 150 may be removed and the second mask pattern 140 may be exposed. The lower mask layer 120 may be partially eroded depending on the etching selectivity. Thereafter, the lower mask pattern 125 may be formed by anisotropically etching the lower mask layer 120 using the second mask pattern 140. As described above, when the lower mask layer 120 is not formed, an oxide layer that may be formed on the surface layer 150 and the base layer 110 may be selectively removed.

Referring to FIG. 4, the base layer 110 may be etched using the second mask pattern 140 and the lower mask pattern 125. Alternatively, after removing the second mask pattern 140, the base layer 110 may be etched using the lower mask pattern 125. Therefore, the target pattern 115 having the second width w2 may be formed. The target pattern 115 may be a word line, a bit line, or another wiring.

Thus, even if a pattern having a narrow width cannot be formed in the photolithography process, a pattern having an improved resolution can be formed by the oxidation process.

5 to 9, a method of forming a pattern of a semiconductor device according to a second embodiment of the present invention will be described. Hereinafter, the same content as described above is omitted.

Referring to FIG. 5, in the resultant product of FIG. 2, the surface film 150 may be removed. Subsequently, an exposed region of the lower mask layer 120 may be recessed by performing a recess process. The pattern to be subsequently formed and the position of the second mask pattern 140 may be adjusted by the recess process. This will be described later.

Referring to FIG. 6, a spacer layer 135 may be formed on the second mask pattern 140 and the lower mask layer 120. The spacer layer 135 may be conformally formed. For example, the spacer layer 135 may be an oxide layer and may be formed by a chemical vapor deposition (CVD) method. The thickness of the spacer layer 135 may be adjusted in consideration of the recessed depth of the lower mask layer 120 and the gap between the second mask patterns 140.

A second mask layer (not shown) may be formed on the spacer layer 135. The second mask layer may include polysilicon as in the second mask pattern 140. The third mask pattern 144 may be formed by performing a planarization process on the second mask layer. The planarization process may be performed to expose the spacer layer 135 on the second mask pattern 140. The third mask pattern 144 may have a second width like the second mask pattern 140. In addition, the bottom surface of the third mask pattern 144 may be at the same height as the bottom surface of the third mask pattern 140. As described above, the position where the third mask pattern 144 is formed may be determined by the recess of the lower mask layer 120 and the thickness of the spacer layer 135.

6 and 7, the height of the third mask pattern 144 may be higher than the second mask pattern 140 by the thickness of the spacer layer 135. The third mask pattern 144 may be recessed to have the same height as the second mask pattern 140. As a result, the etching mask patterns 146 may be formed. Alternatively, the third mask pattern 144 may be used without being recessed.

The spacer layer 135 interposed between the etching mask patterns 146 may be removed. The spacer layer 135 may be removed by an etching process having a higher etching selectivity with respect to the spacer layer 135 than the etching mask patterns 146. The etching process may be performed to expose all sides of the etching mask patterns 146. The recessed region of the lower mask layer 120 may be compensated by the remaining spacer layer 135 by the etching process, thereby forming a compensation layer 137.

For example, when the first mask patterns 130 (refer to FIG. 1) are formed at a first interval, the etch mask patterns 146 may be formed at a second interval narrower than the first interval.

Referring to FIG. 8, the compensation layer 137 may be selectively etched using the etching mask patterns 146. As a result, the lower mask pattern 125 may be formed.

Referring to FIG. 9, the base layer 110 may be etched using the etching mask patterns 146 and the lower mask pattern 125. Alternatively, after the etching mask patterns 146 are removed, the base layer 110 may be etched using the lower mask pattern 125. As a result, an object pattern 115 having the second width w2 may be formed. The target pattern 115 may be formed to have a narrower line width and spacing than the line width and spacing between patterns that can be achieved in the exposure process.

10 to 15, a method of forming a pattern of a semiconductor device according to a third embodiment of the present invention will be described. The same content as described above is briefly described.

Referring to FIG. 10, the base layer 210 and the lower mask layer 220 may be sequentially formed on the semiconductor substrate 200. A first sub mask pattern 233 having a first width w1 and including polysilicon may be formed on the lower mask layer 220 by a photolithography process. The lower mask layer 220 may be partially recessed.

Referring to FIG. 11, a spacer layer 235 may be conformally formed on the top and sidewalls of the first sub mask pattern 233 and the lower mask layer 220. A second sub mask pattern 236 including polysilicon may be formed between the adjacent first sub mask patterns 233. The second sub mask pattern 236 may be spaced apart from the first sub mask pattern 233 by the spacer layer 235. The second sub mask pattern 236 may be formed through a mask layer (not shown) forming process and a planarization process for the mask layer.

 The second sub mask pattern 236 may have a first width like the first sub mask pattern 233. In addition, the bottom surface of the second sub mask pattern 236 may be at the same height as the bottom surface of the first sub mask pattern 233.

Referring to FIG. 12, the second sub mask pattern 236 may be recessed so that the second sub mask pattern 236 and the first sub mask pattern 233 have the same height. The spacer layer 235 interposed between the first sub mask pattern 233 and the second sub mask pattern 236 may be removed to expose side surfaces of the sub mask patterns 233 and 236. have. As a result, a compensation layer 237 including the lower mask layer 220 and the remaining spacer layer 235 may be formed.

Referring to FIG. 13, a thermal oxidation process is performed on the first sub mask pattern 233 and the second sub mask pattern 236, so that the surfaces of the sub mask patterns 233 and 236 are formed. The silicon oxide film may be grown in the outward and inward directions. Accordingly, a mask pattern 240 having a second width w2 narrower than the first width w1 and a surface layer 250 including silicon oxide may be formed on the mask pattern 240 surface.

Referring to FIG. 14, the surface layer 250 and the compensation layer 237 may be selectively etched using the mask pattern 240. As a result, the lower mask pattern 225 may be formed.

Referring to FIG. 15, the base layer 210 may be etched using the mask pattern 240 and the lower mask pattern 225. As a result, the target pattern 215 having the second width w2 may be formed.

According to the method for forming a pattern of a semiconductor device according to an embodiment of the present invention, a pattern having a fine line width narrower than the resolution of an exposure process may be formed. In addition, according to the method for forming a pattern of a semiconductor device according to another embodiment of the present invention, the pitch of the pattern may be reduced. In addition, according to the method for forming a pattern of a semiconductor device according to another embodiment of the present invention, fine patterns may be formed at narrower intervals. Therefore, high integration of the semiconductor element can be achieved.

Claims (11)

Forming a first mask pattern having a first width on a base film formed on the substrate; Forming a surface layer on the surface of the first mask pattern to cover the surface layer and form a second mask pattern having a second width; Removing the surface film; And And etching the base layer using the mask pattern having the second width. The method of claim 1, And the second width is narrower than the first width. The method of claim 1, And forming a lower mask layer on the base layer. The method of claim 1, And the first mask pattern and the second mask pattern include polysilicon, and the surface layer includes an oxide. The method of claim 4, wherein Forming the second mask pattern is: And oxidizing a surface of the first mask pattern. The method of claim 5, wherein The oxidizing step is: A method of forming a pattern in a semiconductor device, comprising thermal oxidation using oxygen gas. The method of claim 5, wherein After removing the surface film, Conformally forming a spacer layer on the second mask pattern and the base layer; Forming a third mask pattern in contact with the spacer layer and interposed between adjacent second mask patterns; And And removing the spacer film exposed between the second mask pattern and the third mask pattern. The method of claim 7, wherein And the second mask pattern and the third mask pattern have the same width. The method of claim 7, wherein Forming the third mask pattern is: Forming a mask film on the spacer film; And Planarizing the mask film to expose the spacer film on the second mask pattern. The method of claim 5, wherein Forming the first mask pattern is: Forming a first mask film on the base film; Patterning the first mask layer to form a first sub mask pattern; Conformally forming a spacer layer on the first sub mask pattern and the base layer; Forming a second sub mask pattern in contact with the spacer layer and interposed between adjacent first sub mask patterns; And And removing the spacer film exposed between the first sub mask pattern and the second sub mask pattern. The method of claim 10, The forming of the second sub mask pattern may include: Forming a second mask film on the spacer film; And And planarizing the second mask film to expose the spacer film on the first sub mask pattern.

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