KR20090003717A - Nand flash memory device, structure and fabricating method the same - Google Patents

Abstract

A NAND flash memory device is provided to reduce the number of serially connected memory cells to the half in one string, so reducing the channel length. A first string comprises a first drain selecting transistor(DSTo), a first group memory cell transistor(the MC0 o or the MC15 o) and source select transistor(SSTo). The first drain selecting transistor is serially connected between the common bit line(BL0) and common source line. The second string comprises a second drain selection transistor(DSTe), a second group memory cell transistor(the MC0 e or the MC15 e) and the second source select transistor(SSTe). The second drain selection transistor is serially connected between the common bit line and common source line.

Description

NAND flash memory device, structure and manufacturing method {NAND FLASH MEMORY DEVICE, STRUCTURE AND FABRICATING METHOD THE SAME}

The present invention relates to semiconductor technology, and more particularly, to a NAND flash memory device.

Semiconductor memory devices, such as DRAM and SRAM, are volatile and fast data input / output devices that lose data over time, and can be maintained once data is input. It can be divided into ROM products.

Among these ROM products, there is a growing demand for flash memory devices capable of electrically inputting and outputting data.

Flash memory devices are classified into NOR and NAND types, which require one contact per two cells and are disadvantageous for high integration, but have advantages of high speed due to large cell current. Although the cell current is low, it is disadvantageous for high speed, but has the advantage that a plurality of cells share one contact, which is advantageous for high integration. Therefore, NAND flash memory devices have recently been in the spotlight as next generation memory devices, such as those used in MP3s, digital cameras and the like.

1 is a circuit diagram showing a NAND flash memory device according to the prior art, Figure 2 is a view showing the structure of the NAND flash memory device according to the prior art, (a) is a plan view, (b) is (a) Is a cross-sectional view taken along the line II ', and (c) is a cross-sectional view taken along the line II-II'.

As shown in FIGS. 1 and 2, the NAND flash memory cell array includes a drain select transistor (DST) connected to a bit line and a source connected to a common source line. The source select transistor (SST) and 32 memory cell transistors MC0 to MC31 are connected in series to form a string.

The transistors SST, MC0 to MC31, and DST are arranged in a matrix form of rows and columns, and the gates of the drain select transistors DST and the source select transistors SST arranged in the same columns are respectively drain select lines. (Drain Select Line, DSL) and source select line (Source Select Line, SSL). In addition, the gates of the memory cell transistors MC0 to MC31 arranged in the same column are connected to the corresponding word lines WL0 to WL31.

The drains of the drain select transistors DST arranged in the same column are connected to the corresponding bit lines BL0, BL1, BL2, ..., respectively, and the source of the source select transistors SST arranged in the same column is a common source line. (CSL).

The memory cell transistors MC0 to MC31 may include a floating gate 13 formed through the tunneling insulating layer 12 on the substrate 10 and a control gate formed through the dielectric layer 14 on the floating gate 13. (15) has a laminated structure. The floating gate 13 is formed over the active line and a portion of the edge of the device isolation layer 11 on both sides thereof to be isolated from the floating gate 13 of the neighboring memory cell transistor. The control gate 15 includes a floating gate 13 independently formed with the device isolation layer 11 interposed therebetween to be connected to the control gate 15 of a neighboring memory cell transistor to form a word line.

Since the select transistors DST and SST are transistors that do not require a floating gate to store data, some or all of the dielectric film 14 between the floating gate 13 and the control gate 15 is removed, thereby electrically 1. It acts as a MOS transistor with a gate of layers.

A first interlayer insulating layer 16 is formed on the substrate 10 on which the memory cell transistors MC0 to MC31 are formed, and a source of the source select transistor SST is formed on the first interlayer insulating layer 16. A source contact 17 is formed for connection to. A second interlayer insulating film 18 is formed on the first interlayer insulating film 16 including the source contact 17, and a drain of the drain select transistor DST is formed on the second and first interlayer insulating films 18 and 16. A bit line contact 19 is formed to be connected to the bit line, and a bit line BL connected to the bit line contact 19 is formed on the second interlayer insulating layer 18 on the active line.

The NAND flash memory device according to the related art has the following problems.

First, when all 32 memory cell transistors MC0 to MC31 are programmed, the channel resistance becomes very large.

If the channel resistance increases, the BPD (Back Pattern Dependancy) is not negligible so that the threshold voltage Vt of the program cell is different for each of the word lines WL0 to WL31, thereby increasing the threshold voltage distribution of the memory cell.

In addition, as the channel resistance increases, the on current is reduced, thereby deteriorating cycling characteristics and data retention characteristics.

Second, since the bit lines are formed in the same number as the active lines, the bit lines also follow the minimum design rule. As a result, reduced technology reduces the line and space widths of the bit lines, increases the bit line resistance, increases the capacitance between neighboring bit lines, and increases the RC delay. Will be.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a NAND flash memory device capable of reducing channel resistance and reducing bit line RC delay, a structure thereof, and a manufacturing method thereof.

According to an aspect of the present invention, a first string includes a first drain select transistor, a first group memory cell, and a first source select transistor connected in series between a bit line and a common source line. And the second drain select transistor, the second group memory cells, and the second source select transistors corresponding to the first drain select transistor, the first group memory cells, and the first source select transistor. A second string configured to be connected in series between a common source line, wherein a gate of the first drain select transistor and a gate of the second drain select transistor are connected to different first and second signal lines, respectively; The first string and the second switch according to electrical signals applied to first and second signal lines. Provides a NAND flash memory device of the ring is independently selected.

According to another aspect of the present invention, there is provided a substrate on which first and second active lines are formed in pairs and arranged in parallel, and a first portion formed on a portion of the first and second active lines. And a second drain contact region, word lines and source selection lines formed on the substrate to cross the first and second active lines, and the word line and the first and second drain contact regions between the word lines and the first and second drain contact regions. First and second drain select gates formed on first and second active lines, a first interlayer insulating film covering the word lines, source select lines, and the first and second drain select gates, and the first interlayer First and second contacts penetrating the insulating film and connected to the first and second drain selection gates, respectively, and third and second penetrating through the first interlayer insulating film and connected to the first and second drain contact regions, respectively. 4 cones And first and second signal lines formed on the first interlayer insulating film and connected to the first and second contacts, respectively, and formed on the first interlayer insulating film and forming the third contact and the fourth contact. A conductive line to be connected, a second interlayer insulating film covering the first and second signal lines and the conductive line, a fifth contact connected to the conductive line through the second interlayer insulating film, and on the second interlayer insulating film The structure of the NAND flash memory device includes a bit line connected to the fifth contact.

According to still another aspect of the present invention, there is provided a drain select line, word lines, and a plurality of intersecting first and second active lines on a substrate on which paired first and second active lines are formed. Forming a source select line, forming first and second drain contact regions in the first and second active lines on one side of the drain select line, and patterning the drain select line to form the first and second Forming first and second drain select gates on an active line, forming a first interlayer insulating film on the resultant, and penetrating the first interlayer insulating film to pass through the first and second drain select gates Forming first and second contacts connected to the first and second contacts and the third and fourth contacts connected to the first and second drain contact regions, and forming the first and second contacts on the first interlayer insulating film.Forming first and second signal lines connected to each other, a conductive line connecting the third contact and the fourth contact, forming a second interlayer insulating film on the resultant, and forming the second interlayer Forming a fifth contact penetrating the insulating film to be connected to the conductive line; and forming a bit line on the second interlayer insulating film including the fifth contact. do.

According to the present invention, the following effects are obtained.

First, the channel length can be reduced by reducing the number of memory cells connected in series to one string in half, thereby lowering the channel resistance.

Accordingly, since the BPD (Back Pattern Dependancy) is reduced and the on current is improved, the threshold voltage distribution of the memory cell can be reduced, and the cycling characteristics and the data retention characteristics can be improved.

Second, since one bit line is formed per two active lines, the line and space widths of the bit lines can be increased, thereby reducing bit line resistance and inter / capacitance, thereby reducing bit line RC delay.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

3 is a circuit diagram illustrating a NAND flash memory device according to an embodiment of the present invention.

As shown in FIG. 3, in the NAND flash memory device according to the present invention, 32 memory cell transistors, which are conventionally connected in series to one string, are divided into two strings, and 16 memory cell transistors in each string are connected in series. The two strings form a pair to share one bit line.

For example, if the shared bit line is BL0, any one of the two strings in the pair is the first drain select transistor DSTo connected in series between BL0 and the common source line CSL. The second drain select transistor DSTe includes the first group memory cell transistors MC0_o to MC15_o and the source select transistor SSTo, and the other string is connected in series between BL0 and the common source line CSL. ), Sixteen second group memory cell transistors MC0_e to MC15_e and a second source select transistor SSTe.

Here, the second drain select transistor DSTe, the second group memory cell transistors MC0_e to MC15_e and the second source select transistor SSTe are respectively the first drain select transistor DSTo and the first group memory cell transistors. Corresponding to (MC0_o to MC15_o) and the source select transistor SSTo, they are arranged in the same column.

The first and second source select transistors SSTo and SSTe arranged in the same column share one gate line (hereinafter, referred to as a source select line) SSL, and include the first group memory cell transistors MC0_o through. The MC15_o and the second group memory cell transistors MC0_e to MC0_e are arranged in the same column with each other and share a word line.

Meanwhile, the first and second drain select transistors DSTo and DSTe are connected to different gate lines. That is, the first drain select transistor DSTo is connected to a first gate line (hereinafter referred to as a 'first drain select line', DSLo), and the second drain select transistor DSTe is connected to a second gate line (hereinafter, referred to as “drain”). Is referred to as a 'second drain select line', DSLe).

Therefore, the first and second drain select transistors DSTo and DSTe are individually turned on according to electrical signals (voltage values) applied to the first and second drain select lines DSLo and DSLe. The selection / non-selection of the string is determined according to whether the drain selection transistors DSTo and DSTe are turned on.

A structure and a manufacturing method of a NAND flash memory device according to an embodiment of the present invention having such a circuit configuration will be described below with reference to FIGS. 4 to 7.

4 to 7 are views for explaining a method of manufacturing a NAND flash memory device according to an embodiment of the present invention, (a) is a plan view, and (b) is a cut along the line II ′ of FIG. (C) is sectional drawing which cut (a) along the II-II 'line, (d) is sectional drawing which cut (a) along the III-III' line.

First, as shown in (a), (b) and (c) of FIG. 4, an isolation line 41 arranged in one direction is formed on the substrate 40 to define an active line 40A. The source select line SSL, the word lines WL0 to WL15, and the drain select line DSL are formed on the 40, which crosses the active line 40A. The number of lines of the active lines 40A is preferably formed in even numbers so that two can be paired.

The word lines WL0 to WL15 have a structure in which a tunneling insulating layer 42, a floating gate 43, a dielectric layer 44, and a control gate 45 are stacked on the substrate 40, and a source selection line ( The SSL and the drain select line DSL are formed by removing some or all of the dielectric film 44 between the floating gate 43 and the control gate 45 when the word lines WL0 to WL15 are formed.

Next, a drain contact region (not shown) is formed in the active line 40A on one side of the drain select line DSL opposite to the word line WL15 and the source select line SSL opposite to the word line WL0. A source contact region (not shown) is formed in the active line 40A on the other side.

Subsequently, as illustrated in FIGS. 5A, 5B, and 5C, the drain select line DSL is patterned so that the drain select line DSL is separated from the device isolation layer 41, and the active line 40A) and drain select gates DSGo and DSGe in the form of isolated islands are formed on a predetermined portion of the device isolation layer 41 adjacent thereto.

Here, the drain select gate DSGo represents a drain select gate (hereinafter, referred to as a “first drain select gate”) formed over the odd-numbered active line 40A, and the drain select gate DSGe represents an even-numbered active line. A drain select gate (hereinafter referred to as a “second drain select gate”) formed over the 40A is shown.

Subsequently, the first interlayer insulating layer 46 is formed on the entire structure, and contact holes exposing the drain contact regions and the first and second drain select gates DSGo and DSGe, and the source contact regions are exposed. A trench is formed, and a conductive film is filled in the contact holes and the trench, and the first and second contacts 47A and 47B and the drain contact regions connected to the first and second drain select gates DSGo and DSGe are formed. The third and fourth contacts 48A and 48B connected to each other and the common source line CSL 49 connected to the source contact regions are formed.

At this time, the first contacts 47A and the second contacts are positioned such that the first contacts 47A are located on one line and the second contacts 47B are located on the other line parallel to the line. It is preferable to lay out 47B in a zigzag form.

Subsequently, as shown in FIGS. 6A, 6B, 6C, and 6D, a conductive film is formed and patterned on the entire surface on which the first to fourth contacts 47A, 47B, 48A, and 48B are formed. Conductive line 50 connecting the adjacent third and fourth contacts 48A and 28B, the first signal line 51A connecting the first drain selection gate 47A, and the second drain selection A second signal line 51B connecting the gates 47B is formed.

Subsequently, as illustrated in FIGS. 7A, 7B, 7C, and 7D, the front surface including the conductive film line 50 and the first and second signal lines 51A and 51B may be formed. A second interlayer insulating film 52 is formed, and a fifth contact 53 connected to the conductive film line 50 is formed through the second interlayer insulating film 52.

At this time, the fifth contact 53 is disposed on the device isolation line 41 between the active lines 40A which are paired to have the same electrical distance as that of the third contact 48A and the fourth contact 48B. Layout is preferred.

Subsequently, a bit line BL is formed on the device isolation line 41 on the second interlayer insulating layer 52 including the fifth contact 53.

Therefore, two active lines 40A adjacent to each other are connected to one bit line BL through the third and fourth contacts 48A and 48B, the conductive film line 50 and the fifth contact 53. Connected, the two strings share a single bit line BL.

When the NAND flash memory device is configured as described above, the number of memory cell transistors connected in series to a single string is reduced from 32 to 16, thereby reducing the channel resistance by half the channel length.

In addition, since one bit line BL is formed per two active lines 40A, the design rule of the bit line BL is twice the size of the minimum design rule. Therefore, it is possible to increase the line and space width of the bit line BL.

In the above description, only the number of memory cell transistors included in the unit string has been described.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a circuit diagram showing a NAND flash memory device according to the prior art.

2A to 2C are views showing the structure of a NAND flash memory device according to the prior art.

3 is a circuit diagram illustrating a NAND flash memory device according to an embodiment of the present invention.

4 (a), (b), (c) to (a), (b), (c), and (d) of FIGS. 4A to 7D illustrate a NAND flash memory device according to an embodiment of the present invention according to a process flow. Figures shown.

<Explanation of symbols for main parts of drawing>

DSLo, DSLe: first and second signal lines

WL0 to WL15: word lines

SSL: source select line

CSL: Common Source Line

DSTo, DSTe: first and second drain select transistors

MC0_o to MC15_o: first group memory cell transistors

MC0_e to MC15_e: second group memory cell transistors

SSTo, SSTe: first and second source select transistors

Claims (10)

A first string comprising a first drain select transistor, first group memory cells, and a first source select transistor connected in series between a bit line and a common source line; The first drain select transistor, the first group memory cells, and the second drain select transistor, the second group memory cells, and the second source select transistor corresponding to the first source select transistor are the bit line and the common source. A second string configured in series between the lines, A gate of the first drain select transistor and a gate of the second drain select transistor are connected to different first and second signal lines, respectively, and the first and second signal lines are connected to each other according to an electrical signal applied to the first and second signal lines. And a second string and the second string are individually selected. The method of claim 1, The NAND flash memory device in which the first group memory cells and the second group memory cells share a word line between memory cells corresponding to each other. The method of claim 1, The NAND flash memory device of claim 1, wherein the first source select transistor and the second source select transistor share one gate. A substrate on which first and second active lines are formed in pairs and arranged in parallel; First and second drain contact regions formed in predetermined portions of the first and second active lines; Word lines and source selection lines formed on the substrate to cross the first and second active lines; First and second drain select gates formed on the first and second active lines between the word lines and the first and second drain contact regions; A first interlayer insulating layer covering the word lines, the source select line, and the first and second drain select gates; First and second contacts connected to the first and second drain selection gates, respectively, through the first interlayer insulating film; Third and fourth contacts connected to the first and second drain contact regions through the first interlayer insulating film; First and second signal lines formed on the first interlayer insulating film and connected to the first and second contacts, respectively; A conductive line formed on the first interlayer insulating film and connecting the third contact and the fourth contact; A second interlayer insulating film covering the first and second signal lines and the conductive line; A fifth contact connected to the conductive line through the second interlayer insulating film; And a bit line formed on the second interlayer insulating layer and connected to the fifth contact. The method of claim 4, wherein And structure the first and second signal lines in parallel with the word lines and the source select line. The method of claim 4, wherein And a structure of the NAND flash memory device configured to parallel the bit line to the active line. The method of claim 4, wherein And disposing the fifth contact between the first active line and the second active line. Forming drain select lines, word lines, and source select lines across the first and second active lines on a substrate having paired first and second active lines formed thereon; Forming first and second drain contact regions on the first and second active lines on one side of the drain select line; Patterning the drain select line to form first and second drain select gates on the first and second active lines; Forming a first interlayer insulating film on the resultant product; Forming first and second contacts connected to the first and second drain select gates through the first interlayer insulating film and third and fourth contacts connected to the first and second drain contact regions; Forming first and second signal lines connected to the first and second contacts, respectively, and a conductive line connecting the third contact and the fourth contact on the first interlayer insulating film; Forming a second interlayer insulating film on the resultant product; Forming a fifth contact penetrating the second interlayer insulating film and connected to the conductive line; Forming a bit line on the second interlayer dielectric layer including the fifth contact Method of manufacturing a NAND flash memory device comprising a. The method of claim 8, And forming first and second source contact regions in the first and second active lines on the other side of the source select line when the first and second drain contact regions are formed. The method of claim 9, And forming a common source line connected to the first source contact region and the second source contact region when the first to fourth contacts are formed.

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