KR20070103200A - Nand flash memory device and maunfacutring method thereof - Google Patents

Abstract

A NAND flash memory device and a manufacturing method thereof are provided to secure a short margin by preventing a bridge between a drain contact plug and a drain contact plug. A NAND flash memory device includes a plurality of cell strings(201,202,203,204), drain selection transistors (210,212,214,216), and source selection transistors(220,222,224,226). A plurality of cells is serially connected in the cell strings(201,202,203,204). The drain selection transistors(210,212,214,216) are disposed between respective cell strings(201,202,203,204) and respective bit lines. The source selection transistors(220,222,224,226) are provided between the respective cell strings(201,202,203,204) and respective common source lines. The respective drain selection transistors(210,212,214,216) and source selection transistors(220,222,224,226) formed at upper and lower portions of the cell strings(201,202,203,204) are disposed in an opposite position of the drain selection transistors(210,212,214,216) and the source selection transistors(220,222,224,226) formed at upper and lower portions of the adjacent cell strings(201,202,203,204).

Description

NAND flash memory device and its manufacturing method {NAND flash memory device and maunfacutring method

1 is a layout diagram of a general NAND flash memory device.

2 is a circuit diagram of a general flash memory device.

3 is a cross-sectional view taken along the line A-A of FIG. 1 to show a problem occurring when a general drain contact plug is formed.

4 is a layout diagram of a NAND flash memory device according to an embodiment of the present invention.

5 is a circuit diagram of a NAND flash memory device according to an embodiment of the present invention.

6A to 6C are cross-sectional views illustrating a manufacturing method in a state of cutting line B-B of FIG. 4.

7A to 7C are cross-sectional views illustrating a manufacturing method in a state of cutting line C-C of FIG. 4.

8A to 8C are cross-sectional views illustrating a manufacturing method in a state of cutting the line D-D of FIG. 4.

<Description of the symbols for the main parts of the drawings>

300 semiconductor substrate 302 first interlayer insulating film

304: source contact hole 306: source contact plug

308: Second interlayer insulating film 310: Drain contact hole

312: drain contact plug 330: cell

340: drain select transistor 350: source select transistor

201, 202, 203, 204: cell string

210, 212, 214, 216: drain select transistor

220, 222, 224, 226; Source select transistor

The present invention relates to a NAND flash memory device and a method of manufacturing the same, and more particularly, to a NAND flash memory device for securing a short margin between the drain contact plug and the drain contact plug.

1 is a layout diagram of a general NAND flash memory device, and FIG. 2 is a circuit diagram thereof.

1 and 2, a cell array of a NAND flash memory device includes a cell string 101, 102, 103, 104, and a cell string 101, 102 in which a plurality of cells are connected in series to store data. And a drain select transistor 110 and a source select transistor 120 formed between the drains 103 and 104 and the drain and cell strings 101, 102, 103 and 104, and the source, respectively. The drain select transistor 110 is connected to the drain select line DSL and the source select transistor 120 is configured to be connected to the source select line SSL. Here, one drain exists per cell string, and is connected to the bit line BL through a drain contact DCT. In addition, all cell strings share one common source line. Meanwhile, a plurality of cells sharing the same word line WL constitutes one page. In addition, the cell strings 101, 102, 103, and 104 are configured by the number of bit lines BLe and BLo, and accordingly, the drain select transistor 110 and the source select transistor 120 are configured as much.

3 is a cross-sectional view taken along line A-A of FIG. 1 to show a problem occurring when a general drain contact plug is formed. Referring to FIG. 3, the drain contact plug forming process will be described below.

An interlayer insulating layer 11 is formed on the semiconductor substrate 10 on which a predetermined structure such as a cell gate, a source and a drain select transistor gate, and a source and a drain are formed. A photoresist pattern (not shown) is formed on the entire structure to open the drain. The interlayer insulating layer 11 is etched using the photoresist pattern as a mask to form a plurality of drain contact holes for exposing the drain. A polysilicon film is deposited on the entire structure to fill the drain contact hole, and then polished until the upper portion of the interlayer insulating film 11 is exposed to form the drain contact plug 12.

When the drain contact plug is formed in the above manner, since the drain contact plug 12 is arranged in a line with a constant space, the space between the drain contact plug and the drain contact plug is small as the device is reduced. As a result, the short margin decreases (a), resulting in a short failure between the drain contact plugs.

SUMMARY OF THE INVENTION An object of the present invention devised to solve the above problems is to provide a NAND flash memory device and a method of manufacturing the same for securing a short margin between the drain contact plug and the drain contact plug.

A NAND flash memory device according to an embodiment of the present invention may include a plurality of cell strings formed by connecting a plurality of cells in series, a drain select transistor configured between each cell string and each bit line, and a common with each cell string. Source select transistors configured between source lines, and the drain select transistors and source select transistors configured above and below each cell string may include the drain select transistors and source select transistors configured above and below adjacent cell strings. It provides a NAND flash memory device disposed opposite to.

A method of manufacturing a NAND flash memory device according to an exemplary embodiment of the present invention may include a plurality of cell strings, a first selection transistor formed between the cell string and the first junction region, and a second formed between the cell string and the second junction region. Providing a semiconductor substrate including a selection transistor, forming a first interlayer insulating film over the semiconductor substrate, etching a predetermined region of the first interlayer insulating film, and etching the predetermined region of the first interlayer insulating film to be adjacent to the odd-numbered cell string. Forming a plurality of first contact holes exposing a region and exposing the second junction region adjacent to the even-numbered cell string; and forming a conductive layer to fill the plurality of first contact holes. Forming a first contact plug, forming a second interlayer insulating film over the entire structure, and forming a second interlayer insulating film Etching a predetermined region to form a plurality of second contact holes exposing the second junction region adjacent to the odd-numbered cell string and simultaneously exposing the first junction region adjacent to the even-numbered cell string; Forming a plurality of second contact plugs by forming a conductive layer to fill the second contact holes of the plurality of second contact holes, and connecting the plurality of first wires connected to the plurality of first contact plugs and the plurality of second contact plugs. It provides a method of manufacturing a NAND flash memory device comprising the step of forming a plurality of second wiring.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a layout diagram of a NAND flash memory device according to an embodiment of the present invention, and FIG. 5 is a circuit diagram thereof.

4 and 5, one cell array includes a cell string 201, 202, 203, 204, a cell string 201, 202, 203, 204 and a drain connected in series with a plurality of cells for storing data. And drain select transistors 210, 212, 214, and 216 and source select transistors 220, 222, 224, and 226, respectively, between the cell strings 201, 202, 203, and 204 and the source. However, the drain select transistors 210, 212, 214, and 216 and the source select transistors 220, 222, 224, and 226 are not disposed at the same position, but the upper and lower portions of the cell strings 201, 202, 203, and 204. Are placed alternately. That is, on the even bit line BLe side, the drain select transistor 210 is disposed above the cell string 210 around the cell string 210, and the source select transistor 220 is disposed below the cell string 210. Is placed. In contrast, the source select transistor 222 is disposed above the cell string 202 and the drain select transistor 212 is disposed below the cell string 202 on the odd bit line BLO side. The arrangement state of the source select transistors 220, 222, 224, and 226 and the drain select transistors 210, 212, 214, and 216 are repeatedly repeated, and the drain select transistors 210, 212, 214, and 216 are connected to the bit line. The source select transistors 220, 222, 224, and 226 are connected to a common source line CSL. Here, the cell strings 201, 202, 203, and 204 are configured by the number of bit lines BLe and BLo, and accordingly, the drain select transistors 210, 212, 214, and 216 and the source select transistors 220, 222, 224 and 226 are also configured as such.

6A to 6C are cross-sectional views illustrating a line B-B of FIG. 4 taken to explain a method of manufacturing a NAND flash memory device according to an exemplary embodiment of the present invention.

7A to 7C are cross-sectional views taken along line C-C of FIG. 4 to explain a method of manufacturing a NAND flash memory device according to an exemplary embodiment of the present invention.

8A to 8C are cross-sectional views illustrating a line D-D of FIG. 4 taken to explain a method of manufacturing a NAND flash memory device according to an exemplary embodiment of the present invention.

6A, 7A, and 8A, selecting the drain select transistor 340 and the source terminal of the cell 330 to select the drain terminal of the cell 330 and the cell 330 of the NAND flash memory device. A first interlayer insulating layer 302 is formed on the semiconductor substrate 300 on which the source select transistor 350 is formed. A portion of the first interlayer insulating layer 302 is etched to form a source contact hole 304.

6B, 7B, and 8B, a first conductive film is formed over the entire structure such that the source contact hole 304 is filled, and then polished until the top of the first interlayer insulating layer 302 is exposed, so as to expose the source contact plug. 306 is formed. After forming the second interlayer insulating layer 308 on the entire structure, a photoresist pattern (not shown) is formed on the entire structure to open the drain contact region. The second and first interlayer insulating layers 308 and 302 are etched using the photoresist pattern as a mask to form a drain contact hole 310.

Referring to FIGS. 6C, 7C, and 8C, a second conductive layer is deposited on the entire structure such that the drain contact hole 310 is filled, and then polished until the upper portion of the second interlayer insulating layer 308 is exposed. Form 312.

Although not shown in the drawing, a plurality of wires are formed to be connected to the plurality of source contact plugs 306 and a plurality of wires are connected to the source contact plug 306 by forming a plurality of wires connected to the plurality of drain contact plugs 312. The wires are connected to the bar-shaped source lines, and the wires connected to the drain contact plugs are connected to the bit lines.

As described above, when the source contact plug 306 and the drain contact plug 312 are alternately formed, the space between the drain contact plug 312 and the drain contact plug 312 as shown in b of FIG. It is doubled. As a result, a bridge does not occur between the drain contact plug 312 and the drain contact plug 312, thereby ensuring a short margin.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the source contact plug and the drain contact plug are alternately formed to increase the space between the drain contact plug and the drain contact plug so that a bridge does not occur between the drain contact plug and the drain contact plug, thereby reducing the short margin. It can be secured.

Claims (4)

A plurality of cell strings in which a plurality of cells are connected in series; A drain select transistor configured between each cell string and each bit line; A source select transistor configured between each cell string and each common source line; And And each of the drain select transistors and the source select transistors disposed above and below the respective cell strings are disposed opposite to the drain select transistors and the source select transistors disposed above and below the adjacent cell strings. The NAND flash memory device of claim 1, wherein the bit line is disposed above an odd-numbered cell string and the bit line is disposed below an even-numbered cell string. The NAND flash memory device of claim 1, wherein the bit line is disposed under an odd-numbered cell string, and the bit line is disposed above an even-numbered cell string. Providing a semiconductor substrate comprising a plurality of cell strings, a first select transistor formed between the cell string and the first junction region, and a second select transistor formed between the cell string and the second junction region; Forming a first interlayer insulating layer on the semiconductor substrate; Etching a predetermined region of the first interlayer insulating layer to expose the first junction region adjacent to the odd-numbered cell string and to form a plurality of first contact holes exposing the second junction region adjacent to the even-numbered cell string. Doing; Forming a plurality of first contact plugs by forming a conductive layer to fill the plurality of first contact holes; Forming a second interlayer insulating film over the entire structure; A plurality of second contacts etching the predetermined regions of the second and first interlayer insulating layers to expose the second junction region adjacent to the odd-numbered cell strings and to expose the first junction region adjacent to the even-numbered cell strings; Forming a hole; Forming a plurality of second contact plugs by forming a conductive layer to fill the plurality of second contact holes; And Forming a plurality of first wires connected to the plurality of first contact plugs and a plurality of second wires connected to the plurality of second contact plugs.

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