KR20090003662A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
KR20090003662A
KR20090003662A KR1020070066506A KR20070066506A KR20090003662A KR 20090003662 A KR20090003662 A KR 20090003662A KR 1020070066506 A KR1020070066506 A KR 1020070066506A KR 20070066506 A KR20070066506 A KR 20070066506A KR 20090003662 A KR20090003662 A KR 20090003662A
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KR
South Korea
Prior art keywords
voltage
external power
level
semiconductor device
power supply
Prior art date
Application number
KR1020070066506A
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Korean (ko)
Inventor
강길옥
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070066506A priority Critical patent/KR20090003662A/en
Publication of KR20090003662A publication Critical patent/KR20090003662A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

A semiconductor device is provided to prevent the increment of the whole power usage by supplying the external power voltage having relatively low voltage level to an internal circuit. In a semiconductor device, an internal circuit(360) performs the operation which is expected by using the first outer power voltage and outer ground voltage. The boosting up voltage generating circuit(340) produces the boosting-up voltage of the voltage level higher than the second external power voltage by using the second external power voltage and outer ground voltage. A reference voltage generation part(362) of the internal circuit produces the reference voltage(VREF) which is dull to the PVT(Process, Voltage, Temperature) change. The internal voltage generating unit(364) of the internal circuit produces the internal voltage by using the first outer power voltage and outer ground voltage.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor design technology, and more particularly to an external voltage input method of a semiconductor device, and more particularly to a semiconductor device that operates by receiving a plurality of external voltages.

Most semiconductor devices including DRAMs have internal voltage generators on a chip for generating internal voltages of various potentials using a power supply voltage VDD and an external ground voltage VSS supplied from an external device through a set pad PAD. As a result, the voltage necessary for the operation of the chip internal circuit is supplied by itself. The main issue in designing such an internal voltage generator is to provide a stable supply of internal voltage at a desired level.

In addition to the high-speed operation of semiconductor devices, low power has been accelerated. Accordingly, a design technique for satisfying the performance required in a low voltage environment is required. Under such a low voltage environment, most semiconductor devices compensate for voltage loss occurring when operating using the power supply voltage VDD, and boost voltage VPP having a voltage level higher than the power supply voltage VDD to maintain normal data. )need.

In particular, a boost voltage VPP is widely used in DRAM to compensate for a loss caused by a threshold voltage of a MOS transistor in a word line driver circuit, a bit line isolation circuit, and a data output buffer circuit.

On the other hand, in the case of DRAM, the back bias voltage VBB having a voltage level lower than the external ground voltage VSS is applied to the bulk of the NMOS transistor used as the cell transistor.

The boosted voltage VPP, the back bias voltage VBB, and the like are generated using a charge pumping method, and since the voltage generation mechanism is the same, the configuration is similar.

1 is a block diagram illustrating a relationship between a pad PAD for supplying an external voltage and a circuit using an external voltage as a voltage source in a conventional semiconductor device.

Referring to FIG. 1, a pad PAD for supplying an external voltage in a semiconductor device according to the related art includes a first pad 100 and an external ground voltage VSS for receiving an external power supply voltage VDD. It has a second pad 120 for receiving the input.

In addition, the circuit using an external voltage as a voltage source in the semiconductor device according to the prior art, the external power supply voltage (VDD) received through the first pad 100 and the external ground voltage received through the second pad 120. A boosted voltage generation circuit 140 and an internal circuit 160 for performing a predetermined operation using (VSS) as a voltage source are provided.

Here, the boosted voltage generation circuit 140 has a higher voltage level than the external power supply voltage VDD through a charge pumping method using the external power supply voltage VDD and the external ground voltage VSS as the voltage source. The operation of generating the voltage VPP is performed.

In addition, among the components of the internal circuit 160, the reference voltage generator 162 is insensitive to PVT (PROCESS, VOLTAGE, TEMPERATURE) variations using the external power supply voltage VDD and the external ground voltage VSS as voltage sources. The operation of generating the reference voltage VREF is performed.

Similarly, the internal voltage generator 164 of the components of the internal circuit 160 uses an external power supply voltage VDD and an external ground voltage VSS as a voltage source, and is a semiconductor device through a down converting method. And generating an internal voltage used internally, for example, a core voltage VCORE, a ferry voltage VPERI, a bit line precharge voltage VBLP, and the like.

In addition, although not represented in the drawings, a plurality of circuits or devices included in the internal circuit 160 perform predetermined operations using the external power supply voltage VDD and the external ground voltage VSS as voltage sources, respectively.

2 is a block diagram illustrating in detail a boosted voltage generation circuit for generating a boosted voltage in a semiconductor memory device according to the related art.

Referring to FIG. 2, a boosted voltage generation circuit for generating a boosted voltage VPP in a semiconductor memory device according to the related art is configured to detect a level of the boosted voltage VPP corresponding to a level of a reference voltage VREF. An oscillation signal generator 144 for generating an oscillation signal OSC that oscillates at a predetermined period in response to the signal detected by the voltage detector 140 and the signal output from the voltage detector 140, and a charge in response to the oscillation signal OSC. A charge pumping unit 146 for outputting a boosted voltage VPP is provided by performing a pumping operation.

Here, the reference voltage VREF input to the voltage detector 142 is a voltage having a target level of the boosted voltage VPP. In general, a voltage obtained by dividing the boosted voltage VPP at a constant ratio is determined by the reference voltage VREF. Compared with the level, it is detected whether the level of the boosted voltage VPP is larger or smaller than the target level. At this time, the detection signal DET is activated when the level of the boosted voltage VPP is smaller than the target level and deactivated when the level of the boosted voltage VPP is greater than the target level.

The oscillation signal OSC output from the oscillation signal generator 144 oscillates at a predetermined frequency when the detection signal DET output from the voltage detector 142 is activated, and the detection signal DET is deactivated. If it does not rash.

In addition, the charge pumping unit 146 increases the level of the boosted voltage VPP by performing the charge pumping operation in response to the oscillation signal OSC oscillating at a predetermined frequency, so that the oscillation signal OSC does not oscillate. Does not perform a charge pumping operation.

At this time, the oscillation signal OSC oscillates at a predetermined frequency so that the level of the boost voltage VPP, which can be raised by the charge pumping unit 146 in one charge pumping operation, is relatively small.

That is, the charge pumping unit 146 performs one or two charge pumping operations to not raise the level of the boosted voltage VPP to the target level, but rather performs a plurality of charge pumping operations many hundreds of times to several hundred times. The level of VPP) is raised to the target level.

There are two general design methods for reducing the number of charge pumping operations. The first is to increase the level of the voltage used as the voltage source in the charge pumping unit 146, that is, the external power supply voltage VDD. .

When the level of the supplied external power voltage VDD is relatively high, the difference with the output voltage of the boosted voltage VPP does not become large so that a relatively small number of charge pumping operations are performed to increase the voltage of the boosted voltage VPP. The level can be raised to the target level.

In fact, the relatively old technologies such as SDRAM (Synchronous DRAM) and DDR SDRAM (Double Data Rate SDRAM) have relatively high levels of input external power supply voltage (VDD), and thus perform a relatively small number of charge pumping operations. The level of the voltage VPP could be raised to the target level.

That is, in the case of the SDRAM and the DDR SDRAM, since the external power supply voltage VDD having the level of 2.5 V is input, generating the boost voltage VPP having the target level of 3.3 V does not cause the voltage level difference to be relatively large. A relatively small number of charge pumping operations were performed to raise the level of the boosted voltage VPP to the target level.

However, in the case of relatively recent technologies such as DDR2 SDRAM or DDR3 SDRAM, the trend is to minimize the power used in semiconductor devices by lowering the external power supply voltage (VDD). There is a problem that the ascending method cannot be used.

A second design method for reducing the number of charge pumping operations is to perform a charge pumping operation using a relatively large number of steps in the charge pumping unit 146. In other words, the size of the level that can be raised through a single charge pumping operation is increased.

However, performing the charge pumping operation using many steps in the charge pumping unit 146 unconditionally means that the area occupied by the charge pumping unit 146, and thus the boosted voltage generation circuit 140, increases in the semiconductor device. it means.

As described above, applying a boosted voltage generation circuit having an increased area to a semiconductor device has a problem in that it becomes a big burden in developing a semiconductor device that has to be miniaturized and integrated.

Accordingly, the present invention is to solve the problems of the prior art as described above, by using a plurality of external voltage to prevent the increase in the area occupied by the boosted voltage generation circuit in the semiconductor device, while providing a semiconductor device that operates at a low power Its purpose is to.

According to an aspect of the present invention for achieving the above technical problem, a first pad for receiving a first external power supply voltage; A second pad for receiving an external ground voltage; A third pad for receiving a second external power voltage having a voltage level higher than the first external power voltage; An internal circuit configured to perform a predetermined operation using the first external power supply voltage and the external ground voltage as a voltage source; And a boosted voltage generation circuit configured to generate a boosted voltage having a voltage level higher than the second external power supply voltage by using the second external power supply voltage and the external ground voltage as a voltage source.

The present invention described above further includes a pad for supplying a voltage for using the semiconductor device as a voltage source in a circuit for generating a boosted voltage among the components, and by supplying an external power supply voltage having a relatively high level in the semiconductor device. There is an effect that the area occupied by the circuit generating the boosted voltage can be prevented from increasing.

In addition, by supplying an external power supply voltage having a relatively low voltage level to the internal circuits other than the circuit for generating the boosted voltage among the components of the semiconductor device, it is possible to prevent the amount of power used in the entire semiconductor device from increasing. It works.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, parts denoted by the same reference numerals (or reference numerals) throughout the specification represent the same elements.

FIG. 3 is a block diagram illustrating a relationship between a pad PAD for supplying an external voltage and circuits using an external voltage as a voltage source in a semiconductor device according to an exemplary embodiment of the present invention.

3, a pad PAD for supplying an external voltage in a semiconductor device according to an embodiment of the present invention may include a first pad 300 and an external ground voltage for receiving a first external power supply voltage VDD1. A second pad 320 for receiving the VSS, a third pad 380 for receiving the second external power supply voltage VDD2 having a voltage level higher than the first external power supply voltage VDD1, and 1 Internal circuit 360 for performing a predetermined operation using the external power supply voltage VDD1 and the external ground voltage VSS as the voltage source, and the second external power supply voltage VDD2 and the external ground voltage VSS as the voltage source. Thus, a boosted voltage generation circuit 340 for generating a boosted voltage VSS having a voltage level higher than that of the second external power supply voltage VDD2 is provided.

Here, among the components of the internal circuit 360, the reference voltage generator 362 uses the first external power supply voltage VDD1 and the external ground voltage VSS as voltage sources to change PVT (PROCESS, VOLTAGE, TEMPERATURE). The operation of generating an insensitive reference voltage VREF is performed.

Similarly, the internal voltage generator 364 of the components of the internal circuit 360 uses the first external power supply voltage VDD1 and the external ground voltage VSS as a voltage source, and uses a down converting method. An internal voltage used in the semiconductor device, for example, a core voltage VCORE, a ferry voltage VPERI, a bit line precharge voltage VBLP, or the like, is generated.

In addition, although not shown in the drawings, a plurality of circuits or devices included in the internal circuit 360 perform a predetermined operation using the first external power supply voltage VDD1 and the external ground voltage VSS as voltage sources, respectively.

4 is a block diagram illustrating in detail a boosted voltage generation circuit for generating a boosted voltage in a semiconductor device according to the embodiment of the present invention shown in FIG. 3.

Referring to FIG. 4, a boosted voltage generation circuit 340 for generating a boosted voltage VPP in a semiconductor device according to an exemplary embodiment of the present invention may correspond to a level of the boosted voltage VPP corresponding to the level of the reference voltage VREF. A voltage detector 342 for detecting a level, an oscillation signal generator 344 for generating an oscillation signal OSC that oscillates at a predetermined period in response to a signal output from the voltage detector 340, and an oscillation signal OSC Charge pumping unit 346 for outputting boosted voltage VPP by performing a charge pumping operation in response to.

Here, the reference voltage VREF input to the voltage detector 342 is a voltage having a target level of the boosted voltage VPP. In general, the voltage obtained by dividing the boosted voltage VPP at a constant ratio is determined by the reference voltage VREF. Compared with the level, it is detected whether the level of the boosted voltage VPP is larger or smaller than the target level. At this time, the detection signal DET is activated when the level of the boosted voltage VPP is smaller than the target level and deactivated when the level of the boosted voltage VPP is greater than the target level.

The oscillation signal OSC output from the oscillation signal generator 344 oscillates at a predetermined frequency when the detection signal DET output from the voltage detector 342 is activated, and the detection signal DET is deactivated. If it does not rash.

The charge pumping unit 346 increases the level of the boosted voltage VPP by performing the charge pumping operation in response to the oscillation signal OSC oscillating at a predetermined frequency, and the oscillation signal OSC does not oscillate. Does not perform a charge pumping operation.

However, the configuration and operation of the boost voltage generation circuit 340 for generating the boost voltage VPP in the semiconductor device according to the embodiment of the present invention described above with reference to FIG. It can be seen that the configuration and operation of the boosted voltage generation circuit 140 for generating the boosted voltage VPP are not significantly different.

However, the first external power source is different from the other circuits or devices provided in the boosted voltage generation circuit 340 and the internal circuit 360 for generating the boosted voltage VPP in the semiconductor device according to the embodiment of the present invention. The charge pumping operation is performed by using the second external power supply voltage VDD2 having the level higher than the voltage VDD1 and the external ground voltage VSS as the voltage source.

That is, the voltage booster voltage generation circuit 140 receives the external power supply voltage VDD input to the semiconductor device from the booster voltage generator circuit 140 for generating the boosted voltage VPP in the semiconductor device according to the related art of FIG. 2. In contrast, the semiconductor device according to the embodiment of the present invention has a second external power supply voltage having a relatively high level additionally input for the boost voltage generation circuit 340 for generating the boost voltage VPP. VDD2) is used to generate a boosted voltage VPP.

As such, when the boosted voltage VPP is generated using the second external power supply voltage VDD2 having a relatively high level, as described in the above-described prior art, charges among the components of the boosted voltage generation circuit 340 are generated. The pumping unit 346 may increase the level of the boosted voltage VPP through a relatively small charge pumping operation.

However, in the semiconductor device according to the exemplary embodiment of the present invention, the remaining internal circuit 360 except the boosted voltage generation circuit 340 may receive the first external power supply voltage VDD1 having a level lower than the second external power supply voltage VDD2. It can be used to avoid the trend of the semiconductor device using a low voltage that has been a problem in the prior art.

As described above, when the embodiment of the present invention is applied, the first external power supply voltage VDD1 having a relatively low voltage level used as a voltage source in most internal circuits 360 of components of the semiconductor device, By receiving a second external power supply voltage VDD2 having a relatively high voltage level used as a voltage source in the boosted voltage generation circuit 340 separately, the area occupied by the boosted voltage generation circuit 340 increases in the semiconductor device. You can prevent it.

In addition, since most of the internal circuits 360 of the components of the semiconductor device operate by using the first external power supply voltage VDD1 having a relatively low voltage level, the amount of power used in the entire semiconductor device is increased. Can be prevented.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

For example, in the above-described embodiment, the first external power supply voltage VDD1, the second external power supply voltage VDD2, and the external ground voltage VSS are examples of the plurality of external voltages input to the semiconductor device. This includes the case where a number of external voltages are input.

1 is a block diagram illustrating a relationship between a pad PAD for supplying an external voltage and a circuit using an external voltage as a voltage source in a semiconductor device according to the related art.

2 is a block diagram illustrating in detail a boosted voltage generation circuit for generating a boosted voltage in a semiconductor memory device according to the prior art;

3 is a block diagram illustrating a relationship between a pad PAD for supplying an external voltage and circuits using the external voltage as a voltage source in a semiconductor device according to an embodiment of the present invention.

4 is a block diagram illustrating in detail a boosted voltage generation circuit for generating a boosted voltage in a semiconductor device according to the embodiment of the present invention shown in FIG.

* Explanation of symbols for main parts of the drawings

100, 300: first pad 120, 320: second pad

140, 340: boosted voltage generation circuit 160, 360: internal circuit

162, 362: reference voltage generator 164, 364: internal voltage generator

380: third pad 142, 342: voltage detector

144, 344: oscillation signal generation unit 146, 346: charge pumping unit

Claims (3)

A first pad configured to receive a first external power voltage; A second pad for receiving an external ground voltage; A third pad for receiving a second external power voltage having a voltage level higher than the first external power voltage; An internal circuit configured to perform a predetermined operation using the first external power supply voltage and the external ground voltage as a voltage source; And Step-up voltage generation circuit for generating a step-up voltage of a voltage level higher than the second external power supply voltage using the second external power supply voltage and the external ground voltage as a voltage source. A semiconductor device comprising a. The method of claim 1, The internal circuit includes a reference voltage generator for generating a reference voltage having a predetermined level. The method of claim 2, The boosted voltage generation circuit, A voltage detector for detecting a level of a boosted voltage corresponding to the level of the reference voltage; An oscillation signal generator for generating an oscillation signal oscillating at a predetermined period in response to an output signal of the voltage detector; And And a charge pumping unit configured to output the boosted voltage by performing a charge pumping operation in response to the oscillation signal.
KR1020070066506A 2007-07-03 2007-07-03 Semiconductor device KR20090003662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070066506A KR20090003662A (en) 2007-07-03 2007-07-03 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070066506A KR20090003662A (en) 2007-07-03 2007-07-03 Semiconductor device

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KR20090003662A true KR20090003662A (en) 2009-01-12

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KR1020070066506A KR20090003662A (en) 2007-07-03 2007-07-03 Semiconductor device

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