KR20090002632A - Method for forming a transistor with multi-plane channel - Google Patents

Method for forming a transistor with multi-plane channel Download PDF

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Publication number
KR20090002632A
KR20090002632A KR1020070066144A KR20070066144A KR20090002632A KR 20090002632 A KR20090002632 A KR 20090002632A KR 1020070066144 A KR1020070066144 A KR 1020070066144A KR 20070066144 A KR20070066144 A KR 20070066144A KR 20090002632 A KR20090002632 A KR 20090002632A
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KR
South Korea
Prior art keywords
film
layer
forming
heterogeneous material
device isolation
Prior art date
Application number
KR1020070066144A
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Korean (ko)
Inventor
김광옥
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070066144A priority Critical patent/KR20090002632A/en
Publication of KR20090002632A publication Critical patent/KR20090002632A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for fabricating a transistor having multi channels is provided to secure the channel section by maintaining the active area which is contacted with the gate uniformly. A method for fabricating a transistor having multi channels comprises a step for forming an element isolation film on a substrate; a step for etching the element isolation film; a step for protruding the active area; a step for forming a gate insulating layer; a step for forming a gate electrode. An element isolation film(111) is formed on the trench arranged on the substrate(110). The element isolation film successively can have laminated insulating layers(111a,111b,111c). A second insulating layer can have different etching ratio from the first and third insulating layers. The second and third insulating layers are successively etched from the first insulating layer. The active area is protruded from the third insulating layer. The gate insulating layer is formed on the active area. Gate electrodes(116,117) are formed on the gate insulating layer passing through the active area.

Description

METHODS FOR FORMING A TRANSISTOR WITH MULTI-PLANE CHANNEL}

TECHNICAL FIELD The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of forming a transistor having a multi-sided channel.

Recently, saddle type pin transistors having been mixed with these have been proposed in order to take full advantage of fin type and recess type transistors. The saddle-type pin transistor is a structure that can solve the problem of the pin-type transistor low threshold voltage and short effective channel length in parallel with the recessed transistor. Accordingly, it may be advantageous to apply a saddle-type pin transistor rather than a pin-type transistor in a DRAM (Dynamic Random Access Memory) device in consideration of operating characteristics of the device.

Hereinafter, a method of forming a saddle-type fin transistor according to the prior art will be described.

1 is a perspective view showing a saddle-type fin transistor according to the prior art, Figure 2 is a cross-sectional view taken along the cutting line (I-I ', II-II') shown in FIG. 3 is a SEM (Scanning Electron Microscope) photograph showing a cross section of the saddle-type fin transistor along the II-II ′ cut line shown in FIG. 1. 4A to 4E are process perspective views.

First, as shown in FIG. 4A, a device isolation film 11 is formed in the substrate 10 by performing a shallow trench isolation (STI) process, and then a fin mask 12 is formed on the substrate 10. Form.

Subsequently, as illustrated in FIG. 4B, an etching process using the fin mask 12 is performed to form the saddle-shaped fin 14. In this case, the etching process uses an etching selectivity between the substrate 10 and the device isolation layer 11. First, the substrate 10 is etched, and then the device isolation layer 11 is etched and recessed. As a result, the saddle-shaped fin 14 is formed in the active region.

Next, as shown in FIG. 4C, the pin mask 12 is removed.

Subsequently, as shown in FIG. 4D, a gate oxide film 15 is formed on the surface of the substrate 10.

Next, as shown in FIG. 4E, the polysilicon film 16 and the conductive film 17 are sequentially deposited so that the fins 14 are embedded.

Subsequently, the conductive film 17 and the polysilicon film 16 are etched to form a gate.

However, according to the related art, the method of forming a saddle-type fin transistor according to the related art is based on the etching process performed in FIG. 4B because the height H2-H1 of FIG. 11) There is a lot of difficulty in controlling the degree of retreat stably. As a result, it is difficult to control the height of the saddle-shaped pin 14, resulting in a problem of deterioration of device characteristics.

Accordingly, the present invention has been proposed to solve the problems of the prior art, and an object thereof is to provide a method for forming a transistor having a multi-channel that can stably control a channel area.

According to an aspect of the present invention, there is provided a device isolation layer including a heterogeneous material film in an intermediate layer in a substrate, and retreating the device isolation film as an etch stop layer. Removing the heterogeneous material layer to protrude an active region over the device isolation layer, forming a gate insulating layer along a step of the protruding active region, and forming a gate electrode on the gate insulating layer. Provided is a method for forming a transistor having a multi-sided channel.

As described above, according to the present invention, a pin (or saddle type) is formed by interposing a heterogeneous material film in the middle of an isolation layer and using the hetero material film as an etch stop layer during the fin (or saddle-shaped fin) forming process. The height of the pin) can be controlled stably. Through this, it is easy to control the channel area to improve the characteristics of the device.

Hereinafter, with reference to the accompanying drawings, the most preferred embodiment of the present invention will be described. In addition, in the drawings, the thicknesses and spacings of layers and regions are exaggerated for ease of explanation and clarity, and when referred to as being on or above another layer or substrate, it is different. It may be formed directly on the layer or the substrate, or a third layer may be interposed therebetween. In addition, the parts denoted by the same reference numerals throughout the specification represent the same layer, and when the reference numerals include the English, it means that the same layer is partially modified through an etching or polishing process.

Example 1

FIG. 5 is a perspective view illustrating a method of manufacturing a saddle-type fin transistor according to Embodiment 1 of the present invention, and FIGS. 6A and 6B are taken along the line II ′ and II- of FIG. A cross-sectional perspective view taken along the line II '. 7A to 7F are perspective views illustrating a method of manufacturing the saddle fin transistor illustrated in FIG. 5.

First, as shown in FIGS. 5, 6, and 7A, trenches (not shown) are formed in the substrate 110.

Next, the first insulating layer 111a is formed to partially fill the trench. In this case, the first insulating layer 111a is formed of any one selected from a high density plasma (HDP) film, a high aspect ratio process (HARP) film, and a spin on dielectric (SOD) film having excellent embedding characteristics.

Subsequently, a second insulating film 111b formed of a heterogeneous material film having a different etching selectivity from the first insulating film 111a is formed on the first insulating film 111a. For example, the second insulating film 111b is formed of a nitride film when the first insulating film 111a is formed of an oxide film. More specifically, a silicon-containing nitride film such as Si x N y (x, y is an integer), SiON or SRON (silicon rich SiON) film is formed. The second insulating layer 111b is preferably deposited within a minimum thickness range that can function as an etch stop layer, for example, 100 Å to 500 Å.

Subsequently, the third insulating film 111c is deposited on the second insulating film 111b so that the inside of the trench is completely filled, and then a planarization process such as a chemical mechanical polishing (CMP) process is performed to isolate the inside of the trench. In this case, the third insulating layer 111c may be formed of the same material as the first insulating layer 111a or may be formed of a different material, and the third insulating layer 111c may be formed of a material having a different etching selectivity from the second insulating layer 111b. As a result, the device isolation layer 111 is formed of a laminated film in which the first to third insulating films 111a, 111b, and 111c are stacked.

Subsequently, a mask process is performed to form the fin mask 112 on the semiconductor substrate 110.

Subsequently, as illustrated in FIGS. 5, 6, and 7B, the etching process using the fin mask 112 is performed to form the saddle-shaped fin 114. In this case, the etching process is performed by using the second insulating layer 111b, which is an intermediate layer of the device isolation layer 111, as the etch stop layer. For example, in the etching process, the silicon substrate 110 is first etched, and then only the third insulating layer 111c, which is the upper layer of the device isolation layer 111, is etched to form the saddle-shaped fin 114. At this time, in the process of etching the third insulating film 111c, it is preferable to perform the etching condition to bring the etching selectivity between the oxide film and the nitride film as high as possible to selectively remove only the third insulating film 111c. As a result, the third insulating film 111c is selectively removed, and the second insulating film 111b is exposed. Accordingly, the height of the saddle fin 114 formed by the etching process is determined by the second insulating layer 111b.

Subsequently, as shown in FIGS. 5, 6 and 7C, the second insulating layer 111b is selectively removed by using only the etching solution without using the pin mask 112 as it is. As a result, the height of the saddle-shaped fin 114 is also increased by the thickness of the second insulating layer 111b. Meanwhile, the etching process for removing the second insulating layer 111b selectively removes the second insulating layer 111b under the condition that the selectivity between the oxide layer and the nitride layer is as high as possible.

Subsequently, as shown in FIGS. 5, 6 and 7D, the fin mask 112 is removed through a strip process.

Subsequently, as illustrated in FIGS. 5, 6, and 7E, the gate insulating layer 115 is formed on the exposed surface of the substrate 110 by performing a gate oxidation process. At this time, the oxidation process is carried out by an oxidation process using dry oxidation, wet oxidation or radical ions.

Subsequently, as shown in FIGS. 5, 6, and 7F, the polysilicon film 116 and the conductive film 117 are sequentially deposited with the gate electrode material to cover the saddle-shaped fins 114 (see FIG. 7D). do. For example, the polysilicon film 116 is formed of a doped polysilicon film doped with impurity ions. In addition, the conductive film 117 is formed of any one of a transition metal or a rare earth metal, or a nitride layer, a silicide layer, or a laminated structure in which these are laminated.

Subsequently, the conductive film 117 and the polysilicon film 116 are etched to form a gate electrode.

Example 2

Embodiment 2 of the present invention is an embodiment in which the saddle-type pin transistor manufacturing method according to Embodiment 1 is applied to the manufacturing method of the pin transistor as it is. That is, it is possible to stably control the height of the fins by interposing a heterogeneous material in the device isolation layer and using the heterogeneous material as an etch stop layer during the device separator retreat process for forming the fin.

10A to 10E are perspective views illustrating a method of manufacturing a saddle-type fin transistor according to Embodiment 2 of the present invention.

First, as shown in FIG. 8A, a trench (not shown) is formed in the substrate 210.

Subsequently, the first insulating layer 211a is formed to partially fill the trench. In this case, the first insulating film 211a is formed of any one selected from among the HDP film, the HARP film, and the SOD film having excellent embedding characteristics.

Subsequently, a second insulating film 211b formed of a heterogeneous material film having a different etching selectivity from the first insulating film 211a is formed on the first insulating film 211a. For example, the second insulating film 211b is formed of a nitride film. More specifically, it is formed of Si x N y (x, y is an integer), SiON or SRON film. The second insulating film 211b is preferably deposited within a minimum thickness range that can function as an etch stop layer, for example, 100 Å to 500 Å.

Subsequently, after the third insulating film 211c is deposited on the second insulating film 211b so that the inside of the trench is completely filled, a planarization process such as a CMP process is performed to isolate the inside of the trench. In this case, the third insulating film 211c may be formed of the same material as the first insulating film 211a or may be formed of a different material, but may be formed of a material having a different etching selectivity from the second insulating film 211b. As a result, the device isolation film 211 is formed of a laminated film in which the first to third insulating films 211a, 211b, and 211c are stacked.

Subsequently, a mask process is performed to form the fin mask 212 on the semiconductor substrate 210.

Subsequently, as illustrated in FIG. 8B, an etching process using the fin mask 212 is performed to form the fin 214. In this case, in the etching process, the third insulating layer 211c is selectively etched using the second insulating layer 211b as an etch stop layer. Here, the etching process may be performed under an etching condition in which the etching selectivity between the oxide film and the nitride film is as high as possible, so that only the third insulating film 211c may be selectively removed. As a result, the third insulating film 211c is selectively removed, and the second insulating film 211b is exposed. Therefore, the height of the fin 214 formed by the etching process is determined by the second insulating film 211b.

Subsequently, as shown in FIG. 8C, the second insulating layer 211b is selectively removed by using only the etching solution without using the pin mask 212 without removing the pin mask 212. As a result, the height of the fin 214 is also increased by the thickness of the second insulating film 211b. On the other hand, the etching process for removing the second insulating film 211b selectively removes the second insulating film 211b under the condition that the selectivity between the oxide film and the nitride film is as high as possible.

The pin mask 212 is then removed via a strip process.

Subsequently, as shown in FIG. 8D, a gate insulating film 215 is formed on the surface of the substrate 210. In this case, the gate insulating layer 215 is formed by an oxidation process using dry oxidation, wet oxidation, or radical ions.

Subsequently, as shown in FIG. 8E, the gate electrode material, for example, the polysilicon film 216 and the conductive film 217 are sequentially deposited to cover the fin 214.

Subsequently, the conductive film 217 and the polysilicon film 216 are etched to form a gate electrode.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a perspective view showing a saddle-type fin transistor according to the prior art.

FIG. 2 is a cross-sectional view taken along the cut lines I-I 'and II-II' shown in FIG. 1; FIG.

Figure 3 is a SEM (Scanning Electron Microscope) photograph showing a cross-section of the saddle-type fin transistor prepared by the prior art.

4A to 4E are process perspective views showing a saddle-type fin transistor forming method according to the prior art.

5 is a perspective view showing a saddle-type fin transistor according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view taken along the cut lines I-I 'and II-II' shown in FIG. 5; FIG.

7A to 7F are process perspective views showing a saddle-type fin transistor forming method according to Embodiment 1 of the present invention.

8A to 8E are process perspective views showing a saddle-type fin transistor forming method according to Embodiment 2 of the present invention.

<Explanation of symbols for the main parts of the drawings>

110, 210: semiconductor substrate 111, 211: device isolation film

111a, 211a: first insulating film 111b, 211b: second insulating film

111c and 211c: Third insulating film 112 and 212: Fin mask

114: saddle pin 214: pin

115, 215: gate insulating film 116, 216: polysilicon film

117, 217: conductive film

Claims (9)

Forming an isolation layer in the substrate having a heterogeneous material film interposed in the intermediate layer; Retracting the device isolation layer using the heterogeneous material layer as an etch stop layer; Removing the heterogeneous material film to protrude an active region over the device isolation layer; Forming a gate insulating film along a step of the protruding active region; And Forming a gate electrode on the gate insulating film A transistor forming method having a multi-channel including a. The method of claim 1, And retracting the active region to an upper height of the heterogeneous material film before the retreating the device isolation layer. The method of claim 1, Retracting the device isolation layer has a multi-faceted channel that retracts the active region together. The method of claim 1, And after the retracting the device isolation layer, retracting the heterogeneous material layer with the etch stop layer. The method of claim 1, And the heterogeneous material film is formed of a nitride film. The method of claim 5, wherein And the nitride film is a nitride film containing silicon. The method of claim 1, The heterogeneous material film has a multi-channel formed in a thickness of 100 ~ 500Å. The method of claim 1, The device isolation layer has a polyhedral channel having a multi-channel structure in which a first oxide film and a second oxide film are stacked on top of and below the heterogeneous material film. The method of claim 8, And the first and second oxide layers are formed of any one selected from a high density plasma (HDP), a high aspect ratio process (HARP), and a spin on dielectric (SOD).
KR1020070066144A 2007-07-02 2007-07-02 Method for forming a transistor with multi-plane channel KR20090002632A (en)

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