KR20080114023A - Fabrication method for a nanowire - Google Patents

Fabrication method for a nanowire Download PDF

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KR20080114023A
KR20080114023A KR1020070063168A KR20070063168A KR20080114023A KR 20080114023 A KR20080114023 A KR 20080114023A KR 1020070063168 A KR1020070063168 A KR 1020070063168A KR 20070063168 A KR20070063168 A KR 20070063168A KR 20080114023 A KR20080114023 A KR 20080114023A
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nanowires
silicon
nanowire
oxide film
manufacturing
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이국녕
성우경
정석원
김원효
조남규
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전자부품연구원
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
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    • H01L21/02603—Nanowires
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
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    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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Abstract

The method for manufacturing nanowires is provided to use the silicon nano wire that does not completely float as the sacrificial layer and to manufacture the nanowire which has the stress-proof in the material deposition. The nanowire manufacturing method comprises as follows. A step is for making the silicon nano wire. A step is for evaporating the material for making the nanowire in the silicon nano wire. A step is for removing the silicon nano wire. The silicon nano wire is connected to the silicon substrate(200) by the silicon or the oxide film.

Description

나노와이어 제작 방법{Fabrication method for a nanowire}Fabrication method for a nanowire

도 1a는 종래의 실리콘 나노와어어의 구성도,1A is a configuration diagram of a conventional silicon nanowire;

도 1b는 종래의 실리콘 나노와이어의 제작 방법을 나타낸 도면,Figure 1b is a view showing a manufacturing method of a conventional silicon nanowire,

도 2a 내지 도 2c는 본 발명의 일실시예에 따른 알루미늄 나노와이어 제작 방법을 나타낸 도면,2a to 2c is a view showing a method for manufacturing aluminum nanowires according to an embodiment of the present invention,

도 3a 및 도 3b는 본 발명의 다른 실시예에 따른 완전히 떠 있지 않은 실리콘 나노와이어를 나타낸 도면,3A and 3B show completely non-floating silicon nanowires according to another embodiment of the invention,

도 4a는 본 발명의 또 다른 실시예에 따른 Coaxial 구조의 나노와이어를 나타낸 도면,Figure 4a is a view showing a nanowire of the coaxial structure according to another embodiment of the present invention,

도 4b는 본 발명의 또 다른 실시예에 따른 Triaxial 구조의 나노와이어를 나타낸 도면이다.Figure 4b is a view showing a nanowire of a triaxial structure according to another embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명>           <Explanation of symbols for main parts of the drawings>

200 : 실리콘 기판 210 : 실리콘 나노와이어200: silicon substrate 210: silicon nanowires

220 : 알루미늄 나노와이어220: aluminum nanowire

본 발명은 나노와이어 제작 방법에 관한 것으로, 보다 자세하게는 종래의 실리콘 나노와이어를 희생층으로 사용하여 다양한 물질을 증착시켜 나노와이어를 제작하는 방법에 관한 것이다.The present invention relates to a method for manufacturing nanowires, and more particularly, to a method for manufacturing nanowires by depositing various materials using conventional silicon nanowires as a sacrificial layer.

나노와이어(nano wire)는 수십 대 일의 큰 종횡비(aspect ratio)를 가지는 나노 스케일의 구조로써, 이러한 나노와이어가 적용된 소자는 그 응용에 따라 FET와 같이 각종 전자소자의 핵심부품인 트랜지스터로 이용될 수 있고, 화학센서 및 바이오센서 등으로 다양하게 이용될 수 있다.Nanowires are nanoscale structures with large aspect ratios of several tens of days. These nanowires can be used as transistors, which are the core components of various electronic devices, such as FETs. It may be used in various ways, such as chemical sensors and biosensors.

종래의 수십 미크론의 길이를 갖는 나노와이어를 제작하는 방법은 다공성 나노와이어 구조물(AAO 또는 폴리머로 이루어진 희생층 구조물 등)에 원하는 재료를 채워넣은 후, 이를 제거함으로써 얻어지는 나노와이어를 이용하는 방법이 주로 사용되고 있다. 또한 기판 일부에 나노리소그라피 기술 등으로 나노와이어 폭 등을 정의하여 직접 나노와이어를 얻거나 그 하부 물질을 RIE 등으로 식각함으로써 원하는 재료로 이루어진 나노와이어를 제작하였다.Conventional methods for manufacturing nanowires having a length of several tens of microns are mainly used by using nanowires obtained by filling a desired material in porous nanowire structures (such as AAO or sacrificial layer structures made of polymers) and then removing them. have. In addition, nanowire width was defined on a portion of the substrate by using nanolithography technology to obtain nanowires directly, or nanowires made of desired materials were manufactured by etching the underlying material by RIE.

하지만 종래의 이러한 방법들은 여러 가지 문제점들이 있다.However, these conventional methods have various problems.

다공성 희생층을 이용한 나노와이어 제작 방법은 위치와 개수 조절이 자유로운 나노와이어를 제작하기 어렵고, 특히 수평배향으로 이루어진 현과 같은 떠있는 나노와이어를 얻기 어렵다.In the nanowire fabrication method using the porous sacrificial layer, it is difficult to fabricate the nanowires free of position and number control, and in particular, it is difficult to obtain floating nanowires such as strings having horizontal orientations.

또한, 나노리소그라피 기술을 이용한 나노와이어 제작 방법도 제작공정이 비싸고 어려워 경제성이 없다는 문제점이 있다.In addition, a nanowire manufacturing method using nanolithography technology also has a problem that the manufacturing process is expensive and difficult and economical.

이러한 문제점을 해결하기 위해, 본 출원인은 공개특허 2007-33794호에서 실리콘 나노와이어 제작 방법을 개발하였다.In order to solve this problem, the applicant has developed a method for manufacturing silicon nanowires in Korean Patent Publication No. 2007-33794.

도 1a는 종래의 실리콘 나노와어어의 구성도이고, 도 1b는 종래의 실리콘 나노와이어의 제작 방법을 나타낸 도면이다.1A is a configuration diagram of a conventional silicon nanowire, and FIG. 1B is a view illustrating a method of manufacturing a conventional silicon nanowire.

도 1a를 참조하면, 실리콘 나노와이어(110)는 실리콘 기판(100)을 식각하여 제작되며, 지지대(120)에 의해 공중에 떠 있는 구조이다.Referring to FIG. 1A, the silicon nanowires 110 are manufactured by etching the silicon substrate 100 and are floating in the air by the support 120.

그리고 도 1b를 참조하면, 실리콘 나노와이어(110)의 제작 방법을 알 수 있다.1B, a method of manufacturing the silicon nanowires 110 may be known.

첫 번째로, 결정구조가 (100) 방향을 갖는 실리콘 기판(100)에 열산화를 통해 제1 열산화막(130)을 생성시킨다.First, the first thermal oxide film 130 is formed through thermal oxidation on the silicon substrate 100 having a crystal structure in the (100) direction.

두 번째로, 사진식각 공정으로 식각할 부분의 산화막을 제거하고, RIE 공정과 같은 실리콘 건식 식각 공정으로 실리콘 이방성 식각을 통해 칼럼구조(140)를 형성한다. Second, the oxide layer of the portion to be etched is removed by a photolithography process, and the column structure 140 is formed through silicon anisotropic etching by a silicon dry etching process such as a RIE process.

세 번째로, 형성된 칼럼구조(140)에 KOH 등의 실리콘 이방성 식각용액을 이용하여 실리콘 기판을 습식 식각한다. 여기서 실리콘 기판의 (100) 결정방향의 식각 특성으로 인해 나노와이어 구조물(150)은 단면이 소정의 경사를 갖는 역삼각형 구조로 형성된다.Third, the silicon substrate is wet etched using the silicon anisotropic etching solution such as KOH in the formed columnar structure 140. Here, due to the etching characteristic of the (100) crystal direction of the silicon substrate, the nanowire structure 150 is formed in an inverted triangle structure having a predetermined slope in cross section.

네 번째로, 실리콘 습식식각을 완료한 후, 수십 nm 크기의 직경을 갖는 실리 콘 나노와이어를 제작하기 위해 실리콘 기판에 열산화를 통해 제2 열산화막(160)을 생성시킨다. Fourth, after the silicon wet etching is completed, a second thermal oxide film 160 is formed through thermal oxidation on the silicon substrate to fabricate the silicon nanowires having a diameter of several tens of nm.

다섯 번째로, 실리콘이 2차 열산화되어 생성된 제2 열산화막(160)을 BOE(Buffered Oxide Etchant)에 의한 습식식각방법 또는 플라즈마를 이용한 건식습각방법을 이용하여 제거함으로써, 수십 nm 크기의 직경을 갖는 수 μm 내지 수백 μm 길이의 실리콘 나노와이어(110)를 제작한다.Fifth, the second thermal oxide film 160 formed by the second thermal oxidation of silicon is removed by a wet etching method using BOE (Buffered Oxide Etchant) or a dry wet method using plasma, thereby having a diameter of several tens of nm. To produce a silicon nanowires 110 having a length of several μm to several hundred μm.

상기와 같은 방법으로 실리콘 나노와이어를 제작할 수 있다.Silicon nanowires can be manufactured in the same manner as described above.

하지만, 상기와 같은 종래의 나노와이어는 실리콘이라는 물질에 국한된 방법이므로, 다양한 물질의 나노와이어를 제작함에 있어 어려움이 있다.However, since the conventional nanowires as described above are limited to a material called silicon, there is a difficulty in manufacturing nanowires of various materials.

따라서, 본 발명은 실리콘 나노와이어를 희생층으로 사용하여 다양한 물질을 희생층에 증착시킴으로써 나노와이어를 제작하는 다양한 재질의 나노와이어 제작 방법을 제공함에 본 발명의 목적이 있다.Accordingly, an object of the present invention is to provide a method for fabricating nanowires of various materials for fabricating nanowires by depositing various materials on the sacrificial layer using silicon nanowires as a sacrificial layer.

본 발명의 상기 목적은 실리콘 나노와이어를 제작하는 단계; 상기 실리콘 나노와이어에 나노와이어를 제작하기 위한 재료를 증착시키는 단계; 및 상기 실리콘 나노와이어를 제거하는 단계를 포함하는 나노와이어 제작 방법에 의해 달성된다.The object of the present invention is to produce a silicon nanowire; Depositing a material for fabricating nanowires on the silicon nanowires; And removing the silicon nanowires by the nanowire fabrication method.

이에 앞서, 본 명세서 및 청구범위에 사용된 용어나 단어는 통상적이거나 사 전적인 의미로 한정해서 해석되어서는 아니되며, 발명자는 그 자신의 발명을 가장 최선의 방법으로 설명하기 위해 용어의 개념을 적절하게 정의할 수 있다는 원칙에 입각하여 본 발명의 기술적 사상에 부합하는 의미와 개념으로 해석되어야만 한다.Prior to this, the terms or words used in this specification and claims should not be construed as being limited to the ordinary or dictionary meanings, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention.

따라서, 본 명세서에 기재된 실시예와 도면에 도시된 구성은 본 발명의 가장 바람직한 일실시예에 불과할 뿐이고 본 발명의 기술적 사상을 모두 대변하는 것은 아니므로, 본 출원시점에 있어서 이들을 대체할 수 있는 다양한 균등물과 변형예들이 있을 수 있음을 이해하여야 한다.Therefore, the embodiments described in the specification and the drawings shown in the drawings are only one of the most preferred embodiments of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명의 일실시예에 따른 알루미늄 나노와이어(220) 제작 방법을 나타낸 도면이다.2A to 2C are views illustrating a method of manufacturing aluminum nanowires 220 according to an embodiment of the present invention.

도 2a는 실리콘 기판(200)과 그 위에 떠 있는 구조의 실리콘 나노와이어(210)를 나타낸다.2A illustrates a silicon substrate 200 and a silicon nanowire 210 having a structure floating thereon.

실리콘 나노와이어(210)는 도 1b에 도시된 방법으로 제작이 가능하다.The silicon nanowires 210 may be manufactured by the method illustrated in FIG. 1B.

도 2b는 실리콘 나노와이어(210) 위에 알루미늄을 증착한 것이다. 알루미늄을 실리콘 나노와이어(210) 위에 증착함으로써, 도 2b에 도시된 바와 같이, 알루미늄 나노와이어(220)의 구조물이 형성된다.2B shows aluminum deposited on the silicon nanowires 210. By depositing aluminum over silicon nanowires 210, the structure of aluminum nanowires 220 is formed, as shown in FIG. 2B.

도 2c는 희생층 역할을 하는 실리콘 나노와이어(210)를 선택적으로 제거함으로써, 알루미늄 나노와이어(220)가 제작된다. 실리콘 나노와이어(210)의 선택적 제 거는 XeF2 등의 화학적 건식 식각방법을 이용한다.2C shows that aluminum nanowires 220 are fabricated by selectively removing the silicon nanowires 210 serving as sacrificial layers. Selective removal of the silicon nanowires 210 uses a chemical dry etching method such as XeF 2 .

도 2a 내지 도 2c를 참조하면, 본 발명의 일실시예에 따른 알루미늄 나노와이어(220)의 제작방법은, 첫 번째로, 실리콘 기판(200)에 떠 있는 실리콘 나노와이어(210)를 제작한다.2A to 2C, the method of manufacturing the aluminum nanowires 220 according to an embodiment of the present invention firstly manufactures the silicon nanowires 210 floating on the silicon substrate 200.

두 번째로, 실리콘 나노와이어(210)를 희생층으로 이용하여 상기 희생층 위에 나노와이어로 제작하고자 하는 알루미늄을 증착한다. 또한 상기 알루미늄을 증착하기 전, 실리콘 나노와이어(210)를 산화시키는 공정을 추가하여, 산화막 형태의 희생층을 이용하기도 한다.Secondly, using the silicon nanowires 210 as a sacrificial layer, aluminum to be manufactured as nanowires is deposited on the sacrificial layer. In addition, before the aluminum is deposited, a sacrificial layer in the form of an oxide film may be used by adding a process of oxidizing the silicon nanowires 210.

세 번째로, 상기 희생층을 선택적으로 제거함으로써, 알루미늄 나노와이어(220)를 제작한다. 상기 희생층이 실리콘 산화막 형태의 나노와이어인 경우, 실리콘과 선택성이 없는 재료를 갖는 나노와이어도 용이하게 제작할 수 있다.Third, by selectively removing the sacrificial layer, an aluminum nanowire 220 is manufactured. When the sacrificial layer is a nanowire in the form of a silicon oxide film, nanowires having silicon and a material having no selectivity may be easily manufactured.

상기 방법을 통해 제작된 알루미늄 나노와이어(220)의 선폭과 피치 어레이 수는 희생층으로 사용된 실리콘 나노와이어(210)와 동일하거나 그에 준하므로, 실리콘 나노와이어(210)의 선폭과 피치 어레이 수 및 증착시키는 알루미늄막의 두께를 제어하는 방법으로 알루미늄 나노와이어(220)의 선폭과 피치 어레이 수를 제어할 수 있다. 또한 알루미늄 나노와이어(220)의 두께는 물질의 증착두께에 의해 결정된다.Since the line width and pitch array number of the aluminum nanowires 220 manufactured by the method are the same as or equivalent to the silicon nanowires 210 used as the sacrificial layer, the line width and pitch array number of the silicon nanowires 210 and The line width and pitch array number of the aluminum nanowires 220 may be controlled by controlling the thickness of the deposited aluminum film. In addition, the thickness of the aluminum nanowires 220 is determined by the deposition thickness of the material.

또한 도 2b에서 알루미늄뿐만 아니라, 납, 금, 백금 등의 금속이나 ZnO, GaAs 등의 반도체, 또는 AlO3, SiO2, SiN 등의 절연체 등의 다양한 재료를 증착하여 다양한 재료의 나노와이어를 제작할 수 있다.In addition, in FIG. 2B, nanowires of various materials may be manufactured by depositing various materials such as not only aluminum but also metals such as lead, gold, platinum, semiconductors such as ZnO and GaAs, and insulators such as AlO 3 , SiO 2 , and SiN. have.

도 3은 본 발명의 다른 실시예에 따른 완전히 떠 있지 않은 실리콘 나노와이어를 나타낸 도면이다.FIG. 3 is a view showing completely non-floating silicon nanowires according to another embodiment of the present invention.

도 3을 참조하면, 다양한 재료의 나노와이어를 제작함에 있어, 희생층으로 사용되는 완전히 떠 있지 않은 실리콘 나노와이어(310)를 나타낸다.Referring to FIG. 3, in the fabrication of nanowires of various materials, a completely non-floating silicon nanowire 310 used as a sacrificial layer is shown.

여기서 완전히 떠 있지 않은 실리콘 나노와이어(310)는 도 3에 도시된 바와 같이, 실리콘 나노와이어(310)가 산화막(320)에 의하여 실리콘 기판(300)과 연결되어 있는 구조이다.As shown in FIG. 3, the silicon nanowires 310, which are not completely floating, have a structure in which the silicon nanowires 310 are connected to the silicon substrate 300 by the oxide film 320.

산화막(320)은 도 1b에 도시된 2차 열산화 공정 과정에서 생성된 제2 열산화막을 제거시, 일부만 제거함으로써 생성된다.The oxide film 320 is generated by removing only a part of the second thermal oxide film generated in the second thermal oxidation process shown in FIG. 1B.

또한 완전히 떠 있지 않은 실리콘 나노와이어(310)는 산화막(320)이 아닌 얇은 두께의 실리콘(narrowed silicon)을 사용할 수도 있다. 얇은 두께의 실리콘은 도 1b에 도시된 실리콘 나노와이어의 제작시 식각 또는 열산화 공정의 시간을 조절하여 생성할 수 있다.In addition, the silicon nanowires 310, which are not completely floating, may use thin silicon instead of the oxide layer 320. The thin silicon may be produced by controlling the time of the etching or thermal oxidation process in manufacturing the silicon nanowires shown in FIG. 1B.

완전히 떠 있지 않은 실리콘 나노와이어(310)를 희생층으로 사용함으로써, 도 2a 내지 도 2c에 도시된 방법으로 다양한 재료의 나노와이어를 제작할 때, 상기 재료의 증착시 발생하는 스트레스에 강하기 때문에 더욱 안정적인 제작 공정이 된다.By using the silicon nanowires 310, which are not completely floating, as sacrificial layers, when the nanowires of various materials are manufactured by the method shown in FIGS. 2A to 2C, they are more stable because they are resistant to stress generated during deposition of the materials. It becomes a process.

도 4a는 본 발명의 또 다른 실시예에 따른 Coaxial 구조의 나노와이어(420)를 나타낸 도면이고, 도 4b는 본 발명의 또 다른 실시예에 따른 Triaxial 구조의 나노와이어(430)를 나타낸 도면이다.4A is a diagram illustrating a nanowire 420 having a coaxial structure according to another embodiment of the present invention, and FIG. 4B is a diagram illustrating a nanowire 430 having a triaxial structure according to another embodiment of the present invention.

도 4a를 참조하면, 실리콘 기판(400)에 제작된 실리콘 나노와이어(410)에 나노와이어를 제작하고자 하는 재료를 원자층 증착(Atomic Layer Deposition) 공정을 통해 실리콘 나노와이어(410)를 감싸도록 증착시킨다. 상기 공정을 통해, 실리콘 나노와이어(410)를 제거하지 않고, Coaxial 구조의 나노와이어(420)를 제작할 수 있다.Referring to FIG. 4A, a material for fabricating nanowires is deposited on the silicon nanowires 410 fabricated on the silicon substrate 400 to surround the silicon nanowires 410 through an atomic layer deposition process. Let's do it. Through the above process, the nanowires 420 having a coaxial structure can be manufactured without removing the silicon nanowires 410.

상기 공정은 원자층 증착뿐만 아니라, 등각의(conformal) 증착이 가능한 기타 공정을 사용해도 무방하다.The process may use not only atomic layer deposition but also other processes capable of conformal deposition.

도 4b를 참조하면, 도 4a에 도시된 Coaxial 구조의 나노와이어에 다른 재료를 이용하여 한번 더 원자층 증착 공정을 수행하여 Triaxial 구조의 나노와이어(430)를 제작할 수 있다.Referring to FIG. 4B, the nanowire 430 having the triaxial structure may be manufactured by performing an atomic layer deposition process once again using another material on the coaxial nanowire shown in FIG. 4A.

또한, 상기의 방법에 따라, 복수 개의 재료로 이루어진 구조의 나노와이어 제작도 가능하다.In addition, according to the above method, it is also possible to manufacture nanowires having a structure composed of a plurality of materials.

각 실시예에 따른 다양한 재료의 나노와이어는 떠 있는 구조로써 다른 기판에 손쉽게 트랜스퍼 할 수 있으므로 여러 가지 재료를 갖는 나노와이어 소자 제작에도 이용될 수 있다.The nanowires of various materials according to each embodiment may be used in the fabrication of nanowire devices having various materials because they can be easily transferred to other substrates as floating structures.

또한 각 실시예에 따른 다양한 재료의 나노와이어는 패드부분에 전극을 형성하는 공정을 추가하여 나노와이어 공진기(nanomechanical resonator)를 간편하게 제작할 수 있다.In addition, the nanowires of various materials according to each embodiment can be easily manufactured by adding a process of forming an electrode in the pad portion to form a nanowire resonator.

본 발명은 이상에서 살펴본 바와 같이 바람직한 실시예를 들어 도시하고 설 명하였으나, 상기한 실시예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 본 발명의 기술사상과 아래에 기재될 특허청구범위의 균등범위 내에서 다양한 수정 및 변형이 가능함은 물론이다.Although the present invention has been shown and described with reference to the preferred embodiments as described above, it is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. It is apparent that various modifications and variations are possible within the scope of the technical spirit of the present invention and the equivalent scope of the claims to be described below.

따라서, 본 발명의 나노와이어 제작 방법은 기존의 실리콘 나노와이어를 희생층으로 사용하고, 다양한 재료를 증착하여 나노와어어를 제작함으로써 간단하게 제작할 수 있는 장점이 있고, 다양한 재료의 나노와이어를 제작할 수 있는 효과가 있다.Therefore, the nanowire fabrication method of the present invention has the advantage that it can be easily produced by using the conventional silicon nanowires as a sacrificial layer, by depositing various materials to produce nanowires, and can produce nanowires of various materials. It has an effect.

본 발명의 나노와이어 제작 방법은 희생층으로 사용되는 실리콘 나노와이어를 열산화함으로써, 선택적으로 제거함에 있어 용이한 효과가 있다.The nanowire fabrication method of the present invention has an easy effect in selectively removing the silicon nanowires used as the sacrificial layer by thermal oxidation.

본 발명의 나노와이어 제작 방법은 희생층으로 사용할 수 있는 떠있는 나노와이어를 제작한 후 동일한 방법으로 다양한 재료의 나노와이어를 제작할 수 있는 효과가 있다.The nanowire fabrication method of the present invention has the effect of fabricating nanowires of various materials in the same manner after fabricating floating nanowires that can be used as sacrificial layers.

본 발명의 나노와이어 제작 방법은 완전히 떠 있지 않는 실리콘 나노와이어를 희생층으로 사용함으로써, 재료 증착시 스트레스를 잘 견디고, 안정적인 나노와이어를 제작할 수 있는 효과가 있다.Nanowire fabrication method of the present invention by using a silicon nanowire not completely floating as a sacrificial layer, there is an effect that can withstand the stress during material deposition, and can produce a stable nanowire.

본 발명의 나노와이어 제작 방법은 실리콘 나노와이어에 원자층 증착 공정을 이용하여 쉽고 간단하게 다양한 재료의 나노와이어를 제작할 수 있는 효과가 있다.The nanowire fabrication method of the present invention has an effect of easily and simply fabricating nanowires of various materials using an atomic layer deposition process on silicon nanowires.

본 발명의 나노와이어 제작 방법은 나노공진기(nanomechanical resonator)와 같은 떠 있는 구조의 다양한 재료의 나노와이어를 간단하게 제작할 수 있는 장점이 있다.The nanowire fabrication method of the present invention has an advantage of simply fabricating nanowires of various materials having a floating structure such as a nanoresonator.

Claims (7)

실리콘 나노와이어를 제작하는 단계;Fabricating silicon nanowires; 상기 실리콘 나노와이어에 나노와이어를 제작하기 위한 재료를 증착시키는 단계; 및Depositing a material for fabricating nanowires on the silicon nanowires; And 상기 실리콘 나노와이어를 제거하는 단계Removing the silicon nanowires 를 포함하는 나노와이어 제작 방법.Nanowire manufacturing method comprising a. 제 1항에 있어서,The method of claim 1, 상기 실리콘 나노와이어를 제작한 후, 상기 실리콘 나노와이어를 열산화시키는 단계After fabricating the silicon nanowires, thermally oxidizing the silicon nanowires 를 더 포함하는 나노와이어 제작 방법.Nanowire manufacturing method comprising a more. 제 1항 또는 제 2항에 있어서,The method according to claim 1 or 2, 상기 실리콘 나노와이어는 실리콘 또는 산화막에 의해 실리콘 기판에 연결되어 있는 나노와이어 제작 방법.The silicon nanowires are connected to the silicon substrate by silicon or oxide film. 제 1항에 있어서,The method of claim 1, 상기 재료는 금속, 반도체 또는 절연체인 나노와이어 제작 방법.Wherein said material is a metal, semiconductor, or insulator. 제 4항에 있어서,The method of claim 4, wherein 상기 증착은 원자층 증착을 이용하는 나노와이어 제작 방법.The deposition is a nanowire manufacturing method using atomic layer deposition. 제 5항에 있어서,The method of claim 5, 상기 원자층 증착은 한 번 이상 증착하는 나노와이어 제작 방법.The atomic layer deposition is a nanowire manufacturing method that is deposited more than once. 제 1항에 있어서,The method of claim 1, 상기 실리콘 나노와이어를 제작하는 단계는,Producing the silicon nanowires, 실리콘 기판에 제1 열산화막을 형성하는 단계;Forming a first thermal oxide film on the silicon substrate; 상기 실리콘 기판에 칼럼구조를 형성하는 단계;Forming a column structure on the silicon substrate; 칼럼구조가 형성된 상기 실리콘 기판에 지지기둥 및 나노와이어 구조물을 형성하는 단계;Forming a support column and a nanowire structure on the silicon substrate on which the column structure is formed; 상기 실리콘 기판에 제2 열산화막을 형성하는 단계; 및Forming a second thermal oxide film on the silicon substrate; And 상기 제1 열산화막 및 제2 열산화막을 제거하는 단계Removing the first thermal oxide film and the second thermal oxide film 를 더 포함하는 다양한 재료의 나노와이어 제작 방법.Nanowire manufacturing method of a variety of materials further comprising.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9899473B2 (en) 2015-09-10 2018-02-20 Samsung Electronics Co., Ltd. Method of forming nanostructure, method of manufacturing semiconductor device using the same, and semiconductor device including nanostructure
US10127905B2 (en) 2015-09-10 2018-11-13 Samsung Electronics Co., Ltd. Apparatus and method for generating acoustic model for speech, and apparatus and method for speech recognition using acoustic model

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9899473B2 (en) 2015-09-10 2018-02-20 Samsung Electronics Co., Ltd. Method of forming nanostructure, method of manufacturing semiconductor device using the same, and semiconductor device including nanostructure
US10127905B2 (en) 2015-09-10 2018-11-13 Samsung Electronics Co., Ltd. Apparatus and method for generating acoustic model for speech, and apparatus and method for speech recognition using acoustic model

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