KR20080100903A - Display apparatus and method of manufactruing the same - Google Patents

Abstract

A display device and a method for manufacturing the same are provided to prevent the light leakage and movement of the liquid crystal cell gap by using ball spacers, thereby improving the display quality. A gate wiring(110) is arranged on the first substrate. A common wire is arranged on the first substrate to be adjacent to the gate wiring. A data line(130) intersects with the gate wiring. A thin film transistor(140) is arranged in the intersection area of data line and gate line. A first electrodes of the comb-shaped is connected to the drain electrode of the thin film transistor. Common electrodes are arranged to pixel electrodes by turns while being connected to the common wire. Ball spacers form a group(210), and arranged along the gate line, and common wirings.

Description

DISPLAY APPARATUS AND METHOD OF MANUFACTRUING THE SAME}

1 is a plan view of a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

3 to 7 are plan views and cross-sectional views illustrating a method of manufacturing a display device according to an exemplary embodiment of the present invention.

The present invention relates to a display device and a manufacturing method thereof.

In recent years, technology development of an information processing apparatus for processing a large amount of data and a display apparatus for changing data processed by the information processing apparatus into an image has been made.

The display device is typically a liquid crystal display, an organic light generating device, a plasma display panel, or the like. The liquid crystal display displays an image using liquid crystal, the organic light generating device displays an image using an organic light emitting layer that generates light by a forward current, and the plasma display panel displays an image using plasma.

Among them, the liquid crystal display includes a pair of electrodes spaced apart from each other to form an electric field, and a spacer interposed between the electrodes and a spacer for maintaining a cell gap of the liquid crystal.

The liquid crystal display is divided into a vertical electric field type liquid crystal display device and a horizontal electric field type liquid crystal display device.

In the vertical field type liquid crystal display, electrodes are formed on the pair of substrates facing each other, and the liquid crystal is disposed between the electrodes. For example, vertical field type liquid crystal displays generally operate in normally white mode (eg, TN mode).

In the vertical field type liquid crystal display device which operates in a normally white mode, a ball spacer and a column spacer formed by a patterning process may be used as a spacer to maintain a cell gap of a liquid crystal.

The horizontal electric field type liquid crystal display includes a liquid crystal disposed between a pair of electrodes disposed on one substrate and between the electrodes. For example, the horizontal field type liquid crystal display device operates in a normally black mode.

In a horizontal electric field type liquid crystal display device operating in a normally black mode, ball spacers and column spacers may be used as spacers to maintain cell gaps of liquid crystals.

The ball spacer has an advantage of significantly reducing the number of manufacturing processes of the vertical and horizontal electric field type liquid crystal display devices compared to the column spacer.

However, the ball spacer has a constraint that the light matrix generated from the backlight assembly is blocked by a black matrix (BM) and metal wiring between pixels on which an image is displayed. If the ball spacer is disposed inside the pixel, light leakage may occur due to an abnormal liquid crystal alignment around the ball spacer, causing a decrease in the contrast ratio. In the liquid crystal display operating in the normally black mode, the bright spot is poor. Ball spacers should be formed in the black matrix area.

In addition, even if the ball spacers are disposed between the pixels to prevent display quality degradation due to light leakage, when the ball spacers are disposed at the uneven portions between the signal lines disposed between the pixels, the cell gap of the liquid crystal is uneven. Differences occur in the portion, which causes cell gap staining, which greatly reduces the display quality of the image.

One object of the present invention is to provide a display device that further improves the display quality of an image by preventing light leakage and cell gap change of liquid crystal generated by using a ball spacer.

Another object of the present invention is to provide a method of manufacturing a display device which further improves the display quality of an image by preventing the change of cell gap between light leakage and liquid crystal generated by using a ball spacer.

A display device for realizing an object of the present invention includes a gate wiring disposed on a first substrate, a common wiring disposed adjacent to the gate wiring on the first substrate, a data wiring crossing the gate wiring, and A thin film transistor disposed at an intersection of gate and data lines, comb-shaped first electrodes connected to a drain electrode of the thin film transistor, common electrodes connected to the common line and alternately arranged with the pixel electrodes, and the first electrode Ball spacer groups comprising a plurality of unit ball spacer groups are intermittently disposed along the gate wiring and the common wiring so as to include a second substrate facing the first substrate, and at least partially disposed on the gate and the common wirings. .

According to another aspect of the present invention, there is provided a method of manufacturing a display device, including forming a gate line and a common line adjacent to the gate line on a first substrate, and forming a gate line and a first insulating layer covering the gate line and the common line. Forming a channel pattern overlapping a gate electrode which is a part of the gate wiring, a data wiring having a source electrode connected to the channel pattern, and a drain electrode spaced apart from the source electrode and connected to the channel pattern; The common electrode is connected to the drain electrode through the first contact hole of the second insulating layer exposing a part of the drain electrode, and the pixel electrode has a comb shape and the second contact hole exposes a part of the common wiring. Forming a common electrode connected to a wire and alternately arranged with the pixel electrodes; Preparing a second substrate having a lattice-shaped black matrix covering wirings, common wirings, and data wirings, and maintaining the gate wirings and the common wirings to maintain a constant cell gap between the first and second substrates. The method may include interposing a plurality of unit ball spacer groups to interpose a ball spacer group and attaching the first and second substrates to each other.

Hereinafter, a display device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments. Those skilled in the art can implement the present invention in various other forms without departing from the technical spirit of the present invention.

Display

1 is a plan view of a display device according to an exemplary embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

1 and 2, the display device 300 includes a first substrate 105, a gate wiring 110, a common wiring 120, a data wiring 130, a thin film transistor 140, and a pixel electrode 150. ), The common electrode 160, the second substrate 200, and the ball spacer groups 210.

The first substrate 105 (see FIG. 2) comprises a transparent substrate. For example, the first substrate 105 may be a transparent glass substrate.

The gate wiring 110 is disposed on the first substrate 105. The gate wiring 110 is disposed in a direction parallel to the first direction illustrated in FIG. 1. Although one gate wiring 110 is shown in FIG. 1, the gate wiring 110 is formed in plural numbers according to the resolution of the display device 300. For example, when the resolution of the display device 300 is about 1,280 × 1,024, about 1,024 gate lines 110 are disposed on the first substrate 105 in parallel.

Examples of materials that can be used as the gate wiring 110 include aluminum, aluminum alloys, aluminum-neodymium alloys, copper, tungsten, molybdenum, and the like.

The turn-on signal for driving the thin film transistor 140 to be described later is applied to the gate line 110.

The common wiring 120 is disposed on the first substrate 105. The common wiring 120 is disposed on the same plane as the gate wiring 110, for example, and the common wiring 120 is disposed adjacent to each gate wiring 110. The common wiring 120 disposed adjacent to the gate wiring 110 is disposed in a direction parallel to the first direction. The gate wiring 110 and the common wiring 120 are arranged in parallel with each other on the first substrate 105, for example.

On the other hand, a part of the common wiring 120 has, for example, an extension 121 extending in a closed loop shape along the edge of the pixel displaying the image.

Examples of the material that can be used as the common wiring 120 disposed on the same plane as the gate wiring 110 include aluminum, an aluminum alloy, an aluminum-neodymium alloy, copper, tungsten, molybdenum, and the like. The gate wiring 110 and the common wiring 120 include the same material.

A common level of a constant level is applied to the common line 120.

Referring to FIG. 2, a ball spacer group 210 is disposed on the gate wiring 110 and / or the common wiring 120 to maintain a cell gap between the first substrate 105 and the second substrate 210. . The ball spacer group 210 may be disposed between the gate wiring 110, the common wiring 120, or the gate wiring 110 and the common wiring 120.

In the present embodiment, the ball spacer group 210 may be disposed on the gate wiring 110 or the common wiring 120 by a ball spacer supply unit (not shown).

On the other hand, when all the ball spacer groups 210 are disposed in the concave recessed portions formed between the gate wiring 110 and the common wiring 120, the cell gap of the display device 300 is partially changed to display the display device ( Long smudges may be generated in the line shape.

In order to prevent the ball spacer group 210 from being disposed in the concave recess between the gate wiring 110 and the common wiring 120, the gate wiring 110 has a first area having an area extending from the gate wiring 110. The extension part 112 is disposed, and the second extension part 122 having an area extending from the common wire 120 is disposed in the common wire 120.

The first extension 112 of the gate wiring 110 and the second extension 122 of the common wiring 122 are always kept at a predetermined interval.

If the distance between the first extension 112 of the gate wiring 110 and the second extension 122 of the common wiring 120 is too narrow, parasitic capacitance between the gate wiring 110 and the common wiring 120 May be greatly increased or the gate wiring 110 and the common wiring 120 may be shorted, and between the first extension 112 of the gate wiring 110 and the second extension 122 of the common wiring 120. If the spacing is too wide, the gate spacer 110 may be disposed between the first extension 112 of the gate wiring 110 and the second extension 122 of the common wiring 120. The distance between the first extension part 112 of FIG. 1 and the second extension part 122 of the common wiring 120 is adjusted according to the size and / or resolution of the display device 300.

The gate wiring 110 having the first extension part 112 and the common wiring 120 having the second extension part 122 are insulated by the gate insulating layer 129. The gate insulating layer 129 may be a silicon oxide layer or a silicon nitride layer.

Referring back to FIG. 1, the data line 130 is disposed on the gate insulating layer 129 illustrated in FIG. 2. For example, the data line 130 may be disposed in a second direction crossing the first direction illustrated in FIG. 1. Although one data line 130 is illustrated in FIG. 1, a plurality of data lines 130 are formed according to the resolution of the display device 300. For example, when the resolution of the display device 300 is about 1,280 × 1024, about 1,280 × 3 of the data lines 130 are disposed on the gate insulating layer 129 in parallel.

Examples of the material that can be used as the data line 130 include aluminum, aluminum alloys, aluminum-neodymium alloys, copper, tungsten, molybdenum, and the like.

Data signals having different levels are applied to the data line 130 to display an image.

The thin film transistor 140 is disposed on the gate insulating layer 129 corresponding to the gate wiring 110.

The thin film transistor 140 includes a channel pattern 142, a gate electrode, a source electrode 144, and a drain electrode 145 that are part of the gate wiring 110 overlapping the channel pattern 142.

The channel pattern 142 is disposed on the gate insulating layer 129 overlapping with the gate electrode that is a part of the gate wiring 110. The channel pattern 142 may include an amorphous silicon pattern and an n + amorphous silicon pattern implanted with a high concentration of impurities. The n + amorphous silicon pattern is selectively disposed only below the source electrode 144 and the drain electrode 145.

The source electrode 144 extends from the data line 130 along the gate insulating layer 129 and is electrically connected to the channel pattern 142. The end of the source electrode 144 is arranged in a "U" shape when viewed in plan view.

The drain electrode 145 is disposed on the gate insulating layer 129, and one end of the drain electrode 145 is disposed between the source electrodes 144 having a “U” shape, and one side of the drain electrode 145. The other end opposite to the end is disposed on the common wiring 120.

The passivation layer 147 covering the thin film transistor 140 is disposed on the gate insulating layer 129. Examples of the thin film that can be used as the protective film 147 include a silicon oxide film or a silicon nitride film.

The passivation layer 147 may include a first contact hole 148 exposing a part of the drain electrode 145 of the thin film transistor 140 and a second contact hole exposing a part of the extension 121 of the common wiring 120. 149).

The pixel electrode 150 and the common electrode 160 are disposed on the passivation layer 147, respectively. The pixel electrode 150 and the common electrode 160 are transparent and conductive indium tin oxide (ITO), indium zinc oxide (IZO), or amorphous tin indium oxide (amorphous) to improve the aperture ratio, respectively. ITO, a-ITO), and the like.

A portion of the pixel electrode 150 disposed on the passivation layer 147 is electrically connected to the drain electrode 145 exposed by the first contact hole 148 disposed in the passivation layer 147 and the pixel electrode 150. The rest of the extends into the extension portion 121 of the common wiring 120. The pixel electrode 150 may have a comb shape when viewed in a plan view, and the pixel electrode 150 may have a shape that is bent at least once to improve the reagent angle.

A part of the common electrode 160 disposed on the passivation layer 147 is electrically connected to the extension 121 of the common wiring 120 exposed by the second contact hole 149 disposed in the passivation layer 147. The rest of the common electrode 160 extends into the extension part 121 of the common wiring 120. At this time, the common electrode 160 has a comb shape when viewed on a plane. In addition, each common electrode 160 may be alternately disposed with the pixel electrode 150, and the common electrode 160 may be disposed in parallel with the pixel electrode 150.

Referring to FIG. 2, the second substrate 200 faces the first substrate 105. The second substrate 200 may include, for example, a black matrix 202 and a color filter 204.

The black matrix 202 may comprise chromium, chromium alloys or black resin with high light absorption. The black matrix 202 may have a shape covering the gate wiring 110, the common electrode 120, and the data wiring 130 when viewed in plan view, so that the black matrix 202 may display pixels. And corresponding openings.

The color filter 204 is disposed in the openings of the black matrix 202, respectively. The color filter 204 includes a red color filter for passing red light having a red wavelength length from white light, a green color filter for passing green light having a green wavelength length from white light, and a blue color filter for passing blue light having a blue wavelength length from white light. Alternatively, it may include a white color filter for selectively improving the luminance by passing the white light.

In addition, the second substrate 200 may further include an overcoat layer (not shown) for alleviating the step formed by the black matrix 202 and the color filter 204.

Meanwhile, a liquid crystal (not shown) may be disposed between the first substrate 105 and the second substrate 200, and a cell gap () of the liquid crystal may be disposed between the first substrate 105 and the second substrate 200. At least two ball spacer groups 210 are disposed to reduce the variation of the cell gap).

Each ball spacer group 210 includes a unit ball spacer group 213.

Each ball spacer group 210 may include a plurality of unit ball spacer groups 213, and the number of unit ball spacer groups 213 included in each ball spacer group 210 may be two to four. Alternatively, four or more unit ball spacer groups 213 included in each ball spacer group 210 may be provided. In the present embodiment, the unit ball spacer groups 213 included in each ball spacer group 210 may be, for example, three.

The unit ball spacer groups 213 constituting each ball spacer group 210 are, for example, on the first extension 112 of the gate wiring 110 or the second extension 122 of the common wiring 120. It can be formed intermittently. In the present embodiment, the unit ball spacer group 213 may be intermittently formed on the gate wiring 110, for example.

In detail, two adjacent unit ball spacer groups 213 of the ball spacer group 210 are spaced apart from each other at first intervals. For example, the first spacing between two adjacent unit ball spacer groups 213 forming the ball spacer group 210 may be about 10 μm to about 30 μm.

Meanwhile, a second gap between two adjacent ball spacer groups 210 including each unit ball spacer group 213 is formed to be wider than a first gap, and thus, the unit ball spacer groups 213 may be formed of gate wiring ( Intermittently disposed on the first extension 112 of the 110 or the second extension 122 of the common wiring 120.

The unit ball spacer groups 213 included in each ball spacer group 210 may include about 3 to about 20 ball spacers 213a.

For example, about 3 to about 20 ball spacers 213a are intermittently included on the first extension 112 of the gate wiring 110 or the second extension 122 of the common wiring 120. When the unit ball spacer group 213 is formed intermittently, a part of the intermittently arranged unit ball spacer group 210 may be, for example, recessed in a recess between the gate wiring 110 and the common wiring 120. Although the rest of the unit ball spacer group 213 is disposed on the first extension 112 of the gate wiring 110 or the second extension 122 of the common wiring 120, the first substrate. It is possible to prevent the cell gap between the 105 and the second substrate 200 from being rapidly changed to prevent staining in the form of lines in the display device 300.

In order to prevent spots from being formed in a long line shape in the display device 300, the unit ball spacer groups 213 may be arranged in a zigzag form when viewed in a plan view. When the unit ball spacer groups 213 are arranged in a zigzag form when viewed in a plan view, a part of the unit ball spacers 213 may be disposed in the first extension 112 of the gate wiring 110. The remainder of the unit ball spacer group 213 may be disposed on the second extension 122 of the common wiring 120.

In the present embodiment, it is disclosed that the unit ball spacer 213 is disposed on the first extension 112 of the gate wiring 110 and the second extension 122 of the common wiring 120. The unit ball spacer 213 may be a black matrix 202 of the second substrate 200 corresponding to the first extension 112 of the gate wiring 110 and the second extension 122 of the common wiring 120. It may be arranged on.

Manufacturing method of display device

3 to 7 are plan views and cross-sectional views illustrating a method of manufacturing a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a metal film (not shown) is formed over the entire surface of the first substrate 105, which is a transparent substrate, to manufacture a display device. In this embodiment, examples of the material that can be used as the metal film include aluminum, aluminum alloy, aluminum-neodymium alloy, copper, tungsten, molybdenum and the like. The metal film may be formed by a sputtering process or a chemical vapor deposition process.

A photoresist film (not shown) is formed on the metal film. The photoresist film may be formed by a spin coating process or a slit coating process.

The photoresist film is patterned by a photo process including an exposure process and a developing process to form a photoresist pattern on the metal film.

The metal film is patterned by using the photoresist film as an etching mask, and the gate wiring 110 and the common wiring 120 are formed on the first substrate 105.

The gate wiring 110 formed on the first substrate 105 is formed in a direction parallel to the first direction illustrated in FIG. 3. Although a process of forming one gate wiring 110 is illustrated in FIG. 3, a plurality of gate wirings 110 may be formed on the first substrate 105 according to the resolution of the display device 300. For example, when the resolution of the display device 300 is about 1,280 × 1,024, about 1,024 gate lines 110 are formed on the first substrate 105.

The common wiring 120 is formed together on the first substrate 105 during patterning of the metal film to form the gate wiring 100. Therefore, the common wiring 120 is formed on the same plane as the gate wiring 110, and the common wiring 120 is formed adjacent to each gate wiring 110. The common wiring 120 adjacent to the gate wiring 110 is formed in a direction parallel to the first direction illustrated in FIG. 3.

When the common wiring 120 is formed on the first substrate 105, a part of the common wiring 120 extends in a closed loop shape along the edge of the pixel displaying the image, thereby forming the extension 121.

In the meantime, when the gate wiring 110 and the common wiring 120 are formed, a first extension portion 112 is formed in the gate wiring 110, and a second extension portion 122 is formed in the common wiring 120. do. In this embodiment, a constant gap is formed between the first expansion portion 112 and the second expansion portion 122 when viewed in plan view.

In the present embodiment, when the distance between the first extension 112 of the gate wiring 110 and the second extension 122 of the common wiring 120 is formed too narrowly, the gate wiring 110 and the common wiring are formed. Since the parasitic capacitance may be greatly increased or the gate wiring 110 and the common wiring 120 may be shorted between the 120, the first extension 112 of the gate wiring 110 and the second of the common wiring 120 may be shortened. The distance between the expansion units 122 is adjusted according to the size and / or resolution of the display device 300.

Referring to FIG. 4, after a gate insulating film (not shown) covering the gate wiring 110 and the common wiring 120 is formed, an amorphous silicon layer (not shown) or n + amorphous is heavily doped over the entire gate insulating film. Silicon layers (not shown) are formed sequentially.

A photoresist film is formed on the n + amorphous silicon over the entire area, and the photoresist film is patterned by a photo process including an exposure process and a developing process to form a photoresist pattern on the n + amorphous silicon.

Subsequently, the n + amorphous silicon layer and the amorphous silicon layer are patterned by using the photoresist pattern as an etching mask to form a channel pattern 142.

After the channel pattern 142 is formed, a metal film is formed over the entire gate insulating film.

Examples of the material that can be used as the metal film include aluminum, aluminum alloys, aluminum-neodymium alloys, copper, tungsten, molybdenum and the like.

A photoresist film is formed on the metal film, and the photoresist film is patterned by a photo process including an exposure process and a developing process to form a photoresist pattern on the metal film.

The metal film is patterned by using the photoresist pattern as an etching mask, and the data line 130 and the drain electrode 145 having the source electrode 144 are formed on the gate insulating film.

The data line 130 disposed on the gate insulating layer may be formed in a second direction crossing the first direction illustrated in FIG. 4, and the data line 130 may be formed in the extension portion 121 of the common line 120. It is formed corresponding to the shape. Although one data line 130 is illustrated in FIG. 4, the data line 130 is formed of a plurality of data lines 130 according to the resolution of the display device 300. For example, when the resolution of the display device 300 is about 1,280 × 1024, about 1,280 × 3 data lines 130 are formed on the gate insulating layer 129 in a parallel manner.

In the present embodiment, the process of forming the data wiring 130, the source electrode 144, and the drain electrode 145 after forming the channel pattern 142 on the gate insulating film is disclosed. After forming a layer (not shown), an n + amorphous silicon layer (not shown) doped with a high concentration of impurities, and a metal film, they may be patterned using a single pattern mask.

Subsequently, a passivation film (not shown) covering the data line 130 having the source electrode 144 and the drain electrode 145 is formed on the gate insulating film. Examples of the thin film that can be used as the protective film include a silicon oxide film or a silicon nitride film. The protective film may be formed by a chemical vapor deposition process.

After the protective film is formed, a photoresist film is formed on the protective film, and the photoresist film is patterned by a photo process including an exposure process and a developing process to form a photoresist pattern.

The passivation layer is patterned using a photoresist pattern as an etch mask, and the passivation layer exposes a portion of the first contact hole 148 exposing a portion of the drain electrode 144 and a portion of the extension 121 of the common wiring 120. The second contact hole 149 is formed.

Referring to FIG. 5, a transparent conductive film (not shown) made of a transparent and conductive material, for example, ITO, IZO, or a-ITO, over the entire surface of the protective film on which the first and second contact holes 148 and 149 are formed. Is formed.

A photoresist film is formed on the transparent conductive film, and the photoresist film is patterned by a photo process including an exposure process and a developing process to form a photoresist pattern.

The transparent conductive layer is patterned by using the photoresist pattern as an etching mask, and the pixel electrode 150 and the common electrode 160 are formed on the passivation layer, respectively.

A portion of the pixel electrode 150 formed on the passivation layer is electrically connected to the drain electrode 145 exposed by the first contact hole 148 formed in the passivation layer, and the rest of the pixel electrode 150 is connected to the common wiring 120. Extends into the extension 121. The pixel electrode 150 has a comb shape when viewed in a plan view, and the pixel electrode 150 has a shape that is bent at least once to improve the reagent angle.

On the other hand, a part of the common electrode 160 disposed on the passivation layer is electrically connected to the extension 121 of the common wiring 120 exposed by the second contact hole 149 formed in the passivation layer, and the common electrode 160. The rest of) extends into the extension part 121 of the common wiring 120. At this time, the common electrode 160 has a comb shape when viewed on a plane. In addition, each common electrode 160 may be alternately disposed with the pixel electrode 150, and the common electrode 160 may be disposed in parallel with the pixel electrode 150.

Referring to FIG. 6, the second substrate 200 faces the first substrate 105. In order to manufacture the second substrate 200, a light blocking layer (not shown) made of chromium, chromium alloy, or black resin is formed on the second substrate 200 over its entire surface.

Subsequently, a photoresist film is formed on the light blocking layer over the entire area, and the photoresist film is patterned by a photo process including an exposure process and a developing process to form a photoresist pattern on the second substrate 200.

The light blocking layer is patterned using a photoresist pattern as an etching mask, and is formed on the second substrate 200 to cover the common wiring 120, the gate wiring 110, and the data wiring 130 illustrated in FIG. 4. 202 is formed. The black matrix 202 has a plurality of openings when viewed in a plane.

Subsequently, the opening of the black matrix 202 is patterned with a photoresist film including a photoresist including red cyan dyes or red cyan pigments, and thus a color filter 204 including a red color filter, a green color filter, or a blue color filter. ) Is formed.

In addition, an overcoat layer (not shown) covering the black matrix 202 and the color filter 204 may be further formed on the second substrate 200.

After the first and second substrates 105 and 120 are formed, respectively, a sealing member (not shown) may be disposed along an edge of one of the first substrate 105 and / or the second substrate 200. have.

Referring to FIG. 7, after the first and second substrates 105 and 120 are formed, respectively, the cell gap of the liquid crystal is uniformly set in either the first substrate 105 or the second substrate 200. Ball spacer groups 210 are formed for retention.

The ball spacer group 210 is formed by a ball spacer supply unit (not shown) having a nozzle for ejecting the ball spacer 213a. Arrows at the bottom of FIG. 7 indicate the traveling path of the ball spacer supply unit.

The ball spacer supply unit (not shown) mixes about 3 to about 20 ball spacers 213a with isopropyl alcohol and the like and discharges them first to the right pixel of the first substrate 105 shown in FIG. 7.

In this case, the ball spacer supply unit may intermittently discharge the ball spacers 213a to form the unit ball spacer groups 213 on the first substrate 105.

In the present embodiment, the unit ball spacer groups 213 made of about 3 to about 20 by the ball spacer supply unit are, for example, a first extension portion of the gate wiring 110 of the first substrate 105. 112 or the second extension 122 of the common wiring 120. In the present embodiment, the ball spacer supply unit forms the unit ball spacer group 213a in the first extension 112 corresponding to the right pixel of the gate wiring 110 shown in FIG. 7.

The number of unit ball spacer groups 213 formed on the first extension 112 of the gate wiring 110 of the first substrate 105 or the second extension 122 of the common wiring 120 may be two to four. 2 to 4 unit ball spacer groups 123 may form the ball spacer group 210. A plurality of ball spacer groups 210 including a plurality of unit ball spacer groups 213 may be provided.

In detail, the ball spacer supply unit may include the unit ball spacer groups 213 to extend the first wiring 112 or the common wire 120 of the gate wiring 110 at a first interval from each other to form the unit ball spacer group 213. ) To the second extension 122. For example, the ball spacer supply unit forms the unit ball spacer groups 213 such that the first gap between two adjacent unit ball spacer groups 213 is about 10 μm to about 30 μm.

On the other hand, the ball spacer supply unit forms a second gap between two adjacent ball spacer groups 210 including each unit ball spacer group 213 is wider than the first gap.

In the present embodiment, when the ball spacer supply unit forms the unit ball spacer group 213 intermittently, a part of the intermittently arranged unit ball spacer group 213 is, for example, the gate wiring 110 and the common. Although it may be disposed in the recessed recess between the wirings 120, the rest of the unit ball spacer group 213 may be the first extension 112 of the gate wiring 110 or the second extension of the common wiring 120 ( 122, the cell gap between the first substrate 105 and the second substrate 200 may be prevented from being rapidly changed, and the staining in the form of lines in the display device 300 may be prevented. can do.

Referring to FIG. 8, after the ball spacer group 210 is formed on the first extension 112 of the gate wiring 110 corresponding to the right pixel of FIG. 7, the ball spacer supply unit is shown in FIG. 1. As described above, the unit ball spacer group 213 is formed in the first extension 112 of the gate line 110 corresponding to the right pixel.

On the other hand, in order to prevent staining in the form of lines in the display device 300, the unit ball spacer groups 213 formed by the ball spacer supply unit may be arranged in a zigzag form when viewed in plan view. When the unit ball spacer groups 213 are arranged in a zigzag form when viewed in a plan view, a part of the unit ball spacers 213 may be disposed in the first extension 112 of the gate wiring 110, and the unit The rest of the ball spacer group 213 may be disposed on the second extension 122 of the common wiring 120.

In the present embodiment, the unit ball spacer 213 formed by the ball spacer supply unit is disposed on the first extension 112 of the gate wiring 110 and the second extension 122 of the common wiring 120. In some embodiments, the unit ball spacer 213 may include a second substrate corresponding to the first extension 112 of the gate wiring 110 and the second extension 122 of the common wiring 120. It may be disposed on the black matrix 202 of the 200.

As described above in detail, in the display device having the liquid crystal structure in which the common wiring and the gate wiring are disposed adjacently, the ball spacer is suitable for mounting on the common wiring and the gate wiring in order to precisely maintain the cell gap of the liquid crystal. The expansion unit may be formed, and the ball spacer group including the plurality of ball spacers may be formed intermittently to minimize the cell gap variation of the liquid crystal, thereby greatly improving the display quality of the image.

In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

Claims (20)

A gate wiring disposed on the first substrate; A common wiring disposed on the first substrate and adjacent to the gate wiring; A data line crossing the gate line; A thin film transistor disposed at an intersection of the gate and data lines; Comb-shaped first electrodes connected to the drain electrode of the thin film transistor; Common electrodes connected to the common wiring and alternately arranged with the pixel electrodes; A second substrate facing the first substrate, And a plurality of unit ball spacer groups intermittently arranged along the gate line and the common line such that at least a portion thereof is disposed on the gate and the common line. The display device of claim 1, wherein the unit ball spacer groups are intermittently disposed on the extension portion of the gate line and the common line. The display device of claim 1, wherein the ball spacer groups comprise 2 to 4 unit ball spacer groups. The display device of claim 1, wherein the unit ball spacer groups are arranged in a zigzag shape on the gate line and the common line. The display device of claim 1, wherein the unit ball spacer groups are spaced apart from each other at first intervals, and the ball spacer groups are spaced at a second interval wider than the first interval. The display device of claim 5, wherein the first gap between the unit ball spacer groups is between 10 μm and 30 μm. The display device of claim 1, wherein the unit ball spacer group comprises 3 to 20 ball spacers. The display device of claim 1, wherein some of the ball spacers included in the unit ball spacer group are interposed between the gate line and the common line. The method of claim 1, wherein the second substrate is A grid-shaped black matrix overlapping the gate wiring, common wiring and data wiring; And And a color filter disposed in the opening formed by the black matrix. Forming a gate wiring and a common wiring adjacent to the gate wiring on a first substrate, respectively; Forming a channel pattern overlapping a gate electrode which is a part of the gate wiring on a first insulating layer covering the gate wiring and the common wiring; Forming a data line having a source electrode connected to the channel pattern and a drain electrode spaced apart from the source electrode and connected to the channel pattern; The common electrode is connected to the drain electrode through the first contact hole of the second insulating layer exposing a part of the drain electrode, and the pixel electrode has a comb shape and the second contact hole exposes a part of the common wiring. Forming a common electrode connected to a wiring and alternately arranged with the pixel electrodes; Preparing a second substrate having a grid-shaped black matrix covering the gate wiring, the common wiring and the data wiring; Arranging a ball spacer group by intermittently providing a plurality of unit ball spacer groups along the gate line and the common line to maintain a constant cell gap between the first and second substrates; And And bonding the first and second substrates together. The method of claim 10, wherein in the forming of the gate wiring and the common wiring, the gate wiring and the common wiring include forming an extension, and the ball spacer groups are disposed on the extension. The manufacturing method of the display apparatus characterized by the above-mentioned. The method of claim 10, wherein in the forming of the ball spacer groups, the unit ball spacer groups are formed at mutually first intervals, and the ball spacer groups are spaced at a second interval wider than the first interval. Method for manufacturing a display device. The method of claim 10, wherein the unit ball spacer groups include two to four. The method of claim 10, wherein in the forming of the ball spacer groups, the unit ball spacer groups are formed in a zigzag shape on the gate line and the common line. The method of claim 10, wherein in the forming of the ball spacer groups, the first gap between the unit ball spacer groups is 10 μm to 30 μm. The method of claim 10, wherein in the forming of the ball spacer groups, the unit ball spacer group comprises 3 to 20 ball spacers. The method of claim 10, wherein, in the forming of the ball spacer groups, a part of the ball spacers included in the unit ball spacer group is interposed between the gate wiring and the common wiring. . The method of claim 1, wherein the manufacturing of the second substrate is performed. Forming a lattice-shaped black matrix corresponding to the gate wiring, common wiring and data wiring; And And a color filter formed in each of the openings formed by the black matrix. The method of claim 10, wherein in the forming of the ball spacer groups, the ball spacer groups are formed on the first substrate. The method of claim 10, wherein in the forming of the ball spacer groups, the ball spacer groups are formed on the second substrate.

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