KR20080099688A - Method for forming a metal contact in semiconductor device - Google Patents

Abstract

In a method of forming metal contact which at the same time, exposes the object film which is covered with a plurality of materials which has the different etch rate and the different step height through an etching process using the identical etching mask. The metal contact is formed by the in-situ process in the identical plasma etching chamber. The number of process can be reduced. Provided is the forming method of metal contact of the semiconductor device. A step is for forming a conductive pattern on the substrate(100). A step is for forming a first interlayer insulating film on the substrate including a conductive pattern. A step is for forming the contact plug(113) within the first interlayer insulating film not to be overlapped with the conductive pattern. A step for forming an etch stopping layer(114A) on the substrate including a contact plug. A step for exposing the contact plug to etch the etch stopping layer. A step for forming the capacitor(118) with which the contact plug and bottom electrode are connected. A step for forming the protective film(119A) on the upper electrode of capacitor. A step is for forming a second intermetal dielectric on the substrate including the protective film. A step is for etching the second intermetal dielectric and the etch stopping layer overlapped with the conductive pattern. At the same time, while the second inter metal dielectric is etched through the first etching process and a part of the protective film is exposed. A step is for exposing the upper electrode to etch the protective film exposed through the second etching process. A step is for etching the first interlayer insulating film to expose the conductive pattern through the third etching process.

Description

METHOD FOR FORMING A METAL CONTACT IN SEMICONDUCTOR DEVICE

1A to 1D are cross-sectional views illustrating a method for forming a metal contact of a semiconductor device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 substrate 101 gate insulating film

102 gate conductive film 103 protective film

104: gate 105: spacer

106, 108, 112, 120: interlayer insulating film

107: landing plug 109: conductive film

110: protective film 111: bit line

113: storage node contact plug

114: etching stop film 115: lower electrode

116: dielectric film 117: upper electrode

118: capacitor 119: protective film

121: contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of forming metal contact of a semiconductor device including a cylinder type capacitor.

In the semiconductor memory device having a capacitor on bitline (COB) structure, the metal contact forming process connecting the upper metal line and the lower bit line has a high aspect ratio as the height of the capacitor increases. Many difficulties are emerging. The metal contact refers to a contact for connecting the upper metal wiring and the upper electrode of the capacitor, the bit line of the peripheral circuit region, and the junction region of the transistor, respectively.

In a semiconductor memory device, a capacitor is formed in a concave type and a cylindrical structure, and in a double cylinder type structure, as the upper electrode of the capacitor is formed at a portion relatively close to the lower substrate than the concave type structure, the metal is formed. In the etching process for forming a contact, such a process control is difficult, so problems such as a punch through phenomenon in which the upper electrode of the capacitor is drilled occur. Accordingly, in the cylindrical structure, an amorphous silicon film is formed on the upper electrode as an etch stop layer to protect the upper electrode of the capacitor during the capacitor manufacturing process. As a result, the etching is stopped on the amorphous silicon layer during the etching process, thereby preventing the upper electrode from being damaged.

However, in the method of forming a metal contact of a semiconductor device according to the related art, a process is increased in a separate amorphous silicon film etching apparatus to etch an amorphous silicon film formed on an upper electrode of a capacitor.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and a method of forming a metal contact by simultaneously exposing the target film covered with a plurality of materials having different etch rates with different steps with the same etching mask. An object of the present invention is to provide a metal contact forming method of a semiconductor device capable of reducing the number of processes.

According to an aspect of the present invention, there is provided a semiconductor device for simultaneously exposing a target film covered with a plurality of materials having different etching rates with different steps through an etching process using the same etching mask. In the method for forming a metal contact, using the etching mask, in-situ process in the same plasma etching chamber by selectively supplying the etching gas in accordance with the material in the chamber by etching the material Provided is a method for forming a metal contact of a semiconductor device to expose the target film at the same time.

In addition, the present invention according to another aspect for achieving the above object, forming a conductive pattern on a substrate, forming a first interlayer insulating film on the substrate comprising the conductive pattern, the conductive Forming a contact plug in the first interlayer insulating layer so as not to overlap with the pattern, forming an etch stop layer on the substrate including the contact plug, and etching the etch stop layer to expose the contact plug Forming a capacitor to which the contact plug and the lower electrode are connected, forming a protective film on the upper electrode of the capacitor, and forming a second interlayer insulating film on the substrate including the protective film; Etching the second interlayer insulating layer through a first etching process to expose a portion of the passivation layer; Etching the second interlayer insulating layer and the etch stop layer overlapping the turn; etching the passivation layer exposed through a second etching process to expose the upper electrode; and forming the conductive pattern through a third etching process. And etching the first interlayer insulating layer to expose the exposed portions, wherein the first to third etching processes are performed in-situ in the same chamber. do.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the parts denoted by the same reference numerals throughout the specification represent the same layer, and when the uppercase letters included in each reference number means that the same layer is modified through an etching process.

Example

1A to 1D are cross-sectional views illustrating a method for forming a metal contact of a semiconductor device according to an embodiment of the present invention. Here, a semiconductor memory device is illustrated as an example of the semiconductor devices. In the drawing, 'CELL' represents a cell region in which a memory cell is to be formed, and 'PERI' represents a peripheral circuit region in which a driving circuit for driving the cell is to be formed.

First, as illustrated in FIG. 1A, a plurality of gates 104, gate spacers 105, and junction regions (source and drain) (not shown) are formed in a cell region CELL. In this case, the gate 104, the gate spacer 105, and the junction region are also formed in the peripheral circuit region, although not shown.

The gate 104 is connected to a word line and includes a gate insulating film 101, a gate conductive film 102, and a protective film 103 called a hard mask. The gate insulating film 101 is formed of an oxide film or a stacked structure (oxide film / nitride film) of an oxide film and a nitride film. The gate conductive film 102 may be formed of a polysilicon film, a transition metal such as iron (Fe), cobalt (Co), tungsten (W), nickel (Ni), palladium (Pd), platinum (Pt), and molybdenum (Mo). Or titanium (Ti) or the like or rare earth metals such as erbium (Er), ytterium (Yb), samarium (Sm), yttrium (Y), lanthanum (La), cerium (Ce), terbium (Tb), It is formed of dysprosium (Dy), holmium (Ho), tolium (Tm) and lutetium (Lu). The protective film 103 is formed of a nitride film or an oxide film / nitride film. On the other hand, a gate metal film, for example, WN / Wsix, formed of a metal nitride film, a metal silicide layer, or a laminated structure of the metal nitride film and the metal silicide layer may be further formed on the gate conductive film 102.

The gate spacer 105 is formed of a nitride film, or a structure in which an oxide film and a nitride film are stacked.

Subsequently, an interlayer dielectric (Interlayer Dielectric, ILD1) 106 is formed on the substrate 100 including the gate 104. At this time, the ILD1 106 is formed of USG (Un-doped Silicate Glass), TEOS (Tetra Ethyle Ortho Silicate), HDP (High Density Plasma) film, or doped with impurities, BPSG (BoroPhosphoSilicate Glass), PSG (PhosphoSilicate Glass) Film) or a spin on glass (SOG) film.

Subsequently, the ILD1 106 between the gates 104 is etched to form a landing plug 107 at the etched portion. In this case, the landing plug 107 may be formed by depositing a polysilicon layer, tungsten, aluminum, copper, or the like by a chemical mechanical polishing process, or by a selective epitaxial growing (SEG) process.

Next, an interlayer insulating film (hereinafter referred to as ILD2) 108 is formed on the landing plug 107. At this time, the ILD2 108 is formed of any one material selected from the same materials as the ILD1 106.

Subsequently, the bit line 111 is formed in the cell region CELL and the peripheral circuit region PERI. In this case, the bit line 111 includes a conductive layer 109 and a protective layer 110, and the conductive layer 109 is formed of any one metal selected from transition metals and rare earth metals, and the protective layer 110 is formed of a nitride layer. Form.

Subsequently, an interlayer insulating film (hereinafter referred to as ILD3) 112 is formed on the substrate 100 including the bit lines 111. In this case, the ILD3 112 may be formed in a single layer or a structure in which different materials are stacked, and the material of the ILD3 112 may be formed of any one material of the ILD1 106.

Subsequently, the ILD3 112 and the ILD2 108 are etched to expose the landing plug 107, and then the storage node contact plug 113 is formed at the etched portion. In this case, the storage node contact plug 1163 is formed of any one of a polysilicon film, tungsten, aluminum, and copper.

Next, an etch stop film 114 is formed on the ILD3 112. In this case, the etch stop layer 114 is formed of a material having an etch selectivity with a sacrificial insulating film (not shown) to be formed through a subsequent process-a film serving as a template for forming the lower electrode of the cylinder type capacitor. For example, when the sacrificial insulating film is formed of a silicon oxide film, the sacrificial insulating film is formed of a silicon nitride film (Si ₃ N ₄ ).

Subsequently, the lower electrode 115 of the cylindrical capacitor is formed using the sacrificial insulating film. In this case, the lower electrode 115 is formed of any one metal of a transition metal or a rare earth metal, or formed of a nitride film thereof.

Next, a dielectric film 116 is formed on the inner wall of the lower electrode 115. At this time, the dielectric film 116 is formed of an oxide film, a nitride film, a stacked structure of an oxide film (oxide film / nitride film / oxide film), and a high dielectric film having a dielectric constant of 4 or more. At this time, the high dielectric film includes Al ₂ O ₃ , HfO ₂ , ZrO ₂ .

Next, the upper electrode 117 is formed along the stepped surface of the substrate 100 including the dielectric film 116. In this case, the upper electrode 117 is formed of any one of a transition metal or a rare earth metal, or a nitride film thereof, such as a TiN, TaN, or WN film.

Subsequently, a passivation layer 119 functioning as an etch stop layer is formed on the upper electrode 117. In this case, the passivation layer 119 is preferably formed of a material having a high etching selectivity with the interlayer insulating layer (hereinafter referred to as ILD4) 120 and the upper electrode 117 to be formed through a subsequent process. For example, when the ILD4 120 is formed of a silicon oxide film and the upper electrode 117 is formed of a TiN film, the ILD4 120 is formed of an amorphous silicon film that can bring an etch selectivity to infinity. In addition, the thickness of the passivation layer 119 is determined within a range that is easily etched during the etching process for exposing the upper electrode 117 while protecting the upper electrode 117 during the etching process of the ILD4 120 for forming the metal contact. do. For example, the protective film 119 is formed to a thickness of 200 ~ 500Å.

Next, the ILD 4 120 is formed to cover the protective film 119. In this case, the ILD4 120 may be formed of a single layer or a structure in which different materials are stacked, and the material of the ILD4 120 is formed of any one material of the ILD1 106.

Subsequently, the chemical mechanical polishing process may be performed on the ILD4 120 to be planarized.

Subsequently, as shown in FIG. 1B, a photo process is performed to form an etching mask (not shown) for the metal contact, and then an etching process using the etching mask (hereinafter referred to as a first etching process) is performed. (Hereinafter referred to as a first contact hole) 121 is formed. In this case, the first etching process is performed using a plasma etching equipment, and the etching process is performed under an etching condition having a high etching selectivity with respect to the passivation layer 119. For example, when the protective film 119 is made of an amorphous silicon film, C ₄ F ₆ , C ₄ F ₈ of the fluorocarbon compounds in order to obtain a high etching selectivity to silicon Or a mixture of these gases (C ₄ F ₆ / C ₄ F ₈ ), and in addition, Ar, O ₂ or both gases (Ar, O ₂ ) are added to increase the ion collision to increase the etching rate. You may. In addition, H ₂ may be added to further increase the etching selectivity to silicon.

By performing the first etching process under such etching conditions, only the ILD4 120A is etched in the cell region CELL to expose the passivation layer 119, and the ILD4 120A and the etch stop layer 114A in the peripheral circuit region PERI. ) Is etched to form a first contact hole 121 through which the ILD3 112 is exposed.

Subsequently, as illustrated in FIG. 1C, an etching process (hereinafter, referred to as a second etching process) is performed in-situ in the same etching chamber using the plasma etching equipment used in the first etching process in FIG. 1B as it is. Step) to selectively etch only the protective film 119A. In this case, the second etching process is a mixture of Cl ₂ and O ₂ having a high etching selectivity with respect to the oxide film (Cl ₂ / O ₂ ) or CF ₄ to selectively etch only the amorphous silicon film constituting the protective film 119A Mixture gas of O ₂ and O ₂ (CF ₄ / O ₂ ) may be used, and in addition, Ar or HBr may be further added.

Subsequently, as shown in FIG. 1D, an etching process (hereinafter referred to as a third etching process) is performed in-situ in the same etching chamber using the plasma etching equipment used in the second etching process in FIG. 1C as it is. In this case, the ILD 3 112A and the protective film 110 are selectively etched. In this case, the third etching process is a mixture of C ₄ F ₈ and CH ₂ F ₂ (C ₄ F ₈ / CH ₂ F ₂ to selectively etch the ILD 3 (112A) consisting of an oxide film and the protective film 110 consisting of a nitride film) ), And in addition, Ar, O ₂ or both gases (Ar, O ₂ ) can be added.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, in the exemplary embodiment of the present invention, a method of forming a metal contact of a semiconductor memory device including a cylindrical capacitor is described as an example. However, the target film covered with a plurality of materials having different etching rates while having different steps is the same. Any method may be applied to the method of forming a metal contact exposed simultaneously with an etching mask. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, in the metal contact forming method of simultaneously exposing the target film covered with a plurality of materials having different steps and different etching rates through an etching process using the same etching mask, The number of processes can be reduced by forming metal contacts in an in-situ process in the same plasma etching chamber.

Claims (14)

In the method of forming a metal contact of a semiconductor device to expose the target film covered with a plurality of materials having different steps and different etching rates at the same time through an etching process using the same etching mask, A semiconductor using the etching mask and selectively supplying an etching gas into the chamber according to the material in an in-situ process in the same plasma etching chamber to etch the material to simultaneously expose the target layer. Metal contact formation method of the device. Forming a conductive pattern on the substrate; Forming a first interlayer insulating film on the substrate including the conductive pattern; Forming a contact plug in the first interlayer insulating layer so as not to overlap the conductive pattern; Forming an etch stop layer on the substrate including the contact plug; Etching the etch stop layer to expose the contact plug; Forming a capacitor to which the contact plug and the lower electrode are connected; Forming a protective film on the upper electrode of the capacitor; Forming a second interlayer insulating film on the substrate including the protective film; Etching the second interlayer insulating layer through a first etching process to expose a portion of the passivation layer and etching the second interlayer insulating layer and the etch stop layer overlapping the conductive pattern; Etching the passivation layer exposed through a second etching process to expose the upper electrode; Etching the first interlayer insulating layer to expose the conductive pattern through a third etching process, The first to third etching process is a metal contact forming method of a semiconductor device is performed in-situ process in the same chamber. The method of claim 2, The capacitor is a metal contact forming method of the semiconductor device to form a concave or cylindrical. The method of claim 2, The first to third etching process is a metal contact forming method of a semiconductor device performed by a plasma etching process. The method of claim 2, The protective layer is a metal contact forming method of a semiconductor device to form a different material to have an etching selectivity with the upper electrode. The method of claim 5, wherein The protective film is a metal contact forming method of a semiconductor device formed of an amorphous silicon film. The method of claim 6, And the first and second interlayer insulating layers are formed of a silicon oxide layer. The method of claim 7, wherein The etch stop layer is a metal contact forming method of a semiconductor device formed of a silicon nitride film. The method of claim 8, The first etching process is C ₄ F ₆ , C ₄ F ₈ Or a metal contact forming method of a semiconductor device using a mixed gas (C ₄ F ₆ / C ₄ F ₈ ) thereof. The method of claim 9, The first etching process is a metal contact forming method of a semiconductor device performed by adding Ar, O ₂ or both of these gases (Ar, O ₂ ). The method of claim 8, The second etching process is a metal contact forming method of a semiconductor device using a mixed gas of Cl ₂ and O ₂ or a mixed gas of CF ₄ and O ₂ . The method of claim 8, The third etching process is a metal contact forming method of a semiconductor device using a mixed gas of C ₄ F ₈ and CH ₂ F ₂ . The method of claim 12, The third etching process is a metal contact forming method of a semiconductor device performed by adding Ar, O ₂ or both of these gases (Ar, O ₂ ). The method of claim 2, The conductive pattern is a metal contact forming method of a semiconductor device comprising a nitride film formed on the top layer.

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