KR20080096981A - Display device - Google Patents

Abstract

A display device is provided to increase the viewing angle and pixel charge rate. A plurality of pixels having a first, and a second sub-pixel are arranged to the matrices. A plurality of gate lines is connected to the first and the second sub-pixel, and delivers the gate signal to the first and the second sub-pixel. A plurality of data lines is connected to the first sub-pixel and the second sub-pixel by turns, and delivers data voltage to the first and the second sub-pixel. The first sub-pixel pre-charges data voltage of the other first sub-pixel from data line. The second sub-pixel pre-charges data voltage of the other second sub-pixel from data line. Therefore, data voltage of the pixel in which the sub-pixel following the different gamma curve of 2 follows the respective same gamma curve is pre-charged and the side and charging rate can be secured.

Description

Display device {DISPLAY DEVICE}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of two subpixels in a liquid crystal display according to an exemplary embodiment of the present invention.

3 is an equivalent circuit diagram for one pixel according to an embodiment of the present invention.

4 is a schematic diagram illustrating a pixel array, a signal line array, and a pixel polarity of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a graph illustrating a gamma curve of two subpixels according to an exemplary embodiment of the present invention.

6 is a signal waveform diagram illustrating an operation of a liquid crystal display according to an exemplary embodiment of the present invention.

The present invention relates to a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light to display an image. In such a liquid crystal display, a voltage is applied to two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image.

Among the liquid crystal display devices, the vertical alignment mode liquid crystal display in which the long axis of the liquid crystal molecules are arranged perpendicular to the upper and lower display panels without an electric field applied to the liquid crystal display device has a high contrast ratio and is easy to implement a wide reference viewing angle. Here, the reference viewing angle refers to a viewing angle having a contrast ratio of 1:10 or a luminance inversion limit angle between gray levels.

Means for implementing a wide viewing angle in a vertical alignment mode liquid crystal display include a method of forming a cutout in the field generating electrode and a method of forming a protrusion on the field generating electrode. Since the inclination and the projection can determine the direction in which the liquid crystal molecules are tilted, the reference viewing angle can be widened by using these to disperse the oblique directions of the liquid crystal molecules in various directions.

However, the vertically aligned liquid crystal display device is less lateral visibility than the front visibility. For example, in the case of a patterned vertically aligned (PVA) type liquid crystal display device having an incision, the image becomes brighter toward the side, and in severe cases, the luminance difference between the high grays disappears and the picture may appear clumped. .

To improve this phenomenon, one pixel is divided into two subpixels, two subpixels are capacitively coupled, and one subpixel is directly applied with voltage, and the other subpixel causes voltage drop by capacitive coupling. A method of changing the transmittances by changing the voltages of the two subpixels has been proposed.

However, this method does not exactly match the transmittance of the two subpixels to the desired level, and in particular, the light transmittance is different depending on the color, and thus this cannot be done even though the voltage combination for each color must be different.

Therefore, a method of directly applying respective voltages to two subpixels has been proposed. However, when the frame frequency is increased in such a liquid crystal display, the charging time allocated to each subpixel is shortened, thereby lowering the charging rate of the voltage.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a liquid crystal display device capable of securing side visibility and filling rate.

According to an embodiment of the present invention, a display device is arranged in a matrix, and is connected to a plurality of pixels including first and second subpixels, and the first and second subpixels. A plurality of gate lines that transfer gate signals to the first and second subpixels, and are alternately connected to the first subpixel and the second subpixel, and a data voltage to the first and second subpixels. A first subpixel precharges the data voltage of another first subpixel from the data line, and the second subpixel is another second subpixel from the data line. The data voltage of the pixel is precharged.

The gate signal may have a gate-on voltage when the precharge voltage and the data voltage of the pixel are applied.

The first subpixel and the second subpixel may receive different levels of data voltages with respect to the same gray level.

The first subpixel and the second subpixel may receive the data voltage for one piece of image information.

An odd number of horizontal periods may be located between the precharge voltage application period and the data voltage application period of the pixel.

The gate signal may have a gate-off voltage during one horizontal period between the precharge voltage application period and the data voltage application period of the corresponding pixel.

The number of the data lines may be twice the number of the pixel columns, and the number of the gate lines may be the same as the pixel rows.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

1 is a block diagram of a liquid crystal display according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of two subpixels in a liquid crystal display according to an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. It is an equivalent circuit diagram for one pixel according to an example.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. Connected gray voltage generator 800 and a signal controller 600 for controlling the gray voltage generator 800.

The liquid crystal panel assembly 300, when viewed as an equivalent circuit, includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _2m , and a plurality of pixels PX connected thereto and arranged in a substantially matrix form. It includes. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes the thin film transistor array panel 100 and the common electrode panel 200 facing each other and the liquid crystal layer 3 interposed therebetween.

The display signal lines G ₁ -G _n and D ₁ -D _2m are a plurality of gate lines G ₁ -G _n transmitting gate signals (also called “scan signals”) and data lines D transferring data signals. ₁ -D _2m ). The gate lines G ₁ -G _n extend approximately in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _2m extend substantially in the column direction and are substantially parallel to each other. A pair of data lines D ₁ -D _2m are disposed on both sides of one pixel PX.

An equivalent circuit of the display signal line and one pixel PX is shown in FIG. (SL) is further included.

Each pixel PX includes a pair of subpixels PXa and PXb, and each subpixel PXa / PXb includes a switching element connected to a corresponding gate line GL and data line DLa / DLb. Qa / Qb) and liquid crystal capacitors (Clc _a / Clc _b ) and storage capacitors (Cst _a / Cst _b ) connected thereto. Holding capacitors Cst _{a and} Cst _b can be omitted as necessary.

Referring to FIG. 3, the switching elements Qa / Qb of each of the subpixels PXa and PXb are formed of thin film transistors and the like provided in the thin film transistor array panel 100, and are connected to the gate lines GL, respectively. It is a three-terminal device having a control terminal, an input terminal connected to the data lines DLa / DLb, and an output terminal connected to the liquid crystal capacitors Clc _a / Clc _b and the storage capacitor Cst _a / Cst _b .

As shown in FIG. 2, the liquid crystal capacitor Clc _a / Clc _b has two terminals including the subpixel electrode PEa / PEb of the thin film transistor array panel 100 and the common electrode 230 of the common electrode display panel 200. The liquid crystal layer 3 between the PE and 230 functions as a dielectric. The subpixel electrodes PEa / PEb are connected to the switching elements Qa / Qb, and the common electrode 230 is formed on the entire surface of the common electrode display panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 230 may be provided in the thin film transistor array panel 100. In this case, at least one of the two electrodes PE and 230 may be linear or rod-shaped.

In the storage capacitor Cst _a / Cst _b , which serves as an auxiliary role of the liquid crystal capacitor Clc _a / Clc _b , the storage electrode line SL and the subpixel electrode PEa / PEb provided in the thin film transistor array panel 100 are insulators. Are overlapped with each other, and a predetermined voltage such as the common voltage Vcom is applied to the storage electrode line SL. However, the storage capacitor Cst _a / Cst _b may be formed by the subpixel electrode PE overlapping the shear gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel uniquely displays one of the primary colors (spatial division) or each pixel alternately displays the primary colors according to time (time division) so that the spatial and temporal combination of these primary colors can be achieved. To recognize the desired color. Examples of primary colors include red, green and blue. 3 illustrates that each pixel includes a color filter CF representing one of primary colors in an area of the common electrode display panel 200 as an example of spatial division. Unlike FIG. 3, the color filter CF may be formed above or below the subpixel electrodes PEa / PEb of the thin film transistor array panel 100.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ).

The data driver 500 is connected to the data lines D ₁ -D _2m of the liquid crystal panel assembly 300, and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _2m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300. In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the arrangement of the pixels will be described in detail with reference to FIGS. 4 and 3 to 3.

4 is a diagram illustrating a pixel array and a signal line array of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

Referring to FIG. 4, a liquid crystal panel assembly according to an exemplary embodiment of the present invention includes a pixel electrode PE including a pair of subpixel electrodes PEa / PEb, and a plurality of gate lines G ₁ extending in a horizontal direction. -G _n ), a plurality of data lines D ₁ -D _2m extending in the vertical direction, a first switching element Qa, and a second switching element Qb.

The polarities of the data voltages flowing through the two data lines (for example, D ₁ and D ₂ ) connected to the pair of subpixel electrodes PEa / PEb constituting the pixel electrode PE are opposite to each other. That is, the polarity of the data voltage flowing to the data line D ₁ positioned on the left side of the pixel electrode PE is positive (+), and the polarity of the data voltage flowing to the data line D ₂ positioned on the right side of the pixel electrode PE is measured. The polarity is negative.

Referring to the pixel PX disposed in the first row and the first column of FIG. 4, the gate line G ₁ extends under the pixel and two data lines D ₁ and D ₂ extend to the left and right. The first switching element Qa connected to the first subpixel electrode PEa is connected to the left data line D ₁ , and the second switching element Qa is connected to the second subpixel electrode PEb. Qb) is connected to the right data line D ₂ . Hereinafter, a pixel having such a connection relationship is referred to as a first pixel.

In contrast, referring to the pixels PX disposed in the first row and the second column, the second switching element Qb connected to the left data line D ₃ is connected to the second subpixel electrode PEb. The first switching element Qa connected to the right data line D ₄ is connected to the first subpixel electrode PEa. Hereinafter, a pixel having such a connection relationship is referred to as a second pixel.

The pixels PX arranged in the second row and the first column also have the same connection relationship as the pixels PX arranged in the first row and the second column. That is, the first pixel and the second pixel are alternately arranged in the row direction and the column direction.

As described above, the data lines D ₁ -D _2m surround one pixel PX and are arranged two on the left and right. Therefore, the total number of data lines D ₁ -D _2m is twice the total number of pixel columns.

Since the liquid crystal panel assembly 300 according to an exemplary embodiment has the arrangement as shown in FIG. 4, polarities of the first and second subpixel electrodes PEa and PEb adjacent in the row direction are opposite to each other. The polarities of the first subpixel electrodes PEa adjacent in the column direction are also opposite to each other, and the polarities of the second subpixel electrodes PEb adjacent in the column direction are also opposite to each other.

Next, the operation of the liquid crystal display will be described in detail with reference to FIGS. 5 and 6.

5 is a graph illustrating a gamma curve of two subpixels according to an exemplary embodiment of the present invention, and FIG. 6 is a signal waveform diagram illustrating an operation of a liquid crystal display according to an exemplary embodiment of the present invention.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). The input image signals R, G, and B contain luminance information of each pixel PX, and the luminance is a predetermined number, for example, 1024 (= 2 ¹⁰ ), 256 (= 2 ⁸ ), or 64 (= 2 ⁶ ) It has gray. Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 applies an analog data voltage to the horizontal synchronizing start signal STH and the data lines D ₁ -D _m indicating the start of transmission of the digital image signal DAT for one row of pixels PX. Includes a load signal LOAD and a data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the analog data voltage relative to the common voltage Vcom (hereinafter referred to as " polarity of the data voltage " RVS) may be further included.

Meanwhile, the signal controller 600 converts the input image signals R, G, and B for one pixel PX into output image signals DAT for the two subpixels PXa and PXb. Can be sent to. Alternatively, the gray voltage generator 800 separately sets the gray voltage sets for the two subpixels PXa and PXb and alternately provides them to the data driver 500, or alternately selects them in the data driver 500. Different voltages may be applied to the subpixels PXa and PXb. However, as shown in FIG. 5, the gamma curve of one subpixel PXa has a larger value than the gamma curve of the other subpixel PXb, where the synthetic gamma curves of the two subpixels PXa and PXb are referenced from the front. It is desirable to correct the image signal or create a set of gradation voltages so as to be close to the gamma curve. For example, the composite gamma curve at the front side should match the reference gamma curve at the front that is best suited for this liquid crystal panel assembly 300 and the composite gamma curve at the side will be closest to the reference gamma curve at the front side. .

Referring to FIG. 6, the data driver 500 receives a digital image signal DAT for one row of pixels PX according to a load signal LOAD, and a gray level corresponding to each digital image signal DAT. By selecting the voltage, the digital image signal DAT is converted into an analog data voltage, and then applied to the corresponding data line D ₁ -D _2m when the load signal transitions to a high level.

A data line (D ₁ -D _2m) has two sub-pixels (PXa, PXb) is so connected to alternating rows, the data driver 500 is different gamma curves for each of the data lines (D ₁ -D _2m) The data voltage following is applied alternately in the horizontal period.

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n during the precharge period and the voltage charge period according to the gate control signal CONT1 from the signal controller 600. The switching elements Qa and Qb connected to the lines G ₁ -G _n are turned on. Then, the data voltage applied to the data lines D ₁ -D _2m is applied to the pixel PX through the turned-on switching elements Qa and Qb.

In this case, the precharge period is a period ahead of the voltage charge period, and the gate-off voltage Voff is supplied to the gate lines G ₁ -G _n during an odd horizontal period between the precharge period and the voltage charge period. For example, as shown in FIG. 6, the precharge period may be a horizontal period two horizontal periods earlier than the corresponding pixel row, and the pixel PX charges the data voltage of the pixel PX before two rows as the precharge voltage.

The gamma curves of both subpixels (PXa, PXb) have a large voltage difference at low gray scales, which are sufficient even at low gray scales by precharging data voltages of other subpixels (PXa, PXb) following the same gamma curve as in the present invention. Filling rate can be secured.

Next, when the voltage charging section of the corresponding pixel row starts, the pixel PX receives the corresponding data voltage from the data lines D ₁ -D _2m , and the liquid crystal capacitors Clc _a / Clc _b are precharged. The data voltage is supplied and charged to the data voltage in a short time.

The liquid crystal molecules vary in arrangement depending on the size of the pixel voltage, which is a difference between the common voltage and the data voltage, and thus the polarization of the light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in the transmittance of light by a polarizer attached to the display panel assembly 300, whereby the pixel PX displays the luminance represented by the gray level of the image signal DAT.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all the gate lines G ₁ -G _n. ), The gate-on voltage Von is sequentially applied, and the data voltage is applied to all the pixels PX to display an image of one frame.

As described above, according to the present invention, two sub-pixels that follow different gamma curves may precharge the data voltages of pixels that follow the same gamma curve, thereby ensuring side visibility and charging rate.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (7)

A plurality of pixels arranged in a matrix and including first and second subpixels, A plurality of gate lines connected to the first and second subpixels to transfer gate signals to the first and second subpixels, and A plurality of data lines alternately connected to the first subpixel and the second subpixel, and transferring data voltages to the first subpixel and the second subpixel; Including; The first subpixel precharges the data voltage of another first subpixel from the data line, and the second subpixel precharges the data voltage of the second subpixel from the data line. Display device. In claim 1, The gate signal has a gate-on voltage when the precharge voltage and the data voltage of the pixel are applied. In claim 2, The first subpixel and the second subpixel receive data voltages of different levels with respect to the same gray level. In claim 3, The first subpixel and the second subpixel receive the data voltage for one piece of image information. In claim 4, And an odd horizontal period is positioned between the precharge voltage application period and the data voltage application period of the pixel. In claim 5, And the gate signal has a gate-off voltage for one horizontal period between the precharge voltage application period and the data voltage application period of the pixel. In claim 6, The number of the data lines is twice the number of the pixel columns, and the number of the gate lines is the same as the pixel rows.

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