KR20080090800A - Method for fabricating of semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to suppress gate leaning by removing residues, occurring in forming a gate stack, through a pretreatment procedure using cleaning and oxygen plasma. A method for manufacturing a semiconductor device comprises the following steps of: forming a gate stack on a semiconductor substrate; cleaning the gate stack by using cleaning solution containing ozone; pre-treating the cleaned gate stack by using oxygen plasma; and annealing the pre-treated gate stack. A tunneling layer, a charge trap layer, a blocking layer and a gate electrode are stacked on the semiconductor substrate. The step of cleaning the gate stack comprises the following processes of: firstly cleaning the gate stack by using ozone solution; secondly cleaning the firstly cleaned gate stack by using BOE(Buffered Oxide Etchant) solution; and thirdly cleaning the gate stack by using cleaning solution containing ammonia.

Description

Method for fabricating a semiconductor device

1 to 3 are diagrams for explaining a problem occurring in the process of forming a conventional MANOS device.

4 to 10 are views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device that can improve the efficiency of the electrical characteristics of the device by removing foreign substances generated at the gate interface.

NAND type flash memory devices are nonvolatile memory devices that can be electrically programmed and erased, and are widely used in electronic components that require information retention even when power is cut off. . Most NAND type nonvolatile memory devices have a floating gate structure in which a polysilicon film is capped with an inter-poly oxide (IPO). Floating gate type nonvolatile memory devices are excellent in extensibility and thus, the development of multi-level chips has recently been performed. However, with the recent rapid integration of nonvolatile memory devices using floating gates, attempts have been made on new cell structures to compensate for erase characteristics.

As a kind of new cell structure proposed to meet these demands, a silicon-oxide-nitride-oxide-silicon (SONOS) structure or a metal-aluminum nitride-oxide-semiconductor (MANOS) structure is attempted in a floating gate type nonvolatile memory device. It is becoming. Here, the SONOS device is a nonvolatile memory device having a charge trapping layer, and the MANOS device is a nonvolatile memory device using a metal film in place of silicon that has been used in the conventional gate process.

On the other hand, MANOS devices have a lot of difficulties in proceeding the process as the metal film is used in the gate process unlike the conventional. This will be described with reference to the drawings.

1 to 3 are diagrams for explaining a problem occurring in the process of forming a conventional MANOS device.

Referring first to FIG. 1, a MANOS device includes a structure in which a tunneling layer 102, a charge trap layer 104, a shielding layer 106, and a control gate electrode 110 are stacked on a substrate 100. In the cleaning process performed in the process of forming a MANOS device having such a structure, when a conventional cleaning process condition, that is, a wet station, is applied, the gate profile is determined by the loss of the laminated film and It is difficult to apply due to the cause of contamination. Accordingly, when the cleaning process conditions are relaxed and applied, residual residues (B, FIG. 3) such as titanium nitride (TiNx) or tungsten nitride (WNx) are formed at the gate interface by the nitride layer during gate etching. do. Such residual foreign matter is not found after forming the gate stack, as shown in FIG. 1, and thereafter, it is difficult to be observed and removed after forming the gate spacer. In this case, portions not described in the drawings are the barrier layer 106, the low resistance layer 112, and the hard mask layer 114.

2 and 3, the remaining foreign matter formed at the gate interface is formed more by the nitrogen (N ₂ ) gas used during the subsequent annealing (annealing), so it is difficult to remove such foreign matter under the existing cleaning process conditions Can lose. As described above, the foreign material formed at the gate interface may cause problems such as gate leaning (A, FIG. 2) as the process of forming the MANOS device is performed. The gate tilt phenomenon lowers the erase characteristic, which is an important electrical characteristic of the NAND type nonvolatile memory device, thereby degrading the overall device characteristics. Accordingly, there is a need for a method capable of improving the efficiency of the electrical characteristics of the device by removing foreign substances generated at the gate interface after forming the gate.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a semiconductor device capable of improving efficiency of electrical characteristics of a device by removing foreign substances generated at a gate interface by improving cleaning process conditions performed during gate etching.

In order to achieve the above technical problem, a method of manufacturing a semiconductor device according to the present invention, forming a gate stack on a semiconductor substrate; Performing cleaning of the gate stack using a cleaning solution containing ozone; Performing a pretreatment using an oxygen plasma on the gate stack on which the cleaning is performed; And performing an annealing process on the gate stack on which the pretreatment has been performed.

In the present invention, the gate stack is preferably formed by stacking a tunneling layer, a charge trap layer, a shielding layer, and a gate electrode on a semiconductor substrate.

The performing of the cleaning may include performing a first cleaning on the gate stack using an ozone solution; Performing a secondary cleaning using a BOE solution on the gate stack on which the primary cleaning is performed; And performing a third cleaning using a cleaning solution including ammonia on the gate stack on which the second cleaning is performed.

The primary washing is preferably performed for 30 seconds to 5 minutes by supplying an ozone solution in an amount of 100-500GPM at a temperature of 25 ℃.

The secondary washing may use a BOE solution in which sodium fluoride: hydrofluoric acid is mixed at a concentration of 100: 1 to 300: 1.

The cleaning solution containing ammonia is a mixture of NH ₄ OH, H ₂ O _2, and H ₂ O, and the NH ₄ OH, H ₂ O _2, and H ₂ O may be 1: 2: 40 or 1: 4: It is preferable to mix in 20 ratios.

The third wash is preferably performed for 30 seconds to 5 minutes at a temperature of 30-60 ℃.

The cleaning is preferably carried out in a single type of device.

In the pretreatment using the oxygen plasma, it is preferable to supply hydrogen gas while forming a plasma by applying a bias while supplying oxygen gas and nitrogen gas.

The oxygen gas is preferably supplied in an amount of about 7-10 times greater than the supply amount of nitrogen gas, and the hydrogen gas may be supplied in an amount of 10-50 sccm.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

4 to 10 are views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 4, the tunneling layer 202 is formed by depositing or growing an oxide film having a predetermined thickness on the semiconductor substrate 200. Subsequently, a silicon nitride film is deposited on the tunneling layer 202 to form a charge trap layer 204.

The tunneling layer 202 serves to allow charge carriers such as electrons or holes to be tunneled and injected into the charge trap layer 204 under a certain bias. In this case, the tunneling layer 202 is formed of an insulating film such as silicon oxide film SiO ₂ . The charge trap layer 204 is a layer for trapping electrons or holes injected through the tunneling layer 202. The more uniform the energy level and the more trap sites, the better the trap of the charge, thereby increasing the program and erase speed of the device. . The charge trap layer 204 may be formed of a silicon nitride film.

Referring to FIG. 5, a shielding layer 206 is formed by depositing a material having a high dielectric constant on the charge trap layer 204. The shielding layer 206 serves to block charge from moving from the charge trap layer 204 toward the control gate electrode to be subsequently formed, and is preferably formed of a high dielectric material to improve the operation speed of the cell. The shielding layer 206 may be formed of an oxide film using a chemical vapor deposition (CVD) method. Alternatively, in order to improve the characteristics of the device, a material having a high dielectric constant, for example, an aluminum oxide film (Al ₂ O ₃ ) may be included.

Next, a gate electrode 208 is deposited over the shielding layer 206. Although not shown in the drawings, the gate electrode 208 may be formed including a barrier layer, a low resistance layer, and a hard mask film. The gate electrode 208 serves to apply a bias of a predetermined size so that electrons or holes are trapped from the channel region of the semiconductor substrate 200 to the trap site in the charge trap layer 204. The gate electrode 208 may be formed of a metal film, for example, a tungsten (W) film. The barrier layer is formed of a metal having a high work function to prevent electrons from flowing from the gate electrode to the semiconductor substrate 200 in an erase operation to facilitate the erase operation. Titanium nitride (TiN) may be used as a metal having a high work function. The low resistance layer is to reduce the resistance of the gate electrode 208 and may be formed including a tungsten silicide layer WSix or tungsten nitride WN.

Referring to FIG. 6, an gate mask etch mask (not shown) is formed on the gate electrode 208, and lower layers are sequentially etched using the etching mask to form the gate stack 218. The gate stack 218 includes the tunneling layer pattern 216, the charge trap layer pattern 214, the shielding layer pattern 212, and the gate electrode pattern 210.

Meanwhile, a material forming the charge trap layer pattern 214 during the etching process to form the gate stack 218, for example, titanium nitride (TiNx) or tungsten nitride (WNx) by a nitride film. Residues of may occur. In order to remove the residues generated in this process, the cleaning process is in progress.

In the conventional cleaning process, the residue was removed using a sulfuric acid peroxide mixture (SPM) solution, a buffered oxide etchant (BOE) solution, and a standard clean-1 (SC-1) solution in a wet station apparatus. . However, the SPM solution and the SC-1 solution have a problem that the damage of the metal film is large and can be contaminated. Accordingly, the cleaning solution has to be changed every time the cleaning proceeds, which requires a large amount of consumption of the cleaning solution. In addition, the BOE solution has a large etch amount due to the robot moving time when the cleaning process is performed in the wet station, so that the loss of the hard mask film is large.

Accordingly, a method of weakly proceeding the above-described cleaning process conditions has been proposed, but there is a difficulty in that residual foreign matters are not easily removed. In addition, the remaining foreign matter remaining at the interface of the gate stack 230 is formed more in the process of using nitrogen (N ₂ ) gas in the subsequent annealing process, so that it is not removed by the existing cleaning conditions. In addition, when performing rapid thermal oxide plasma (RTO) using oxygen (O ₂ ) plasma instead of rapid thermal plasma (RTP) after cleaning, foreign matters at the gate stack interface may be removed. However, as the barrier layer, for example, the titanium nitride film is oxidized by the oxygen plasma, as shown in FIG. 9, the gate profile C may be modified, and thus the characteristics of the transistor may be changed. Accordingly, an embodiment of the present invention is to propose a method that can eliminate the problems generated during the cleaning process while removing the residues generated at the gate stack interface.

Referring to FIG. 7, the gate stack 218 is loaded into the cleaning equipment and then cleaned using the cleaning solution including ozone (O ₃ ), the BOE solution, and the cleaning solution including ammonia in the cleaning equipment.

Specifically, the gate stack 218 is loaded into a single type of cleaning equipment. Next, the first cleaning is performed for 30 seconds to 5 minutes by supplying an ozone (O ₃ ) solution into a single type of cleaning equipment. The ozone (O ₃ ) solution may be supplied in an amount of 100-500 gallon per meter (GPM) at a temperature of 25 ° C. Next, a secondary rinse is performed at a temperature of 30-60 ° C. to supply a BOE solution mixed with sodium fluoride (NH ₄ F) and hydrofluoric acid (HF). Here, sodium fluoride (NH ₄ F) and hydrofluoric acid (HF) are preferably mixed at 100: 1 to 300: 1. Subsequently, a third cleaning is performed for 30 seconds to 5 minutes by supplying a cleaning solution containing ammonia (NH ₄ OH). At this time, the cleaning solution containing ammonia (NH ₄ OH) can be used as SC-1 solution, SC-1 solution is NH ₄ OH: H ₂ O ₂ : H ₂ O 1: 2: 40 or 1: 4 It is preferable to mix and use in a ratio of 20.

By this first to third cleaning process, the remaining foreign matter at the interface of the gate stack 218 is removed. As the remaining foreign matter is removed, the etching rate of the metal film can be reduced by using the cleaning solution containing ozone, and the time required to apply the BOE cleaning solution by changing the cleaning equipment from the conventional wet station type equipment to the single type equipment. It can be adjusted exactly. In addition, it is possible to prevent contamination by metal by discharging all of the SC-1 cleaning solution without reuse. In addition, the use of a single type equipment can reduce the consumption of the cleaning solution even if the entire SC-1 cleaning solution is discharged without reuse.

Residual foreign matters generated at the gate stack interface of the cell region and the peripheral circuit region are reduced by the first to third cleaning, but residual foreign material of the low resistance layer pattern interface may remain by a subsequent annealing process. Accordingly, pretreatment using oxygen (O ₂ ) plasma is performed before the annealing process.

Referring to FIG. 8, a preliminary treatment using an oxygen (O ₂ ) plasma is performed on the gate stack 218 where the cleaning is performed to remove residual foreign matter remaining after the cleaning.

Specifically, oxygen (O ₂ ) gas and nitrogen (N ₂ ) gas are supplied to the gate stack 218 where the cleaning is performed. An appropriate bias is then applied to form an oxygen (O ₂ ) plasma in the chamber. In addition, hydrogen (H) gas is supplied onto the gate stack 218. The oxygen gas is preferably supplied in an amount of about 7-10 times greater than the supply amount of nitrogen gas. The bias for applying the plasma is applied at 150-250W, preferably 200W. The oxygen (O ₂ ) plasma is preferably formed thick to 30-40 kPa. In addition, the chamber maintains a pressure of 400-1300 mtorr while forming the oxygen plasma. In addition, hydrogen (H) gas is supplied in an amount of 10-50 sccm to hydrogenate residual impurities by adding an absolute amount to the oxygen / nitrogen gas. The residues can then be combined with hydrogen to remove them better.

Next, an annealing process is performed on the gate stack 218 subjected to the pretreatment using oxygen plasma.

As shown in FIG. 10, residual foreign matters are removed at the interface of the gate stack 218 by a cleaning and pretreatment process using the cleaning solution including ozone (O ₃ ), the BOE solution, and the cleaning solution including ammonia. The gate profile can be formed. Accordingly, the gate leaning phenomenon can be suppressed due to the foreign matter, and the erase characteristic and the program characteristic can be improved, thereby improving the efficiency of the electrical characteristics of the semiconductor operation. Therefore, the manufacturing yield can be improved as well as the reliability of the device can be improved.

As described so far, according to the method of manufacturing a semiconductor device according to the present invention, the remaining foreign substances generated in the process of forming the gate stack are removed using a cleaning process including an ozone cleaning solution and a pretreatment process using an oxygen plasma. The tilting phenomenon can be suppressed, so that the erase characteristic and the program characteristic of the device can be improved. This can increase the efficiency of the electrical characteristics of the inert memory device.

In addition, the cleaning process conditions can be improved to reduce the metal etching rate, to precisely control the cleaning time, and to prevent metal contamination.

Claims (12)

Forming a gate stack over the semiconductor substrate; Performing cleaning of the gate stack using a cleaning solution containing ozone; Performing a pretreatment using an oxygen plasma on the gate stack on which the cleaning is performed; And And performing an annealing process on the gate stack on which the pretreatment has been performed. The method of claim 1, wherein the gate stack, A method of manufacturing a semiconductor device, characterized in that the tunneling layer, the charge trap layer, the shielding layer, the gate electrode is stacked on the semiconductor substrate. The method of claim 1, wherein performing the cleaning comprises: Performing a first wash on the gate stack using an ozone solution; Performing a secondary cleaning using a BOE solution on the gate stack on which the primary cleaning is performed; And And performing a third cleaning using a cleaning solution containing ammonia on the gate stack on which the second cleaning has been performed. The method of claim 3, The primary cleaning is a method of manufacturing a semiconductor device, characterized in that performed for 30 seconds to 5 minutes by supplying an ozone solution in an amount of 100-500GPM at a temperature of 25 ℃. The method of claim 3, The secondary cleaning is a method of manufacturing a semiconductor device, characterized in that the sodium fluoride: hydrofluoric acid is mixed in a concentration of 100: 1 to 300: 1 in a BOE solution. The method of claim 3, The cleaning solution containing ammonia is a method of manufacturing a semiconductor device, characterized in that the solution is a mixture of NH ₄ OH, H ₂ O ₂ and H ₂ O. The method of claim 6, The NH ₄ OH, H ₂ O ₂ and H ₂ O is a method of manufacturing a semiconductor device, characterized in that mixing in the ratio of 1: 2: 40 or 1: 4: 20. The method of claim 3, The third cleaning is a method of manufacturing a semiconductor device, characterized in that performed for 30 seconds to 5 minutes at a temperature of 30-60 ℃. The method of claim 1, And the cleaning is performed in a single type of device. The method of claim 1, Pre-treatment using the oxygen plasma, A method of manufacturing a semiconductor device, characterized in that hydrogen gas is supplied while a plasma is formed by applying a bias while supplying oxygen gas and nitrogen gas. The method of claim 10, The oxygen gas is a semiconductor device manufacturing method, characterized in that for supplying in an amount of about 7-10 times more than the supply amount of nitrogen gas. The method of claim 10, The hydrogen gas is a manufacturing method of a semiconductor device, characterized in that for supplying in an amount of 10-50sccm.

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