KR20080089025A - Semiconductor memory device and method for fabricating the same - Google Patents

Semiconductor memory device and method for fabricating the same Download PDF

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Publication number
KR20080089025A
KR20080089025A KR1020070031986A KR20070031986A KR20080089025A KR 20080089025 A KR20080089025 A KR 20080089025A KR 1020070031986 A KR1020070031986 A KR 1020070031986A KR 20070031986 A KR20070031986 A KR 20070031986A KR 20080089025 A KR20080089025 A KR 20080089025A
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KR
South Korea
Prior art keywords
fuse box
fuse
region
forming
insulating film
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Application number
KR1020070031986A
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Korean (ko)
Inventor
강정규
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070031986A priority Critical patent/KR20080089025A/en
Publication of KR20080089025A publication Critical patent/KR20080089025A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The present invention is to provide a semiconductor memory device and a method of manufacturing the same for preventing the crack of the fuse due to the stress of the laminated structure adjacent to the fuse box during the fuse box forming process, the present invention is A substrate having a fuse box region and having a protrusion formed at the center of the fuse box region, a fuse formed along a step by the protrusion on the substrate, an insulating film formed on the fuse, and an insulating film of the fuse box region are partially removed. And a fuse box formed, wherein the insulating film has a thicker thickness at the edge portion of the fuse box region than at the center portion of the fuse box region.

Description

Semiconductor memory device and manufacturing method therefor {SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME}

1 is a plan view illustrating a fuse of a general semiconductor memory device.

2 is a cross-sectional view of a fuse of a semiconductor memory device according to the prior art;

3 is a photograph showing that cracks are generated at an edge portion of a fuse box of a semiconductor memory device according to the related art.

4 is a cross-sectional view of a fuse of a semiconductor memory device according to an embodiment of the present invention.

5A through 5E are cross-sectional views illustrating a method of manufacturing a semiconductor memory device in accordance with an embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

102, 58A; fuse

111: fuse box

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technology, and more particularly, to a semiconductor memory device and a method of manufacturing the same for preventing a crack of a fuse due to stress of a stacked structure adjacent to a fuse box during a fuse box forming step.

In the manufacture of a semiconductor device, especially a memory device, if any one of a number of fine cells is defective, the semiconductor device does not function as a memory and thus is treated as a defective product. However, even though only some cells in the memory have failed, discarding the entire device as a defective product is an inefficient process in terms of yield.

Accordingly, the yield improvement is achieved by replacing a defective cell by using a preliminary memory cell (hereinafter, referred to as a "redundancy cell") previously installed in the memory device.

In a repair operation using a redundancy cell, a spare row and a spare column are pre-installed in each cell array, and defective defective memory cells are spared in row / column units. It proceeds in the manner of laziness to memory cells.

In detail, after the wafer processing is completed, a program that selects a defective memory cell through a test and replaces the corresponding address with the address signal of the spare cell is performed in the internal circuit. Therefore, when an address signal corresponding to a bad line is input, the selection is changed to a spare line instead.

Among the above-described program methods, the most widely used method is a method of burning off a wire with a laser beam. The wiring broken by the laser irradiation is called a fuse, and the broken part and the area | region surrounding it are called a fuse box.

1 is a plan view illustrating a fuse of a conventional semiconductor memory device, and FIG. 2 is a cross-sectional view of a fuse of a semiconductor memory device according to the related art, and is taken along line A-A of FIG. 1.

1 and 2, a plurality of fuses FUSE 12 are formed in a line / space form on the substrate 10 on which the insulating film 11 is formed. The fuse 12 is formed of, for example, a laminated film of the TiN film 12A and the polysilicon film 12B.

A first interlayer insulating film 13 is formed on the fuse 12, and a first metal wiring 15 connected to the fuse 12 is formed through the first contact 14 penetrating the second interlayer insulating film 13. An interlayer insulating film 16 is formed. At this time, the second interlayer insulating film 16 is formed by depositing a thickness capable of completely applying the upper portion of the first metal wiring 15. Next, the second contact 17 is formed in the second interlayer insulating film 16, and the second metal wiring 18 connected to the second contact 17 is formed to completely cover the outside of the fuse 12. It forms a guiding ring.

The third interlayer insulating film 19 and the SWP (Stable Surface Wave Plasma) film 20 are formed on the entire surface, and the SWP film 20 and the interlayer insulating films 19 and 16 of the fuse box region are formed by a SWP process. 13 is etched to form a fuse box 21. In this case, the etching process of the SWP film 20 and the interlayer insulating films 19, 16, and 13 is performed such that the first interlayer insulating film 13 having a predetermined thickness remains on the upper side of the fuse 12.

However, in the semiconductor memory device including the fuse according to the related art described above, a crack is caused in the edge portion of the fuse box as described below, thereby causing the fuse to be cut undesirably, thereby resulting in the quality of the semiconductor memory device. And there is a problem that the yield is lowered.

Specifically, cracks are caused in the edge portion E of the fuse box 21 due to stress between layers forming the laminated structure outside the fuse box 21, and as a result, the fuse is undesirably cut. The quality and yield of a semiconductor device will fall.

FIG. 3 is a photograph showing cracks generated at an edge portion of a fuse box of a semiconductor memory device according to the prior art. FIG. 3 (a) is a planar photograph of a fuse part according to the prior art, and FIG. It is a cross-sectional photograph which shows the edge part of the fuse box which concerns on technology.

Referring to FIGS. 3A and 3B, cracks are generated at edge portions of the fuse box, and thus, the fuses are cut.

Accordingly, an object of the present invention is to provide a semiconductor memory device and a method of manufacturing the same, which are proposed to solve the above-mentioned problems of the related art and can prevent an undesired fuse from being cut during the fuse box forming process. .

According to an aspect of the present invention, there is provided a substrate having a fuse box region and a protrusion formed at a central portion of the fuse box region, a fuse formed along a step by the protrusion on the substrate; An insulating film formed on the fuse, and a fuse box formed by removing a portion of the insulating film of the fuse box region, wherein the insulating film has a thicker thickness at an edge portion of the fuse box region than at a central portion of the fuse box region. A semiconductor memory device is provided.

According to another aspect of the present invention, there is provided a method including providing a substrate having a fuse box region, forming a first insulating film having a protrusion at a central portion of the fuse box region on the substrate; Forming a fuse on the first insulating film, forming a second insulating film on the fuse, and forming a fuse box by removing a portion of the second insulating film in the fuse box region. A method of manufacturing a memory device is provided.

According to another aspect of the present invention, there is provided a substrate having a cell region and a fuse box region, and forming a first etch stop layer and a first interlayer dielectric layer on the substrate. And forming a second etch stop layer on the fuse box region, forming a second interlayer dielectric layer on the cell region and the fuse box region, and forming the second interlayer dielectric layer and the second interlayer dielectric layer on the cell region. Patterning a first interlayer insulating film to form a trench, and patterning the second interlayer insulating film of the fuse box region to form a protrusion in a central portion of the fuse box region, forming a capacitor lower electrode on the inner side of the trench, Forming a dielectric film on the cell region where the electrode is formed, and forming the capacitor upper electrode on the cell region and the fuse box region. Forming an upper electrode film, patterning the upper electrode film to form a capacitor upper electrode in the cell region, and forming a fuse in the fuse box region, and forming a third interlayer insulating film on the entire surface including the fuse And forming a fuse box by removing a portion of the third interlayer insulating film in the fuse box region.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

4 is a cross-sectional view illustrating a fuse of a semiconductor memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 4, a semiconductor memory device according to an embodiment of the present invention may include a substrate 100 having a fuse region including a region in which a fuse box is to be formed (hereinafter, referred to as a “fuse box region”) and a fuse box region. The second insulating film 103 formed on the uppermost portion, the first insulating film 101 formed on the substrate 100 and having a protrusion below the central portion of the fuse box region, and formed along the step by the protrusion of the first insulating film 101. A fuse 102 is included, and a second insulating layer 103 is positioned on the fuse 102.

When the semiconductor memory device is a DRAM, the fuse 102 is formed by stacking a conductive film for an upper electrode (not shown) of a capacitor formed in a cell region, for example, a TiN film 102A and a polysilicon film 102B. The film is formed using a film, and protrudes from the center portion of the fuse box region as it is formed along a step caused by the protrusion of the first insulating film 101.

The outer side of the fuse box region is formed on the first contact 104 and the second insulating film 103 penetrating through the second insulating film 103 and the fuse 102 and is connected to the fuse 102 through the first contact 104. The second metal wire 105 connected to the first metal wire 105 via the first metal wire 105 to be connected, the second contact 107 connected to the upper portion of the first metal wire 105, and the second contact 107. A guide ring made of 108 is formed to surround the outside of the fuse 102.

In addition, reference numerals 106, 109, 110, and 111 which are not described represent a third insulating film, a fourth insulating film, a Stable Surface Wave Plasma (SWP) film, and a fuse box, respectively, and the fuse box 111 is a SWP film 110; The insulating layers 109, 106, and 103 are formed by etching a predetermined portion, and an insulating layer 103 having a predetermined thickness remains under the fuse box 111.

As described above, the fuse 102 according to the present invention is formed along the step by the protrusion of the first insulating film 101 to protrude from the center portion of the fuse box 111. Accordingly, the second insulating film 103 has a thin thickness at the center portion of the fuse box 111 and has a thick thickness at the edge portion of the fuse box 111.

The thin second insulating layer 103 in the center of the fuse box 111 is formed to have a thickness for cutting the fuse 102, and the fuse 102 is cut through this portion during repair.

The thick second insulating layer 103 of the edge portion of the fuse box 111 is formed to have an increased thickness than the conventional one in order to prevent fuse cracks at the edge portion of the fuse box 111. Stress between the layers forming the laminated structure outside the box 111 is alleviated to reduce crack generation. Even if cracks are generated at the edge portion of the fuse box 111, the crack does not proceed to the fuse 102 without causing cracks. It stops at the insulating film 103, preventing unwanted fuse cutting.

A case where the method of manufacturing the semiconductor memory device according to the present invention is applied to a process of manufacturing a DRAM (Dynamic Random Access Memory) of a semiconductor memory device will be described as an example.

5A through 5E are cross-sectional views illustrating a method of manufacturing a semiconductor memory device in accordance with an embodiment of the present invention.

In each drawing, the first drawing from the left shows a process cross-sectional view of a cell region cut in the bitline direction (X axis), and the second drawing shows a process cross-sectional view of a cell region cut in the wordline direction (Y axis). The second figure shows a process cross section of the fuse box region.

As shown in FIG. 5A, a substrate 50 having a cell region and a fuse box region and having a predetermined substructure formed thereon is provided.

The substructure includes a word line 31, a landing plug 34, a bit line 35, a storage node contact 40, and the like, which are formed through a conventional DRAM manufacturing process. same.

First, an isolation region 30 is formed on the substrate 50 to define an active region, a recess is formed in the active region defined in the cell region, and the gate oxide layer 31A is formed on the substrate 50 on which the recess is formed. And a word line 31 having a structure in which a polysilicon film 31B, a metal silicide film 31C, and a gate hard mask 31D are stacked. Subsequently, the word line spacers 32 are formed on the sidewalls of the word lines 31, and then an insulating layer 33 is formed on the entire surface including the word lines 31 and etched to form trenches (not shown). Subsequently, the landing plug 34 is formed by filling a polysilicon film in the trench. Next, an insulating film 35 is formed on the word line 31, the insulating film 33, and the landing plug 34, and the bit insulating layer 35 is etched to expose the upper portion of the landing plug 34. (Not shown) is formed. A barrier metal layer 36A, a bit line metal layer 36B, and a bit line hard mask layer 36C are stacked and patterned in the bit line contact hole to form a bit line 36 connected to the landing plug 35. . At this time, the bit line 36 and the word line 31 are arranged in a direction crossing each other. Subsequently, bit line spacers 37 are formed on the sidewalls of the bit lines 36, and an insulating film 38 is formed in the cell region and the fuse box region. Next, the insulating layers 38 and 35 are etched by a self alignment contact (SAC) process to form a storage node contact hole (not shown) that exposes the remaining landing plugs 34 not connected to the bit lines 36. . The spacer 39 is formed on the sidewall of the storage node contact hole, and the storage node contact 40 is formed by filling a conductive layer in the storage node contact hole.

The first etch stop layer 51 and the first interlayer insulating layer 52 are stacked on the substrate 50 on which the above-described lower structure is formed.

The first etch stop layer 51 is used as an etch stopper in an etching process for forming a cylindrical storage node forming frame, and may be formed of a nitride film. The first interlayer insulating film 52 can be formed of an oxide film.

Subsequently, as illustrated in FIG. 5B, a second etch stop layer 53 is formed on the first interlayer insulating layer 52. The second etch stop layer 53 may be formed of a nitride layer.

Subsequently, as shown in FIG. 5C, the second etch stop layer 53 formed in the cell region is removed, and the second interlayer insulating layer 54 is formed on the entire surface.

The second interlayer insulating film 54 is provided to form a cylindrical storage node formed in the cell region together with the first interlayer insulating film 52 and may be formed of an oxide film. Preferably, it is formed of a PE-TEOS film.

Next, as shown in FIG. 5D, a trench 55 is formed in the second interlayer insulating film 54 and the first interlayer insulating film 52 in the cell region, and the second interlayer insulating film 54 in the fuse box region is fused. By leaving only the central portion of the box area, it constitutes a protrusion.

The trench 55 and the protrusion may be simultaneously formed through one etching process using a single mask. In this case, in order to form a desired pattern through a single etching process in the cell area and the fuse box area having different thicknesses of the insulating layer to be etched, the first etch stop layer 51 may be the second etch stop in the fuse box area. Membrane 53 is used as an etch stopper.

Subsequently, a capacitor lower electrode 56 is formed on the inner surface of the trench 55, and a dielectric film 57 is formed on the cell region including the trench 55.

Subsequently, as shown in FIG. 5E, a conductive film such as a stacked film of a TiN film and a polysilicon film is formed on the cell region and the fuse box region, and patterned to form a capacitor upper electrode 58A in the cell region. A fuse 58B is formed in the fuse box area.

Next, an insulating film 59 is formed on the cell region and the fuse box region.

Subsequently, although not shown, a first metal wiring connected to the fuse 58B is formed through a first contact penetrating through the insulating film 59 outside the fuse box region.

Then, another insulating film is formed over the entire surface, and then a second contact for contacting the second metal wire to the lower metal wire is formed in another insulating film outside the fuse box region. Then, by forming the upper metal wiring connected to the second contact, a guide ring is formed to completely surround the outside of the fuse box region.

Here, the first contact and the second contact are formed at the first metal contact and the second metal contact process of the cell region, respectively, and the first metal wire and the second metal wire are respectively metal-1 and metal-2 of the cell region. It can form at the time of a process.

Then, another insulating film and a SWP (Stable Surface Wave Plasma) film are formed on the entire surface, and the SWP film and the insulating films are etched in the upper portion of the fuse box region by a SWP process to form a fuse box. At this time, the etching process of the SWP film and the insulating film is performed such that the insulating film 59 of a predetermined thickness remains on the upper side of the fuse 58B.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects are obtained.

By forming a fuse on a substrate on which a protrusion is formed at the center of the fuse box area, the fuse at the edge of the fuse box area is positioned lower than the fuse at the center of the fuse box area, which is a portion cut by laser irradiation. The remaining insulating film becomes thicker at the edge portion than at the fuse box center portion.

Therefore, even when stress due to the stacked structure adjacent to the fuse box is concentrated at the edge of the fuse box during the fuse box forming process, the impact is alleviated by the thick insulating layer at the edge, thereby reducing the occurrence of cracks. The cracks do not proceed to the fuse but are stopped in the insulating film, thereby preventing unwanted fuse cutting, thereby improving the quality and yield of the semiconductor memory device.

Claims (11)

A substrate having a fuse box region and a protrusion formed at a central portion of the fuse box region; A fuse formed on the substrate along a step by the protrusion; An insulating film formed on the fuse; A fuse box formed by partially removing the insulating layer of the fuse box region; And the insulating film has a thickness thicker at an edge portion of the fuse box region than at a center portion of the fuse box region. The method of claim 1, And an insulating film having an uppermost portion of the substrate having a protrusion at a central portion of the fuse box region. The method of claim 1, And a guide ring surrounding the outer side of the fuse outside the fuse box region. Providing a substrate having a fuse box region; Forming a first insulating film having a protrusion at the center of the fuse box region on the substrate; Forming a fuse on the first insulating film; Forming a second insulating film on the fuse; Removing a portion of the second insulating layer in the fuse box region to form a fuse box Method of manufacturing a semiconductor memory device comprising a. The method of claim 4, wherein And forming the fuse using the same material as the upper electrode of the capacitor formed in the cell region outside the fuse box region. The method of claim 5, wherein A method of manufacturing a semiconductor memory device, wherein the fuse is formed of a laminated film of a TiN film and a polysilicon film. Providing a substrate having a cell region and a fuse box region; Stacking a first etch stop layer and a first interlayer dielectric layer on the substrate; Forming a second etch stop layer on the fuse box region; Forming a second interlayer insulating film on the cell region and the fuse box region; Patterning the second interlayer dielectric layer and the first interlayer dielectric layer in the cell region to form a trench, and patterning the second interlayer dielectric layer in the fuse box region to form protrusions in a central portion of the fuse box region; Forming a capacitor lower electrode on the inner side of the trench and forming a dielectric film on the cell region in which the lower electrode is formed; Forming an upper electrode layer on the cell region and the fuse box region to form the capacitor upper electrode; Patterning the upper electrode layer to form a capacitor upper electrode in the cell region and forming a fuse in the fuse box region; Forming a third interlayer insulating film on the entire surface including the fuse; And Forming a fuse box by removing a portion of the third interlayer insulating layer in the fuse box region; Method of manufacturing a semiconductor memory device comprising a. The method of claim 7, wherein The first etch stop layer and the second etch stop layer are formed of a nitride film, and the first interlayer dielectric layer and the second interlayer dielectric layer are formed of an oxide film. The method of claim 8, A method of manufacturing a semiconductor memory device, wherein the second interlayer insulating film is formed of a PE-TEOS film. The method of claim 7, wherein And forming the trench of the cell region and the protrusion of the fuse box region at the same time. The method of claim 10, And using the first etch stop layer in the cell region and the second etch stop layer in the fuse box region as an etch stopper during the patterning process for forming the trench and the protrusion.
KR1020070031986A 2007-03-30 2007-03-30 Semiconductor memory device and method for fabricating the same KR20080089025A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106876326A (en) * 2017-02-14 2017-06-20 上海华虹宏力半导体制造有限公司 Integrated circuit with laser fuse and forming method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106876326A (en) * 2017-02-14 2017-06-20 上海华虹宏力半导体制造有限公司 Integrated circuit with laser fuse and forming method thereof

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