KR20080088974A - Transistor and method for manufacturing the same - Google Patents

Transistor and method for manufacturing the same Download PDF

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Publication number
KR20080088974A
KR20080088974A KR1020070031910A KR20070031910A KR20080088974A KR 20080088974 A KR20080088974 A KR 20080088974A KR 1020070031910 A KR1020070031910 A KR 1020070031910A KR 20070031910 A KR20070031910 A KR 20070031910A KR 20080088974 A KR20080088974 A KR 20080088974A
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KR
South Korea
Prior art keywords
gate
grooves
active region
region
forming
Prior art date
Application number
KR1020070031910A
Other languages
Korean (ko)
Inventor
차선용
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070031910A priority Critical patent/KR20080088974A/en
Publication of KR20080088974A publication Critical patent/KR20080088974A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Abstract

According to the present invention, a transistor and a method of manufacturing the same include a semiconductor substrate having a plurality of grooves formed in a line-and-space shape along a channel width direction on an active region surface, and irregularities on a semiconductor substrate including the active region having the plurality of grooves. And a gate formed in a direction perpendicular to the grooves to have a channel, and a junction region formed in the substrate surface on both sides of the gate.

Description

Transistor and Method for Manufacturing the Same

1 is a plan view showing a transistor and a method of manufacturing the same according to an embodiment of the present invention.

2A to 2C are cross-sectional views illustrating transistors and a method of manufacturing the same according to embodiments of the present invention, corresponding to lines A-A ', B-B', and C-C 'of FIG.

3A to 3C are cross-sectional views illustrating transistors and manufacturing methods thereof according to embodiments of the present invention corresponding to lines A-A ', B-B', and C-C 'of FIG.

Explanation of symbols on the main parts of the drawings

100, 200, 300: active region 102: device isolation region

104: gate line 206, 306: device isolation film

208 and 308: Protruding patterns 210 and 310: Gate insulating film

212 and 312: Gate conductive film 314. 314: Gate hard mask film

216, 316: projection gate 318: etching mask

220, 320: junction area

The present invention relates to a transistor and a method of manufacturing the same, and more particularly, to a transistor capable of improving the operating current of the transistor and a method of manufacturing the same.

Recently, as the design rule of the highly integrated semiconductor device is rapidly reduced to 100 nm or less, the channel length and width of the transistor are correspondingly reduced, and the doping concentration to the junction region is increased, thereby increasing the electric field. As the increase, the junction leakage current increases. As a result, the gate's controllability is degraded to cause a short channel effect in which the threshold voltage (Vt) is drastically reduced, and the junction leakage current increases as the electric field increases to refresh. Deterioration of device characteristics is caused, such as deterioration of characteristics.

More specifically, the short channel effect may cause a so-called bit failure in which an undesired gate is turned on during an operation of reading and writing data in a cell region transistor. In the case of a transistor in the peripheral circuit region, the transistor operation speed is abnormally increased, which may cause a malfunction.

As a result, it is difficult to obtain a threshold voltage value required by a high density device with a conventional planar transistor structure, which leads to a limit in improving refresh characteristics. Accordingly, research on the idea of realization of a gate having a three-dimensional channel structure capable of expanding a channel region and actual process development studies are being actively conducted.

Accordingly, the most common method of extending the channel region to increase the operating current of the transistor is to reduce the channel length and increase the channel width.

However, as is well known, the method of reducing the channel length and increasing the channel width to increase the operating current of the transistor reduces the short channel margin, and in the device of 100 nm or less, As the length of the channel decreases, it is difficult to use it as a method of increasing the operating current due to the increase in mobility deterioration.

In addition, since the increase in the channel width leads to the increase in the area of the semiconductor chip, it is difficult to apply the method of increasing the operating current of the transistor in the manner as is well known.

Meanwhile, in the field of logic devices, a fin gate having a channel having a three-dimensional structure has been recently proposed, but it is difficult to use a portion having a large channel width due to the principle of operation.

That is, it is difficult to use for transistors having various kinds of channel widths, and the problem occurs that the effect decreases rapidly as the channel width increases.

Accordingly, the present invention provides a transistor capable of increasing short channel margin and a method of manufacturing the same.

In addition, the present invention provides a transistor capable of increasing the operating current of the transistor and a method of manufacturing the same.

A transistor according to the present invention includes a semiconductor substrate having a plurality of grooves formed in a line and space shape along a channel width direction on an active region surface; A gate formed in a direction perpendicular to the grooves so as to have an uneven channel on the semiconductor substrate including the active area having the plurality of grooves; And a junction region formed in the substrate surface on both sides of the gate.

The groove is formed in the entire area of the active region.

The groove is selectively formed only in the portion of the active region where the gate is formed.

The grooves are formed in heights and widths of 10 to 100 nm and 10 to 100 nm, respectively.

In addition, the transistor manufacturing method according to the present invention comprises the steps of forming a plurality of grooves in the form of line and space along the channel width direction on the surface of the active region of the semiconductor substrate; Forming a gate in a direction perpendicular to the grooves to have an uneven channel on the semiconductor substrate including the active area having the plurality of grooves; And forming a junction region in a surface of the substrate active region on both sides of the gate.

The grooves have a height and a width of 10 to 100 nm and 10 to 100 nm, respectively.

In addition, the transistor manufacturing method according to the present invention comprises the steps of: forming an etching mask on the semiconductor substrate having an active region to selectively expose the gate forming region of the active region; Forming a plurality of grooves in a line and space shape along a channel width direction on a surface of a gate formation region of the active region exposed by the etching mask; Removing the etching mask; Forming a gate conductive film on the interlayer insulating film including the gate formation region having the plurality of grooves; Forming a gate in a direction perpendicular to the grooves to have an uneven channel on the semiconductor substrate including the active area having the plurality of grooves; And forming a junction region in a surface of the substrate active region on both sides of the gate.

The grooves have a height and a width of 10 to 100 nm and 10 to 100 nm, respectively.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention will be briefly described. According to the present invention, a transistor is formed by etching an active region of a semiconductor substrate to have a shape of a plurality of repeated fine protrusion patterns in a gate channel width direction.

In this case, by forming the shape of the fine protrusion pattern on the active region to increase the effective channel length of the gate in the width direction, the short channel margin can be increased accordingly.

Therefore, by increasing the effective channel length of the gate in the width direction as described above, the short channel margin can be increased, thereby increasing the operating current of the transistor.

In detail, FIG. 1 is a plan view of a transistor according to an exemplary embodiment of the present invention, where reference numeral 100 denotes an active region, 102 an isolation region, and 104 a gate line.

2A to 2C correspond to lines A-A ', BB' and CC 'of FIG. 1, respectively, and are cross-sectional views illustrating a transistor and a method of manufacturing the same according to an embodiment of the present invention. Same as

Here, the cross-sectional view along the line B-B 'represents an etched region of the active region, and the cross-sectional view along the line C-C' represents an unetched region of the active region.

Referring to FIG. 2A, an isolation layer 206 defining an active region 200 of a semiconductor substrate is formed using a known technique.

Referring to FIG. 2B, a mask pattern (not shown) is formed to form a plurality of repeated protruding patterns on the active region 200 defined by the device isolation layer 206. Then, using the mask pattern as an etching mask, the active region 200 is etched to form the protrusion pattern 208 as shown in the cross-sectional view along the line A-A ', and then the mask pattern is removed.

At this time, the etching of the active region 200 is formed so that the entire region of the active region 200 is etched, as shown in the cross-sectional view along the line B-B ', to have a projection pattern 208.

In addition, it is preferable that the protrusion pattern 208 has a height and a width of the protrusion pattern 208 of 10 to 100 nm and 1 to 100 nm, respectively.

Referring to FIG. 2C, the gate insulating layer 210 is formed on the entire surface of the semiconductor substrate including the protrusion pattern 208 formed on the active region 200. Subsequently, a gate conductive film 212 and a gate hard mask film 216 are sequentially formed on the gate insulating film 210.

Subsequently, the gate hard mask film 216, the gate conductive film 212, and the gate insulating film 210 are etched, and as shown in the cross-sectional views along the lines BB ′ and CC ′, the gate insulating film 210 and the gate conductive film 212. ) And the gate hard mask layer 216, and the protrusion gate 216 is formed in a direction perpendicular to the protrusion pattern 208.

Then, the junction region 220 is formed in the substrate active region 200 on one side and the other side of the protruding gate 216.

In this case, the present invention can form a fine protrusion gate by etching to form a fine protrusion pattern on the active region, thereby increasing the effective channel length of the gate in the width direction.

Therefore, short channel margin can be increased.

In addition, as described above, the effective channel length of the gate is increased by forming the minute protrusion gate, thereby increasing the short channel margin, thereby increasing the operating current of the transistor.

3A to 3C are cross-sectional views corresponding to lines A-A ', BB', and CC 'of FIG. 1, respectively, to illustrate a transistor and a method of manufacturing the same according to an embodiment of the present invention. As follows.

Referring to FIG. 3A, a device isolation layer 306 defining an active region 300 of a semiconductor substrate is formed using a known technique. Then, an etching mask 318 is formed on the semiconductor substrate including the device isolation layer 306 to selectively expose the gate forming region of the active region.

Referring to FIG. 3B, after etching the gate forming region exposed by the etching mask on the active region 300, the etching mask may be removed, and the gate forming region may be etched into a fine protrusion pattern. A mask pattern (not shown) is formed.

Then, the substrate portion exposed to the mask pattern is etched to form a fine protrusion pattern 308 only in the gate formation region of the active region 300 as shown in the cross-sectional view along the line B-B '. Subsequently, the mask pattern is removed.

Referring to FIG. 3C, the gate insulating layer 310 is formed on the entire surface of the semiconductor substrate including the protrusion pattern 308 formed on the active region 300. Subsequently, a gate conductive layer 312 is formed on the gate insulating layer 310, and then the gate conductive layer 312 and the gate insulating layer 310 are planarized by CMP until the interlayer insulating layer 318 is exposed.

Subsequently, a hard mask layer 316 is formed on the CMP planarized gate conductive layer 312, and then the gate hard mask layer 316, the gate conductive layer 312, and the gate insulating layer 310 are etched. As shown in the cross-sectional views along the lines BB 'and CC', the protruding gate 316 having a laminated structure of the gate insulating film 310, the gate conductive film 312, and the gate hard mask film 316 is formed.

Then, the junction region 320 is formed in the substrate active region 300 on one side and the other side of the protruding gate 316.

In this case, the present invention can achieve the same effect as in the previous embodiment of the present invention by increasing the effective channel length of the gate in the width direction by the fine protrusion pattern as in the previous embodiment.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention can increase the effective channel length of the gate by forming a fine protrusion gate by etching to form a fine protrusion pattern on the active region.

Therefore, the present invention can increase the short channel margin accordingly.

In addition, the present invention can increase the short channel margin by increasing the effective channel length of the gate as described above, thereby increasing the operating current of the transistor.

Claims (8)

A semiconductor substrate having a plurality of grooves formed in a line and space shape along a channel width direction on an active region surface; A gate formed in a direction perpendicular to the grooves so as to have an uneven channel on the semiconductor substrate including the active area having the plurality of grooves; And A junction region formed in the substrate surface on both sides of the gate; Transistor comprising a. The method of claim 1, And the grooves are formed in all regions of the active region. The method of claim 1, And the groove is selectively formed only in an active region portion in which the gate is formed. The method of claim 1, And the groove is formed to have a height and a width of 10 to 100 nm and 10 to 100 nm, respectively. Forming a plurality of grooves in a line and space shape along a channel width direction on a surface of an active region of the semiconductor substrate; Forming a gate in a direction perpendicular to the grooves to have an uneven channel on the semiconductor substrate including the active area having the plurality of grooves; And Forming a junction region in a surface of the substrate active region on both sides of the gate; Transistor manufacturing method comprising a. The method of claim 5, wherein And the grooves are formed at heights and widths of 10 to 100 nm and 10 to 100 nm, respectively. Forming an etch mask on the semiconductor substrate having the active region to selectively expose the gate forming region of the active region; Forming a plurality of grooves in a line and space shape along a channel width direction on a surface of a gate formation region of the active region exposed by the etching mask; Removing the etching mask; Forming a gate conductive film on the interlayer insulating film including the gate formation region having the plurality of grooves; Forming a gate in a direction perpendicular to the grooves to have an uneven channel on the semiconductor substrate including the active area having the plurality of grooves; And Forming a junction region in a surface of the substrate active region on both sides of the gate; Transistor manufacturing method comprising a. The method of claim 7, wherein And the grooves are formed at heights and widths of 10 to 100 nm and 10 to 100 nm, respectively.
KR1020070031910A 2007-03-30 2007-03-30 Transistor and method for manufacturing the same KR20080088974A (en)

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Application Number Priority Date Filing Date Title
KR1020070031910A KR20080088974A (en) 2007-03-30 2007-03-30 Transistor and method for manufacturing the same

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105870161A (en) * 2014-12-30 2016-08-17 三星电子株式会社 Semiconductor devices and fabricating methods thereof
KR101675400B1 (en) 2016-07-11 2016-11-11 주식회사 한헬스케어 Manufacturing apparatus of cranial remolding helmet and

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105870161A (en) * 2014-12-30 2016-08-17 三星电子株式会社 Semiconductor devices and fabricating methods thereof
CN105870161B (en) * 2014-12-30 2021-04-13 三星电子株式会社 Semiconductor device and method for manufacturing the same
KR101675400B1 (en) 2016-07-11 2016-11-11 주식회사 한헬스케어 Manufacturing apparatus of cranial remolding helmet and

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