KR100650773B1 - Fin transistor and method for forming thereof - Google Patents

Fin transistor and method for forming thereof Download PDF

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KR100650773B1
KR100650773B1 KR1020050132192A KR20050132192A KR100650773B1 KR 100650773 B1 KR100650773 B1 KR 100650773B1 KR 1020050132192 A KR1020050132192 A KR 1020050132192A KR 20050132192 A KR20050132192 A KR 20050132192A KR 100650773 B1 KR100650773 B1 KR 100650773B1
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field oxide
active region
photoresist pattern
gate
oxide film
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KR1020050132192A
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Korean (ko)
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유민수
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)

Abstract

A Fin transistor and a method for forming the same are provided to minimize a leakage current between adjacent cells and to prevent GIDL(Gate Induced Drain Leakage). A substrate(10) having a protrudent active region is prepared. A field oxide layer(20) is formed at a field region of the substrate. A photoresist pattern having an opening part for exposing the active region and the adjacent field oxide layer is formed. The exposed field oxide layer is partially etched using the photoresist pattern as a mask. The photoresist pattern is removed. A gate(70) is then formed on the active region exposed to both sides.

Description

돌기형 트랜지스터 및 그의 형성방법{Fin Transistor and method for forming thereof}Fin transistor and method for forming thereof

도 1은 종래의 돌기형 트랜지스터의 제조방법을 설명하기 위한 평면도.1 is a plan view for explaining a method of manufacturing a conventional projection transistor.

도 2는 종래의 돌기형 트랜지스터의 제조방법을 설명하기 위한 단면도.2 is a cross-sectional view for explaining a method of manufacturing a conventional projection transistor.

도 3a 내지 도 3c는 본 발명에 따른 돌기형 트랜지스터의 제조방법을 설명하기 위한 공정별 단면도.3A to 3C are cross-sectional views for each process for explaining a method of manufacturing the protruding transistor according to the present invention.

도 4a 내지 도 4c는 본 발명에 따른 돌기형 트랜지스터의 제조방법을 설명하기 위한 공정별 평면도.4A to 4C are plan views for each process for explaining a method of manufacturing the protruding transistor according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

10: 반도체 기판 20: 필드산화막10: semiconductor substrate 20: field oxide film

30: 감괌막 패턴 40: 게이트절연막 30: gamma film pattern 40: gate insulating film

50: 도전막 60: 하드마스크막 50: conductive film 60: hard mask film

70: 게이트70: gate

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 돌기형 트랜지스터(Fin Transistor)의 형성방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a fin transistor.

최근, 고집적 모스펫(MOSFET) 소자의 디자인 룰이 급격히 감소함에 따라 그에 대응하여 트랜지스터의 채널 길이(length)와 폭(width)이 감소하고 있고, 아울러, 접합영역으로의 도핑농도는 증가하여 전기장(electric field) 증가에 따른 접합 누설 전류는 증가하고 있다. 이로 인해 기존의 플래너(planar) 채널 구조를 갖는 트랜지스터의 구조로는 고집적 소자에서 요구하는 문턱전압 값을 얻기 위해서는 채널 영역의 도핑농도가 증가되어 리프레쉬 특성을 향상시키는데 한계점에 이르게 되었다. In recent years, as the design rules of highly integrated MOSFETs decrease rapidly, the channel length and width of the transistors correspondingly decrease, and the doping concentration to the junction region increases, thereby increasing the electric field. As the field increases, the junction leakage current increases. As a result, the transistor structure having a planar channel structure has reached a limit in improving the refresh characteristics by increasing the doping concentration of the channel region in order to obtain the threshold voltage value required by the highly integrated device.

이에 따라, 채널 영역을 확장시킬 수 있는 3차원 구조의 채널을 갖는 모스펫 소자의 구현에 대한 아이디어 및 실제 공정개발 연구가 활발히 진행되고 있다. 이러한 노력의 하나로 최근 소자(device) 분야에서는 3차원 구조의 채널을 갖는 트랜지스터로서 돌기형 트랜지스터(Fin Transistor) 구조가 제안되었다. Accordingly, research on the idea and actual process development of the MOSFET device having a channel having a three-dimensional structure capable of expanding a channel region has been actively conducted. As one of such efforts, in the device field, a fin transistor structure has been proposed as a transistor having a channel having a three-dimensional structure.

상기와 같은 돌기형 트랜지스터는 활성 영역의 노출된 세 면 모두에 채널이 형성되기 때문에 채널을 통한 전류구동(current drive) 특성을 향상시킬 수 있는 장점을 가지고 있다. 따라서, 상기와 같은 장점으로 인해, 상기 돌기형 트랜지스터 구조는 차세대 초고집적 소자(device)를 구현할 수 있는 가장 이상적인 구조로 주목받고 있다.The protruding transistor as described above has an advantage of improving current drive characteristics through the channel because the channel is formed on all three exposed surfaces of the active region. Therefore, due to the above-described advantages, the protruding transistor structure has attracted attention as an ideal structure for implementing a next generation ultra-high density device.

여기서, 현재 수행하고 있는 돌기형 트랜지스터의 형성은 도 2a 및 도 2b를 참조하여 간략하게 설명하도록 한다.Here, the formation of the protruding transistor currently being performed will be briefly described with reference to FIGS. 2A and 2B.

도 2는 도 1의 A-A'선에 따른 공정 단면도이다.FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1.

도 2를 참조하면, 활성 영역 및 필드영역이 구비된 반도체 기판(1)을 마련한 후, 상기 필드영역의 기판(1) 부분을 식각하여 트렌치를 형성한다. 다음으로, 상기 트렌치 내에 산화막을 매립하여 셀(cell)과 셀간의 전기적 분리를 위한 필드산화막(2)을 형성한다. 그런다음, 상기 필드산화막(2)을 일부 식각하여 기판의 활성 영역을 돌출시킨다. 다음으로, 상기 돌출된 활성 영역 상에 게이트절연막(3)과 도전막(4) 및 하드마스크막(5)으로 이루어진 게이트(6)를 형성한다.Referring to FIG. 2, after preparing a semiconductor substrate 1 having an active region and a field region, a portion of the substrate 1 of the field region is etched to form a trench. Next, an oxide film is embedded in the trench to form a field oxide film 2 for electrical separation between the cell and the cell. Thereafter, the field oxide film 2 is partially etched to protrude the active region of the substrate. Next, a gate 6 including a gate insulating film 3, a conductive film 4, and a hard mask film 5 is formed on the protruding active region.

이후, 도시하지는 않았으나, 계속해서, 공지된 일련의 후속 공정을 차례로 진행하여 돌기형 트랜지스터를 제조한다.Subsequently, although not shown in the drawings, a series of subsequent known processes are successively performed to fabricate the protruding transistor.

상기에 전술한 바와 같이, DRAM의 최소 기억단위인 셀 분리는 필드산화막에 의해서 이루어진다. 상기 필드산화막을 공유하는 셀간 누설전류의 양을 결정하는 인자는 필드산화막의 깊이와 필드산화막 하부의 도핑(doping) 농도이다.As described above, the cell separation, which is the minimum storage unit of the DRAM, is made by the field oxide film. Factors that determine the amount of leakage current between cells sharing the field oxide film are the depth of the field oxide film and the doping concentration under the field oxide film.

한편, 전술한 바와 같이, 돌기형 트랜지스터를 형성하기 위해서는 활성 영역을 돌출시키기 위해 필드산화막을 식각하여야 하는데, 이때, 상기 필드산화막이 식각되어 그 두께가 감소됨에 따라 셀과 셀간의 누설전류는 증가하게 된다. 따라서, 소자의 리프레쉬(refresh) 타임을 감소시키는 결과가 발생하게 된다. Meanwhile, as described above, in order to form the projection transistor, the field oxide film must be etched to protrude the active region. In this case, as the field oxide film is etched and its thickness is decreased, the leakage current between cells increases. do. Thus, the result is to reduce the refresh time of the device.

또한, 상기 식각된 필드산화막 측벽에 게이트가 지나가는 구조가 만들어지게 되는데, 이렇게 이웃하는 게이트와 필드산화막간의 접촉 면적(도 2b에서 A부분)이 증가하여 GIDL(Gate Induced Drain Leakage) Current가 증가하게 되어 리프레쉬 타임이 감소하게 된다.In addition, a gate is formed on the sidewall of the etched field oxide layer. Thus, a contact area between the neighboring gate and the field oxide layer (part A in FIG. 2B) is increased to increase the gate induced drain leakage (GIDL) current. The refresh time is reduced.

따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출된 것으로서, 셀의 누설전류를 감소시켜 리프레쉬 특성을 향상시킬 수 있는 돌기형 트랜지스터 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a projection transistor manufacturing method capable of improving refresh characteristics by reducing a leakage current of a cell.

상기와 같은 목적을 달성하기 위하여, 본 발명은, 활성 영역이 돌출된 반도체기판을 마련하는 단계; 상기 기판의 활성 영역 이외 영역 상에 필드산화막을 형성하는 단계; 상기 필드산화막이 형성된 기판 결과물 상에 활성 영역의 길이방향에 대해 활성 영역 및 그 양측의 인접한 필드산화막 부분들을 노출시키는 개구부를 갖는 감광막 패턴을 형성하는 단계; 상기 활성영역의 양 측면이 노출되도록 감광막 패턴을 식각마스크로 이용해서 노출된 필드산화막 부분의 일부 두께를 식각하는 단계; 상기 감광막 패턴을 제거하는 단계; 및 상기 양 측면이 노출된 활성 영역 상에 게이트를 형성하는 단계;를 포함하는 트랜지스터 제조방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of providing a semiconductor substrate protruding active region; Forming a field oxide film on a region other than the active region of the substrate; Forming a photoresist pattern on the substrate resultant on which the field oxide film is formed, the photoresist pattern having an opening for exposing the active region and adjacent field oxide portions on both sides thereof in the longitudinal direction of the active region; Etching a part thickness of the exposed field oxide layer by using a photoresist pattern as an etching mask so that both sides of the active region are exposed; Removing the photoresist pattern; And forming a gate on the active region where both sides are exposed.

여기서, 상기 감광막 패턴의 개구부는 활성 영역의 폭 보다 200∼500Å 더 큰 폭을 갖도록 형성하는 것을 특징으로 한다.Here, the opening of the photoresist pattern is characterized in that it is formed to have a width of 200 to 500 kHz greater than the width of the active region.

상기 감광막 패턴의 개구부는 활성 영역의 길이 방향에 대해 적어도 두 개의 게이트를 포함하는 크기를 갖도록 형성하는 것을 특징으로 한다.The opening of the photoresist pattern may have a size including at least two gates in a length direction of the active region.

상기 필드산화막은 300∼2000Å 두께로 식각하는 것을 특징으로 한다.The field oxide film is etched to a thickness of 300 ~ 2000Å.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

먼저, 본 발명의 기술적 원리를 설명하면, 본 발명은 돌기형 트랜지스터를 제조하기 위한 것으로써, 활성영역의 양 측면을 노출하기 위한 필드산화막의 식각시 사용하는 식각마스크인 감광막 패턴을 활성 영역 그 양측의 인접한 필드산화막 부분들을 노출시키는 개구부를 갖는 감광막 패턴으로 형성한다.First, the technical principle of the present invention will be described. The present invention is for manufacturing a projection transistor, and the photoresist pattern, which is an etch mask used for etching the field oxide film for exposing both sides of the active region, on both sides of the active region. It is formed into a photosensitive film pattern having an opening that exposes adjacent field oxide film portions of the film.

이렇게 하면, 활성 영역의 양 측면을 노출하기 위한 필드산화막 식각시 게이트와 인접하는 필드산화막 부분이 식각되는 것을 방지할 수 있다.In this way, the field oxide film portion adjacent to the gate may be prevented from being etched when the field oxide film is etched to expose both sides of the active region.

즉, 상기 필드산화막 식각시 게이트와 인접하는 필드산화막 부분의 식각을 방지함으로써, 필드산화막 두께의 감소로 인한 셀과 셀간의 누설전류 발생을 최소화할 수 있다. 또한, 이웃하는 게이트와 필드산화막간의 접촉면을 감소시켜 GIDL(Gate Induced Drain Leakage)의 발생을 방지할 수 있어 소자의 리프레쉬 특성을 향상시킬 수 있다.That is, by preventing the etching of the field oxide layer adjacent to the gate when the field oxide is etched, leakage current between the cells due to the decrease in the thickness of the field oxide may be minimized. In addition, it is possible to prevent the generation of gate induced drain leakage (GIDL) by reducing the contact surface between the neighboring gate and the field oxide film, thereby improving the refresh characteristics of the device.

자세하게, 도 3a 내지 도 3c 및 도 4a 내지 도 4c는 본 발명에 따른 돌기형(Fin) 트랜지스터 제조방법을 설명하기 위한 공정별 단면도 및 평면도로서, 이를 설명하면 다음과 같다. In detail, FIGS. 3A to 3C and FIGS. 4A to 4C are cross-sectional views and a plan view for each process for explaining a method of manufacturing a protrusion transistor according to the present invention.

도 3a는 도 4a의 Y-Y'선에 따른 따른 공정별 단면도이며, 도 3b는 도 4b의 Y-Y'선에 따른 공정별 단면도이며, 도 3c는 도4c의 Y-Y'선에 따른 공정별 단면도이다.3A is a cross-sectional view of the process according to the line Y-Y 'of FIG. 4A, FIG. 3B is a cross-sectional view of the process according to the line Y-Y' of FIG. 4B, and FIG. It is cross section by process.

도 3a 및 도 4a를 참조하면, 활성영역이 돌출된 반도체 기판(10)을 마련한 후, 상기 기판의 활성영역 이외 영역 상에 필드산화막(20)을 형성한다. 후속 게이트가 형성하는 필드산화막 부분이 식각되는 것을 방지하기 위해 상기 필드산화막이 형성된 기판 결과물에 상에 활성 영역의 길이 방향에 대해 활성 영역 및 그 양측의 인접한 필드산화막 부분들을 노출시키는 개구부를 갖는 감광막 패턴(30)을 형성한다.Referring to FIGS. 3A and 4A, after the semiconductor substrate 10 having the active region protrudes is provided, a field oxide film 20 is formed on a region other than the active region of the substrate. A photoresist pattern having openings exposing the active region and adjacent field oxide portions on both sides thereof in the longitudinal direction of the active region on the substrate resultant on which the field oxide layer is formed to prevent etching of the field oxide layer formed by the subsequent gate. 30 is formed.

여기서, 상기 감광막 패턴의 개구부는 활성 영역의 폭 보다 200∼500Å 더 큰 폭을 갖도록 형성하며, 또한, 상기 감광막 패턴의 개구부는 활성 영역의 길이 방향에 대해 적어도 두 개의 게이트를 포함하는 크기를 갖도록 형성한다.Here, the opening of the photoresist pattern is formed to have a width of 200 to 500 Å greater than the width of the active region, and the opening of the photoresist pattern is formed to have a size including at least two gates in the longitudinal direction of the active region. do.

도 3b 및 도 4b를 참조하면, 상기 활성 영역의 양 측면이 노출되도록 감광막 패턴(30)을 식각마스크로 이용해서 노출된 필드산화막(20) 부분의 일부 두께를 식각한다. 이때, 상기 필드산화막(20)은 300∼2000Å 두께로 식각한다.3B and 4B, a portion of the exposed portion of the field oxide layer 20 is etched by using the photoresist pattern 30 as an etching mask so that both side surfaces of the active region are exposed. At this time, the field oxide film 20 is etched to 300 ~ 2000 300 thickness.

여기서, 본 발명은 상기 활성 영역의 양 측면을 노출시키기 위한 감광막 패턴을 상기와 같이 형성함으로써, 즉, 활성 영역의 길이방향에 대해 활성 영역 및 그 양측의 인접한 필드산화막을 노출시키는 개구부를 갖는 감광막 패턴으로 형성함으로써, 게이트와 인접하는 필드산화막 부분이 식각되는 것을 방지할 수 있다.Here, the present invention forms a photoresist pattern for exposing both sides of the active region as described above, that is, a photoresist pattern having an opening for exposing the active region and adjacent field oxide films on both sides thereof in the longitudinal direction of the active region. In this way, the field oxide film portion adjacent to the gate can be prevented from being etched.

즉, 본 발명은 상기 필드산화막 식각시 게이트와 인접하는 필드산화막 부분의 식각을 방지함으로써, 필드산화막 두께의 감소로 인한 셀과 셀간의 누설전류 발생을 최소화 할 수 있다. 다시말해, 누설전류의 경로(path)가 되는 부분의 필드산화막 부분이 식각되는 것을 방지함으로써, 누설전류 발생을 최소화 할 수 있다.That is, the present invention prevents the etching of the portion of the field oxide layer adjacent to the gate during the etching of the field oxide layer, thereby minimizing the leakage current between the cells due to the decrease in the thickness of the field oxide layer. In other words, by preventing the field oxide film portion of the portion that becomes the path of the leakage current from being etched, generation of the leakage current can be minimized.

아울러, 게이트와 인접하는 필드산화막 부분이 식각되는 것을 방지함에 따라. 이웃하는 게이트와 필드산화막간의 접촉면을 감소시켜 GIDL의 발생을 방지할 수 있어 소자의 리프레쉬 특성을 향상시킬 수 있다.In addition, as the portion of the field oxide layer adjacent to the gate is prevented from being etched. By reducing the contact surface between the neighboring gate and the field oxide film, it is possible to prevent the occurrence of GIDL, thereby improving the refresh characteristics of the device.

도 3c 및 도 4c를 참조하면, 상기 감광막 패턴을 제거한 상태에서 상기 양 측면이 노출된 활성 영역 상에 게이트절연막(40)과 도전막(50) 및 하드마스크막(60)을 차례로 형성한다. 그런다음, 상기 하드마스크막(60)과 도전막(50) 및 게이트절연막(40)을 식각하여 게이트(70)를 형성한다.  Referring to FIGS. 3C and 4C, the gate insulating layer 40, the conductive layer 50, and the hard mask layer 60 are sequentially formed on the active region in which both sides of the photoresist layer are removed. Thereafter, the hard mask layer 60, the conductive layer 50, and the gate insulating layer 40 are etched to form a gate 70.

이후, 도시하지는 않았으나, 계속해서 공지된 일련의 후속 공정을 차례로 진행하여 본 발명에 따른 돌기형 트랜지스터를 제조한다.Thereafter, although not shown, a subsequent series of known processes are subsequently carried out in order to manufacture the protruding transistor according to the present invention.

이상에서와 같이, 본 발명은 돌기형(Fin) 트랜지스터 형성시 활성 영역의 양 측면을 노출하기 위한 필드산화막 식각시 게이트와 인접하는 필드산화막 부분이 식각되는 것을 방지함으로써, 상기 필드산화막의 두께 감소를 방지할 수 있어, 이로 인해 셀과 셀간의 누설전류 발생을 최소할 수 있는 효과를 얻을 수 있다.As described above, the present invention prevents the field oxide layer portion adjacent to the gate from being etched during the field oxide etching to expose both sides of the active region when forming the fin transistor, thereby reducing the thickness of the field oxide layer. This can prevent the leakage current between the cells, which can be minimized.

또한, 본 발명은 상기 게이트와 인접하는 필드산화막 부분이 식각되는 것을 방지함으로써, 이웃하는 게이트와 필드산화막간의 접촉면을 감소시켜 GIDL(Gate Induced Drain Leakage)의 발생을 방지할 수 있어 소자의 리프레쉬 특성을 향상시킬 수 있는 효과를 얻을 수 있다. In addition, the present invention prevents the portion of the field oxide layer adjacent to the gate from being etched, thereby reducing the contact surface between the neighboring gate and the field oxide layer to prevent generation of gate induced drain leakage (GIDL), thereby improving the refresh characteristics of the device. The effect can be improved.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

Claims (4)

활성 영역이 돌출된 반도체기판을 마련하는 단계; Providing a semiconductor substrate on which the active region protrudes; 상기 기판의 활성 영역 이외 영역 상에 필드산화막을 형성하는 단계; Forming a field oxide film on a region other than the active region of the substrate; 상기 필드산화막이 형성된 기판 결과물 상에 활성 영역의 길이방향에 대해 활성 영역 및 그 양측의 인접한 필드산화막 부분들을 노출시키는 개구부를 갖는 감광막 패턴을 형성하는 단계; Forming a photoresist pattern on the substrate resultant on which the field oxide film is formed, the photoresist pattern having an opening that exposes the active region and adjacent field oxide portions on both sides thereof in the longitudinal direction of the active region; 상기 활성영역의 양 측면이 노출되도록 감광막 패턴을 식각마스크로 이용해서 노출된 필드산화막 부분의 일부 두께를 식각하는 단계;Etching a part thickness of the exposed field oxide layer by using a photoresist pattern as an etching mask so that both sides of the active region are exposed; 상기 감광막 패턴을 제거하는 단계; 및Removing the photoresist pattern; And 상기 양 측면이 노출된 활성 영역 상에 게이트를 형성하는 단계;를 포함하는 것을 특징으로 하는 트랜지스터 제조방법.Forming a gate on an active region where both sides are exposed. 제 1 항에 있어서,The method of claim 1, 상기 감광막 패턴의 개구부는 활성 영역의 폭 보다 200∼500Å 더 큰 폭을 갖도록 형성하는 것을 특징으로 하는 트랜지스터 제조방법.And the opening of the photoresist pattern is formed to have a width of 200 to 500 kHz larger than the width of the active region. 제 1 항에 있어서,The method of claim 1, 상기 감광막 패턴의 개구부는 활성 영역의 길이 방향에 대해 적어도 두 개의 게이트를 포함하는 크기를 갖도록 형성하는 것을 특징으로 하는 트랜지스터 제조방 법. The opening of the photoresist pattern is formed to have a size including at least two gates in the longitudinal direction of the active region. 제 1 항에 있어서,The method of claim 1, 상기 필드산화막은 300∼2000Å 두께로 식각하는 것을 특징으로 하는 트랜지스터 제조방법.And the field oxide film is etched to a thickness of 300 to 2000 microns.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100920045B1 (en) 2007-12-20 2009-10-07 주식회사 하이닉스반도체 Semiconductor device and method of manufacturing the same
US9178044B2 (en) 2013-05-30 2015-11-03 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100920045B1 (en) 2007-12-20 2009-10-07 주식회사 하이닉스반도체 Semiconductor device and method of manufacturing the same
US7737492B2 (en) 2007-12-20 2010-06-15 Hynix Semiconductor Inc. Semiconductor device for reducing interference between adjoining gates and method for manufacturing the same
US9178044B2 (en) 2013-05-30 2015-11-03 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US9520499B2 (en) 2013-05-30 2016-12-13 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same

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