KR20080085526A - Method for manufacturing semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to reduce a line width of a bit line contact hole region by performing a resist reflow process after forming a photoresist layer pattern for defining a bit line contact hole region. An interlayer dielectric(140), a hard mask layer, and a barrier layer(150) are formed on an upper portion of a semiconductor substrate(100). An anti-reflective layer and a photoresist layer pattern(160) defining a contact region are formed on an upper portion of the barrier layer. The anti-reflective layer is etched by using the photoresist layer pattern as a mask to form an anti-reflective layer pattern. The anti-reflective layer pattern has a positive slope. The photoresist layer pattern is removed. The barrier layer, the hard mask layer, and the interlayer dielectric are etched by using the anti-reflective layer pattern as an etching mask to form a contact hole. The interlayer dielectric is a BPSG(Boro-Phospho-Silicate-Glass) oxide layer.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1 is a layout showing a semiconductor device.

2A to 2F are cross-sectional views illustrating a method of manufacturing a bit line contact hole in a semiconductor device according to the present invention.

3A to 3C are graphs showing the substrate reflectance according to the thickness of the antireflection film.

<Description of Symbols for Main Parts of Drawings>

100 semiconductor substrate 105 active region

110 device isolation layer 115 gate polysilicon layer

120: gate metal layer 125: gate hard mask layer

127: spacer 130: gate pattern

140: interlayer insulating film 145: hard mask layer

150: barrier film 155: antireflection film

160: photosensitive film pattern 170: contact hole

The present invention relates to a method for manufacturing a semiconductor device, and after forming a photoresist pattern defining a bit line contact hole region, by performing a resist reflow process to reduce the line width of the bit line contact hole region to a minimum, during the anti-reflection film etching process By adding a gas that functions as a passivation, the anti-reflection film is etched to form a positive slope.

Next, a technique is disclosed in which the underlying structure is etched using the inclined antireflection film as a mask to form a bit line contact hole having a fine line width of resolution or less, thereby improving the characteristics of the device.

In recent years, as the semiconductor device becomes extremely fine and highly integrated, the overall chip area is increased in proportion to the increase in memory capacity, but the area of the cell area where the pattern of the semiconductor device is formed is decreasing.

Therefore, in order to secure a desired memory capacity, more patterns must be formed in a limited cell area, and thus a fine pattern having a reduced critical dimension of the pattern must be formed.

In order to form a pattern having a fine line width, the development of a lithography process is required.

In the lithography process, a photoresist is applied on a substrate, and a circuit pattern is formed by using a laser light source having a wavelength length of 365 nm, 248 nm (KrF), 193 nm (ArF), and 153 nm. It is a process of forming a pattern by performing an exposure process using the drawn exposure mask and then a development process.

In the lithography process, the resolution R is determined according to the wavelength λ and the numerical aperture NA of the light source, such as R = k1 × λ / NA.

In the above formula, k1 means a process constant, which has a physical limit, and thus, it is almost impossible to reduce the value by a conventional method, and to overcome this, there is a problem of introducing a new exposure equipment.

In addition, a resist flow process may be introduced in order to form a fine pattern without using a new exposure equipment, but there is a problem that an additional process must be added.

In the method of manufacturing a semiconductor device according to the related art, an interlayer insulating film, a hard mask layer, an antireflection film, and a photosensitive film are sequentially formed on a semiconductor substrate provided with a gate pattern and a landing plug.

Next, an exposure and development process is performed on the photoresist to form a photoresist pattern that exposes the bit line contact hole region.

In this case, the exposure process is performed using an exposure mask having a light transmission pattern defining the bit line contact hole region, and light is diffracted at the time of exposure by a chromium layer formed in a region other than the light transmission pattern, so that the line / space Or there is a problem that the resolution is reduced compared to the island pattern.

Next, a resist reflow process is performed to heat the photoresist pattern to a temperature above the glass transition temperature (Tg) to allow the photoresist to flow, thereby reducing the line width of the region exposed by the photoresist pattern. .

The anti-reflection film, the hard mask layer, and the interlayer insulating layer are sequentially etched using the photoresist pattern on which the resist reflow process is performed, to form a bit line contact hole.

Next, the photoresist pattern and the anti-reflection film are removed, and a bit line material layer is formed on the entire portion including the bit line contact hole and then patterned to form a bit line.

In the above-described method of manufacturing a semiconductor device, a resist reflow process is additionally performed after the formation of the photoresist pattern to form a small line width of the bit line contact hole, which is limited since the 40 nm device. For this reason, a method of Shrink Assist Film for Enhancement Resolution (SAFIER) or Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS), which subsequently coats heterogeneous materials, has been proposed, but there is a problem in applying it to an actual process.

In addition, since the bit line contact hole is to be formed on the landing plug contact, when the overlay correction is incorrect during the bit line contact hole etching process, an interlayer insulating layer serving as a separator of the landing plug contact region may be damaged and a short circuit may occur. There is an increasing problem.

In order to solve the above problem, after forming a photoresist pattern defining a bit line contact hole region, a resist reflow process is performed to reduce the line width of the bit line contact hole region to a minimum and to passivate the anti-reflective layer etching process. By adding a gas, the antireflection film is etched so that a positive slope is formed.

Next, an object of the present invention is to provide a method for manufacturing a semiconductor device by etching a lower structure by using an inclined antireflection film as a mask to form a bit line contact hole having a fine line width of less than the resolution, thereby improving the characteristics of the device.

Method for manufacturing a semiconductor device according to the present invention

Forming an interlayer insulating film, a hard mask layer, and a barrier film on the semiconductor substrate;

Forming a photoresist pattern defining an anti-reflection film and a contact region on the barrier film;

Forming an antireflection film pattern by etching the antireflection film using the photoresist pattern as a mask, wherein the antireflection film pattern has a positive slope;

Removing the photoresist pattern, and etching the barrier layer, the hard mask layer, and the interlayer insulating layer using the anti-reflection layer pattern as an etch mask to form contact holes.

The interlayer insulating film is a BPSG oxide film,

The hard mask layer is an amorphous carbon layer of 500 to 2000 500 thickness,

The barrier film is any one selected from a TEOS film, a silicon oxynitride film, and a combination thereof;

The barrier film has a thickness of 200 to 400 GPa;

The thickness of the anti-reflection film is 450 to 600Å,

Forming the anti-reflection film pattern is to use a carbon-based or bromine-based gas,

The forming of the anti-reflection film pattern may be performed using any one gas selected from C 2 F 6, HBr, Br 2, and a combination thereof.

The temperature of the etching chamber is 23 to 70 degrees when forming the anti-reflection film pattern,

When the anti-reflection film pattern is formed, the bias power is that of the source bias power of 100 to 1500W and the bottom bias power of 0 to 500W,

The method may further include performing a resist reflow process after forming the photoresist pattern.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

1 is a layout illustrating a semiconductor device according to the present invention.

Referring to FIG. 1, a gate pattern 130 is formed on a semiconductor substrate 100 having a device isolation region and an active region 105.

Here, the spacers 127 may be provided on both sides of the gate pattern 130, and two gate patterns 130 may be formed on one active region 105.

The bit line 175 is provided in a direction perpendicular to the gate pattern 130, and the bit line is formed so as not to overlap the active region 105, and is connected to the lower structure and the bit line contact 170. do.

2A to 2F illustrate a method of manufacturing a semiconductor device according to the present invention, and are cross-sectional views illustrating a cutting plane taken along the line X ′ of FIG. 1.

Referring to FIG. 2A, the gate insulating layer (not shown), the gate polysilicon layer 115, the gate metal layer 120, and the gate hard mask layer 125 may be formed on the semiconductor substrate 100 having the device isolation layer 110. A laminate structure is formed.

Next, the stacked structure is patterned to form a gate pattern 130.

Next, a polysilicon layer is formed over the entire surface including the gate pattern 130.

The planarization process is performed until the gate hard mask layer 125 at the top of the gate pattern 130 is exposed to form a landing plug contact 135 between the gate patterns 130.

Referring to FIG. 2B, an interlayer insulating layer 140, a hard mask layer 145, a barrier layer 150, an antireflection layer 155, and a photoresist layer (not shown) are sequentially formed on the resultant.

Here, the interlayer insulating film 140 is a BPSG oxide film, and is preferably formed to a thickness of 500 to 1500 kPa.

In addition, the hard mask layer 145 is an amorphous carbon layer, and preferably formed with a thickness of 500 to 2000 GPa.

The barrier film 150 is formed of any one of a TOES film, a silicon oxynitride film (SiON), and a combination thereof, and is preferably formed to have a thickness of 200 to 400 GPa.

In addition, the anti-reflection film 155 is preferably formed of a material having an extinction coefficient (k, Extinction Coefficient) of 0.2 to 0.4 at a wavelength of 193 nm, and the thickness of the anti-reflection film 155 is preferably 450 to 600 kPa, which is thicker than the prior art. .

 This is to lower the substrate reflectance of the TEOS and the amorphous carbon layer, and to secure the amount of reduction in the contact hole line width during the subsequent anti-reflection film 155 etching process.

In addition, the anti-reflection film 155 preferably has a high etching rate to compensate for the etching selectivity with the photoresist film (not shown) formed thereon, and has a high oxygen ratio in the form of a polyester having a high etching rate. Preference is given to using polymers.

Next, an exposure and development process using an exposure mask defining a bit line contact hole is performed to form a photosensitive film pattern 160 exposing the bit line contact hole region.

Then, a resist reflow process is performed to reduce the line width of the bit line contact hole predetermined region exposed by the photoresist pattern 160 within an adjustable range.

Referring to FIG. 2C, the anti-reflection film 155 is etched using the photoresist pattern 160 as a mask to form the anti-reflection film pattern 155a.

In this case, the etching process for forming the anti-reflection film pattern 155a may be performed by adding a gas having a passivation function to the CF4 and CHF3 gases.

In this case, the passivating gas generates a polymer during an etching process so that the line width of the upper portion of the anti-reflection film pattern 155a is larger than the lower line width of the anti-reflection film pattern 155a. ) To decrease the line width of the bit line contact hole performed by the etching mask.

Here, the gas to be added is preferably a gas selected from any one of HBr, Br2 and a combination thereof containing C2F6 gas having high carbon (C) content or bromine (Br).

In addition, when the anti-reflection film pattern 155a is formed, the etching chamber is performed at a temperature of 23 to 70 degrees, and it is preferable to perform the source bias power of 100 to 1500W and the bottom bias power of 0 to 500W.

Referring to FIG. 2D, the barrier layer 150 is etched using the anti-reflection layer pattern 155a as an etch mask to form the barrier layer pattern 150a.

Referring to FIG. 2E, the hard mask layer 145 is etched using the barrier layer pattern 150a as an etch mask to form the hard mask layer 145 pattern.

Next, the photoresist pattern 160 and the antireflection film pattern 155a are removed.

Referring to FIG. 2F, the interlayer insulating layer 140 is etched using the hard mask layer 145 pattern as an etch mask to form an interlayer insulating layer pattern 140a defining the bit line contact hole 170, and the barrier layer pattern ( 150a) and the hard mask layer 145 pattern are removed.

Next, an additional implant process for compensating the dose may be further performed.

Thereafter, the bit line 175 is formed over the entire portion including the bit line contact hole 170.

3A to 3C are graphs showing the relationship between the thickness of the antireflection film and the substrate reflectance according to the thickness of the oxide film.

Here, the anti-reflection film serves to prevent diffuse reflection by adjusting the substrate reflectance and to increase the uniformity of the pattern line width, and the refractive index (n) and the extinction coefficient (k) are formed at a wavelength of 193 nm by the material formed under the anti-reflection film. The refractive index and the extinction coefficient of the anti-reflection film should be adjusted according to the presence or absence of?

In addition, the thickness of the anti-reflection film should be adjusted so that the substrate reflectance becomes the lowest.

3A to 3C, since the absorption coefficient of the oxide film at a wavelength of 193 nm is 0.01 or less, the substrate reflectance is not adjusted. For this reason, it can be seen that the optimum thickness of the antireflection film varies depending on the thickness of the oxide film.

In the method of manufacturing a semiconductor device according to the present invention, after forming a photoresist pattern defining a bit line contact hole region, a resist reflow process is performed to reduce the line width of the bit line contact hole region to a minimum, and a passivation function during an anti-reflection film etching process. By adding a gas, the anti-reflection film is etched to form a positive slope.

Next, the lower structure is etched using the inclined antireflective film as a mask, thereby forming a bit line contact hole having a fine line width of less than the resolution, thereby improving the characteristics of the device.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (11)

Forming an interlayer insulating film, a hard mask layer, and a barrier film over the semiconductor substrate; Forming a photoresist pattern on the barrier layer, the photoresist pattern defining an anti-reflection film and a contact region; Etching the anti-reflection film using the photoresist pattern as a mask to form an anti-reflection film pattern, wherein the anti-reflection film pattern has a positive slope; And Removing the photoresist pattern and etching the barrier layer, hard mask layer, and interlayer insulating layer using the anti-reflection layer pattern as an etch mask to form a contact hole Method of manufacturing a semiconductor device comprising a. The method of claim 1, The interlayer insulating film is a manufacturing method of a semiconductor device, characterized in that the BPSG oxide film. The method of claim 1, The hard mask layer is a method of manufacturing a semiconductor device, characterized in that the amorphous carbon layer of 500 to 2000Å thickness. The method of claim 1, The barrier film is a semiconductor device manufacturing method, characterized in that any one selected from TEOS film, silicon oxynitride film and a combination thereof. The method of claim 1, The barrier film has a thickness of 200 to 400 GPa. The method of claim 1, The thickness of the anti-reflection film is a manufacturing method of a semiconductor device, characterized in that 450 to 600Å. The method of claim 1, The forming of the anti-reflection film pattern may include using a carbon-based or bromine-based gas. The method of claim 1, The forming of the anti-reflection film pattern is a method of manufacturing a semiconductor device, characterized in that performed using any one of the gas selected from C2F6, HBr, Br2 and combinations thereof. The method of claim 1, The temperature of the etching chamber when forming the anti-reflection film pattern is a method of manufacturing a semiconductor device, characterized in that 23 to 70 degrees. The method of claim 1, When the anti-reflection film pattern is formed, the bias power is a source bias power of 100 to 1500W and a bottom bias power of 0 to 500W. The method of claim 1, And forming a resist reflow process after forming the photoresist pattern.

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