KR20080082394A - Liquid crystal display device - Google Patents

Abstract

An LCD(Liquid Crystal Display) is provided to improve the brightness by changing the structure of a thin film transistor within one pixel instead of covering the pixel through a light-shielding layer. An LCD comprises a first substrate including a display area and a non-display area, a second substrate facing the first substrate, and a liquid crystal layer formed between the first substrate and the second substrate. N gate lines and M data lines are arranged in raw and column directions to define MxN pixel regions above the first substrate. Thin film transistors(T) are formed in the pixel regions, and connected to gate lines of the corresponding pixel regions. Pixel electrodes are formed within the pixel regions. The pixel electrodes receive signal through the thin film transistors. Dummy thin film transistors(T') are formed within pixel regions associated with the first raw to apply signal to the corresponding pixel electrodes. A dummy gate line(DGL) is positioned ahead of the gate lines, and connected to the dummy thin film transistors.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

1 is an exploded perspective view schematically showing a liquid crystal display device according to the prior art.

2 is a plan view schematically illustrating a portion of a first substrate of a liquid crystal display according to the related art.

Figure 3 is a plan view schematically showing a first substrate according to the present invention.

4A is a diagram for explaining the structure of a pixel formed on a first substrate according to an embodiment of the present invention;

4B is a cross sectional view along line IVb-IVb ′ of FIG. 4A;

<Explanation of symbols for main parts of the drawings>

ACT: display area N_ACT: non-display area

GL: Gate Line DL: Data Line

P: Pixel T: Thin Film Transistor

T ': dummy thin film transistor 109, 109': storage capacitor

118: pixel electrode 121, 121 ': gate electrode

122, 122 ': source electrode 123, 123': drain electrode

124: active layer

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having reduced brightness of the first gate line.

Recently, with the development of various electronic devices such as mobile phones, PDAs, computers, and large TVs, the demand for flat panel display devices that can be applied thereto is gradually increasing.

Such flat panel displays are being actively researched, such as LCD (Liquid Crystal Display), PDP (Plasma Display Panel), FED (Field Emission Display), VFD (Vacuum Fluorescent Display), but mass production technology, ease of driving means, Liquid crystal displays (LCDs) are in the spotlight for reasons of implementation.

A liquid crystal display device is a display device using optical anisotropy of a liquid crystal, and implements an image by adjusting the light transmittance of the liquid crystal using an electric field.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a general liquid crystal display.

As shown in the drawing, the liquid crystal display includes a first substrate on which a thin film transistor and the like are largely formed, a second substrate facing the first substrate, and a color filter layer and the like, and a liquid crystal layer formed between the two substrates. layer) 30.

The second substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B). A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. It consists of (8).

In addition, the first substrate 10 is arranged horizontally and horizontally to define a plurality of gate lines 16 and data lines 17 defining the plurality of pixel regions P, and the gate lines 16 and data lines 17. A thin film transistor (T), which is a switching element formed at an intersection region of, and a pixel electrode (18) formed on the pixel region (P).

The second substrate 5 and the first substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a liquid crystal display panel. The second substrate (5) and the first substrate 10 is bonded through a bonding key (not shown) formed on the second substrate 5 or the first substrate 10.

2 is a plan view schematically illustrating one pixel of a first substrate of a general liquid crystal display device.

As shown in the drawing, a gate line 16 and a data line 17 are formed on the first substrate 10 to be arranged vertically and horizontally on the first substrate 10 to define a pixel area. In this case, a thin film transistor T, which is a switching element, is formed in an intersection area of the gate line 16 and the data line 17, and is connected to the thin film transistor T in the pixel area so as to form a second substrate (not shown). A pixel electrode 18 is formed to form an electric field together with the common electrode of FIG. 2 to drive a liquid crystal (not shown).

The thin film transistor is formed on the gate electrode 21 constituting a part of the gate line 16, the semiconductor layer 24 formed on the gate electrode 21, and the semiconductor layer 24 to form a data line 17. And a source electrode 22 and a drain electrode 23 for applying a signal input through the pixel electrode 18.

In the above liquid crystal display device, a pixel voltage is applied to the pixel electrode of the first substrate to form an electric field in the liquid crystal layer formed between the common electrode of the second substrate. It is not maintained until the pixel voltage) is input. Therefore, in order to maintain the applied pixel voltage for a predetermined time and apply an electric field to the liquid crystal layer for a predetermined time, a storage capacitor must be formed in the pixel. As shown in the figure, the storage capacitor is generally formed by overlapping a portion of the n−1 th gate line 16 with the pixel electrode 18 of the n th pixel. Such a storage capacitor is called a storage on gate capacitor. In this method, one more dummy gate line is designed for the first row of pixels to form a storage capacitor on the dummy gate line.

However, no voltage is applied to the dummy gate line. Therefore, even in the case of the same storage capacitor structure as other pixels, the capacitance value is smaller than the storage capacitance value of the other line.

In addition, parasitic capacitance is generated between the pixel electrode and the adjacent pixel electrode. In the case of the first line pixel, the parasitic capacitance of the first line pixel is also different because the adjacent pixel electrode has a different shape from the pixel of the other line. It has a different value from the capacitance of the pixel.

The difference between the storage capacitance and the parasitic capacitance eventually makes the kickback voltage of the first line pixel larger than the kickback voltage in the pixel voltages of the other line pixels. This increase in kickback voltage causes a problem that the pixels of the first line become brighter than the pixels of the other lines. In addition, in the case of the pixels on the first line, a phenomenon that appears brighter than other lines may appear due to the inversion of the frame.

Disclosure of Invention The present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display device having improved brightness by changing the structure and aperture ratio of a thin film transistor in one pixel instead of using a light blocking layer. It is done.

In order to achieve the above object, a liquid crystal display device according to the present invention includes a first substrate including an image display area and an image non-display area, a second substrate facing the first substrate, and a liquid crystal formed between the two substrates. The first substrate is formed on each pixel, N gate lines and M data lines, which are non-thermally arranged in row and column directions on the first substrate to define M × N pixels. A thin film transistor connected to the gate line, a pixel electrode formed in each pixel to receive a signal through the thin film transistor, and a dummy thin film transistor formed in the pixel of the first row to apply a signal to the pixel electrode.

Hereinafter, a liquid crystal display according to the present invention will be described with reference to the drawings.

The present invention relates to a liquid crystal display device having reduced light leakage phenomenon appearing in the pixels of the first row. According to an exemplary embodiment of the present invention, in order to reduce light leakage in the first row, a dummy thin film transistor is further formed in the first row of pixels to increase the charging power of the pixel.

Also, in order to reduce the kickback voltage of the first pixel, the storage capacitance of the first line is formed to be larger than the storage capacitance of the other row.

In general, the pixel electrode of the first substrate forms an electric field together with the common electrode of the second substrate, and the charge forming the electric field is not maintained until the next signal. Thus, a storage capacitor is formed to maintain the applied voltage.

However, the signal voltage transferred to the pixel electrode by a gate signal is unable to maintain the state as it enters ΔV _p as a voltage drop makin done, the ΔV _p is called kickback voltage. The kickback voltage is caused by parasitic capacitance (C _gd ) at the overlapping gate electrode and source electrode or drain electrode of the thin film transistor, and when the kickback voltage is large, the effective voltage applied to the liquid crystal lowers the liquid crystal effectively. Light leaks in black.

Due to the parasitic capacitance C _gd , the pixel voltage is changed by the kickback voltage ΔV _p . The kickback voltage is expressed by the following equation.

Where C _lc represents the capacitance of the liquid crystal capacitor and C _st represents the capacitance of the storage capacitor. Also, ΔV _p represents the voltage difference between the high gate voltage and the low gate voltage.

In the embodiment of the present invention, the value of the storage capacitance is increased to reduce the kickback voltage, thereby reducing light leakage.

In the embodiment of the present invention to describe the above two methods for reducing the light leakage phenomenon, it can be carried out separately as each embodiment of course.

FIG. 3 is a conceptual diagram conceptually showing a structure of a liquid crystal display according to the present invention. FIG. 4A is a diagram illustrating a pixel structure of a liquid crystal display according to an embodiment of the present invention, and FIG. 4B is IVb-IVb of FIG. 4A. 'It is a cross section along the line. 4A and 4B, the N gate lines GL and the M data lines DL intersect with each other on the first substrate 101, but M × N pixels exist for convenience of description. Only the pixel P1 of the row and the pixel P2 portion of the second row are shown. In the following description, the fact that a film or layer is formed on another film or layer includes not only the case where two films or layers are in contact with each other but also a case where another film or layer exists between the two films or layers.

In addition, for convenience of description, the direction in which the gate lines GL1, GL2, ... extend, is in a row direction or the left and right directions, and the direction in which the data lines DL1, DL2, ... are extended in a column direction or up and down It demonstrates as a direction.

Referring to FIG. 3, the first substrate 101 is generally divided into an image display area ACT in which an image is displayed and an image non-display area N_ACT which is another area in which no image is displayed. In general, the non-image display area N_ACT is an area that surrounds the image display area along the edge of the image display area ACT and is located at the outer side. The gate pad GP applies a signal to the gate line GL and the data line DL. ) And a data pad DP.

As illustrated in FIG. 3, in the image display area ACT, N gate lines GL and M data lines DL are disposed so as to vertically cross each other in the row and column directions, respectively. Is formed.

A dummy gate line DGL preceding the gate line GL1 of the first row is formed above the gate line GL1 of the first row constituting the pixel P1 of the first row. Here, the term dummy is used because, unlike the gate line GL that applies the gate signal to the pixels P of each row, the pixel preceding the first row does not exist.

The dummy gate line DGL is formed in the image non-display area N_ACT and is preferably formed in the boundary area in the upper direction of the pixels P1 in the first row.

A thin film transistor T is formed on the dummy gate line DGL. In this case, unlike other gate lines GL, the thin film transistor T 'connected to the dummy gate line DGL is formed in the pixel P1 corresponding to the gate line GL of the first row. In other words, the structures of the pixels P1 of the first row (that is, n = 1) and the pixels Pn and n≥2 of the second and subsequent rows (that is, n≥2) are formed differently.

The structures of the pixels P1 in the first row and the pixels Pn in the nth row will be described in detail with reference to FIGS. 4A and 4B.

4A and 4B, a pixel defined by a gate line GL, a data line DL formed to intersect the gate line GL, a gate line GL, and a data line DL is formed on the first substrate 110. (P), a thin film transistor (T) formed in the pixel (P), and connected to the dummy gate line (DGL) and the dummy gate line (DGL) formed in front of the gate line (GL1) of the first row and the first And a dummy thin film transistor T 'disposed in the pixels P1 in the row.

First, the pixel P of the nth row of the image display area will be described.

The first substrate 101 is made of an insulating material such as glass, quartz, or ceramic, and is formed thereon with a single layer or multiple layers of at least one of chromium, molybdenum, tungsten, nickel, aluminum, and alloys thereof. A layered gate line is arranged.

The gate insulating layer 111 is formed on the first substrate 110. The gate insulating layer 111 is formed by stacking an inorganic material made of silicon nitride (SiNx), silicon oxide (SiOx), or the like.

M data lines DL are formed in the column direction on the gate insulating layer 111 so as to substantially cross vertically with the gate line GL. The data line DL may be formed of a single layer or multiple layers of metal, and may include at least one of chromium, molybdenum, tungsten, nickel, aluminum, and alloys thereof.

The M data lines DL together with the N gate lines GL define M × N pixels P in a matrix form. As shown in FIG. 4A, a thin film transistor is formed in each pixel.

As shown in FIG. 4B, the thin film transistor T is formed on the first substrate 110 and has a gate electrode 121 to which a gate voltage is applied, and a conductive channel as the gate voltage is applied. The active layer 124 and the source electrode 122 and the drain electrode 123 are formed on the active layer 124 to apply a signal to the pixel region through the conductive channel.

In this case, the active layer 124 is formed by sequentially stacking the semiconductor layer 124a and the ohmic contact layer 124b, and the semiconductor layer 124a may be formed of a semiconductor such as amorphous silicon or crystalline silicon. The ohmic contact layer 124b is formed of a material such as amorphous silicon doped with n-type impurities.

The passivation layer 131 is formed on the first substrate 110 on which the data line DL and the source / drain electrodes 122 and 123 are formed. The passivation layer 131 may be formed of an inorganic insulating layer or an organic insulating layer.

The pixel electrode 118 is formed on the passivation layer 131. The pixel electrode 118 is formed in the pixel of the display unit ACT. The pixel electrode 118 is electrically connected to the drain electrode 123 through the contact hole 126 formed in the passivation layer 131.

The pixel electrode 118 is formed of a transparent conductive material, and may be formed using, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

As shown in FIG. 4A, a dummy gate line DGL is preceded by an upper portion of the gate line GL1 of the first row of the gate lines GL. That is, the dummy gate line DGL is formed in parallel with the gate line GL and is formed in the non-display portion N_ACT.

The dummy gate line DGL may be formed of a single layer or multiple layers, and may include chromium, molybdenum, tungsten, nickel, aluminum, chromium, alloys thereof, and the like. In this case, the gate line GL and the dummy gate line DGL may be formed of the same material as the gate line GL.

A dummy thin film transistor T ′ connected to the dummy gate line DGL is formed at an intersection of the dummy gate line DGL and the data line DL in the pixel P1 of the first row.

The dummy thin film transistor T 'is formed similarly to the thin film transistor T except that the thin film transistor is connected to the dummy gate line DGL instead of the gate line GL.

The gate electrode 121 ′ is formed in the dummy gate line DGL in one direction.

A gate insulating layer 111 ′ is formed on the insulating substrate including the dummy gate line DGL, and M data lines DL are formed to intersect the dummy gate line DGL on the gate insulating layer 111 ′. have.

The data line DL has a source centered on the source electrode 122 'and the gate electrode 121' which are branched from the data line DL and extend in the direction of the gate electrode 121 'connected to the dummy gate line DGL. A drain electrode 123 'is formed spaced apart from the electrode 122'.

A dummy thin film transistor T 'is formed in each pixel P1 of the first row by the gate electrode 121', the source electrode 122 ', and the drain electrode 123'.

A passivation layer 131 is formed on the insulating substrate 110 including the data line DL and the source / drain electrodes 122 ′ and 123 ′. In the passivation layer 131, a contact hole 126 ′ which partially exposes the drain electrode 123 ′ is formed.

The pixel electrode 118 is formed on the passivation layer 131. The pixel electrode 118 is connected to the drain electrode 123 of the thin film transistor T as the pixel electrode 118 of the first row pixel P1. Therefore, a signal is simultaneously applied to the pixel electrode 118 of the first row by the dummy thin film transistor T 'connected to the dummy gate line DGL and the thin film transistor T connected to the gate line GL1 of the first row.

As described above, since the signal is simultaneously applied through the two thin film transistors T and T ', the pixel electrode 118 of the first row has no signal delay or signal attenuation compared to when the signal is applied by one thin film transistor. You lose. In general, in the pixel electrode 118 of the first row, one thin film transistor per pixel may not generate a substantial effective voltage sufficient to sufficiently drive the liquid crystal molecules by signal attenuation at the pixel electrode 118. That is, full charging of the pixel voltage is not performed.

However, in the exemplary embodiment of the present invention, two thin film transistors T and T 'are formed in the pixel P1 of the first row to apply a signal, thereby fully charging the pixel electrode 118 of the first row. As the pixel electrode 118 is fully charged as described above, the effective voltage applied to the pixel electrode 118 is increased. As a result, abnormal driving of the liquid crystal molecules is reduced, thereby reducing light leakage.

Meanwhile, a dummy gate pad (not shown) may be formed at one end of the dummy gate line DGL to simultaneously apply the same signal to the dummy gate line DGL and the gate line GL1 of the first row. However, preferably, at least one end of the gate line GL1 of the first row may be connected to the dummy gate line DGL through a connection portion in which a portion of the gate line GL1 of the first row extends. The connection portion is formed in the image non-display area N_ACT and does not affect the image. In this case, a connection portion may be formed at one end in a direction in which the gate pad GP (see FIG. 3) to which the signal is applied to the gate line GL or in a direction opposite to the direction in which the gate pad GP is formed. Of course, it may be formed at both ends of the gate line GL1.

Therefore, when the dummy gate line DGL and the gate line GL1 of the first row are separately formed, the same signal may be applied separately. Preferably, the same signal is applied at the same time by electrically connecting the gate line GL1 and the dummy gate line DGL. As a result, since the same voltage is simultaneously applied to the pixel electrode 118 through the thin film transistor T and the dummy thin film transistor T ', the pixel electrode 118 is quickly and efficiently charged.

In this case, the dummy gate line may be formed of the same material as the gate line.

Meanwhile, in the exemplary embodiment of the present invention, the dummy gate line DGL may have a wider line width than the gate line GLn of the nth (1 ≦ n ≦ N) row. In this case, the dummy gate line DGL is formed to have a wider line width than the gate line GLn, so that the area of the pixel P1 in the first row is smaller than the area of the pixel Pn in the second and subsequent rows.

As described above, since the pixel area of the second and subsequent rows becomes smaller than the pixel area of the first row, the amount of light passing through the corresponding pixel is reduced, so that the phenomenon of abnormally bright pixels in the first row can be alleviated.

In this case, when the dummy gate line DGL is formed to be wide, the area of the pixel P1 becomes small. However, in the conventional invention, about 50% of the upper portion of the pixel P1 is covered by the light blocking layer (not shown) of the second substrate. Compared with that, there is an effect that the substantial opening ratio is improved.

According to the related art, the light shielding layer is formed to cover about 50% of the first pixel in order to reduce the light phenomenon of the first line. In this case, although the luminance of the first row could be reduced, there was a problem that the aperture ratio was lowered. On the other hand, in the exemplary embodiment of the present invention, the area of the gate line is reduced, thereby reducing the luminance and minimizing the light blocking layer near the thin film transistor T, the gate line GL, and the data line DL. This is improved.

In the exemplary embodiment of the present invention, the pixel electrode 118 overlaps the gate line GL or the dummy gate line DGL with the insulating layer 131 interposed therebetween, and respectively, the first and second storage capacitors 109 and 109 '. ).

In this case, the storage capacitor is formed in a storage on gate method using a portion of the n−1 th (1 <n ≦ N) gate line GLn as an electrode of the n th storage capacitor 109. That is, the first storage capacitor 109 of the n-th pixel Pn is overlapped by the gate line GL of the n-th row and the pixel electrode 118 of the n-th row overlapping each other with the insulating layer 131 interposed therebetween. Is formed. Since there is no preceding gate line GL in the pixel electrode 118 of the first row, a portion of the pixel electrode 118 and the dummy gate line DGL of the first row overlap to form a second storage capacitor 109 ′. .

The second storage capacitor 109 'of the first row is larger than the first storage capacitor 109 of the nth row. For this purpose, the area of the partial region where the pixel electrode 118 and the dummy gate line DGL overlap in the first row overlaps the pixel electrode 118 and the n-1 th gate line GLn-1 in the n th row. It is formed larger than the area of the area.

Meanwhile, in the exemplary embodiment of the present invention, in order to overlap the pixel electrode 118 with the dummy gate line DGL and the gate line GL, a part of the pixel electrode 118 is partially overlapped with the dummy gate line DGL and the gate line (G). GL may extend to the GL side, and a part of the dummy gate line DGL and the gate line GL may be overlapped by extending toward the pixel electrode 118.

As described above, according to the exemplary embodiment of the present invention, the value of the storage capacitance of the first row is greater than the value of the storage capacitance of the second or less row. Since the larger the value of the storage capacitance, the lower the kickback voltage, the light leakage may be reduced by improving the voltage holding ratio of the corresponding row pixel.

As described above, according to the exemplary embodiment of the present invention, the thin film transistors are formed together with the thin film transistors in the first row to improve the charging power of the first row, and the storage capacitors of the first row are larger than the storage capacitors of the nth row. This improves the voltage maintenance ratio, thereby reducing the light leakage phenomenon.

In addition, by increasing the line width of the dummy gate line and forming a larger storage capacitor, the light leakage of the first row pixel is reduced, and consequently, the aperture ratio is increased.

The detailed description of the invention should be construed as an illustration of preferred embodiments rather than to limit the scope of the invention.

Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

As described above, the present invention has been made to solve the above-mentioned problem, and the liquid crystal display which improves the brightness phenomenon by changing the number, structure, and aperture ratio of the thin film transistor in one pixel instead of covering the pixel using the light blocking layer. Provide the device.

Claims (15)

A first substrate including an image display area and an image non-display area, a second substrate facing the first substrate, and a liquid crystal layer formed between the two substrates, The first substrate is N gate lines and M data lines arranged in the row and column directions on the first substrate to define M × N pixels; A thin film transistor formed in each pixel and connected to the gate line of the pixel; A pixel electrode formed in each pixel and to which a signal is applied through the thin film transistor; And And a dummy thin film transistor formed on the pixels of the first row to apply a signal to the corresponding pixel electrode. The method of claim 1, And a dummy gate line preceding the gate line and connected to the dummy thin film transistor. The method of claim 2, And the dummy gate line is formed in a non-display area. The method of claim 2, The pixel electrode of the first row is simultaneously connected to the dummy thin film transistor and the thin film transistor of the first row, and the pixel electrode of the nth (1 <n≤N) row is connected to the thin film transistor of the nth row. . The method of claim 2, And the dummy gate line further comprises a connection portion electrically connecting the gate lines of the first row to at least one end thereof. The method of claim 5, And the connection part is formed in the non-display area. The method of claim 2, And a dummy gate pad configured to apply the same signal to the dummy gate line as one of the gate lines of the first row at one end of the dummy gate line. The method of claim 7, wherein And the same signal as that of the gate line of the first row is applied to the dummy gate line. The method of claim 2, And the dummy gate line is formed of the same material as the gate line. The method of claim 2, And the gate line and the dummy gate line overlap the pixel electrode to form a first storage capacitor and a second storage capacitor, each having a different capacitance. The method of claim 9, And the capacitance of the second storage capacitor is greater than that of the first storage capacitor. The method of claim 11, And the dummy gate line has a wider line width than the gate line. The method of claim 12, And the pixels of the first row are smaller than the pixels of the nth (1 < n? N) rows. The method of claim 2, The thin film transistor is A gate electrode branched from the gate line; A source electrode branched from the data line; And And a drain electrode formed to be spaced apart from the source electrode with respect to the gate electrode. The method of claim 2, The dummy thin film transistor is A gate electrode branched from the dummy gate line; A source electrode branched from the data line; And And a drain electrode formed to be spaced apart from the source electrode with respect to the gate electrode.

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