KR20080076398A - Method for forming landing plug contact of semiconductor device - Google Patents

Method for forming landing plug contact of semiconductor device Download PDF

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KR20080076398A
KR20080076398A KR1020070016250A KR20070016250A KR20080076398A KR 20080076398 A KR20080076398 A KR 20080076398A KR 1020070016250 A KR1020070016250 A KR 1020070016250A KR 20070016250 A KR20070016250 A KR 20070016250A KR 20080076398 A KR20080076398 A KR 20080076398A
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polysilicon film
plug contact
interlayer insulating
landing plug
gate
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KR1020070016250A
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Korean (ko)
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김재수
박철환
김형균
조호진
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주식회사 하이닉스반도체
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Publication of KR20080076398A publication Critical patent/KR20080076398A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Abstract

A method for forming a landing plug contact of a semiconductor device is provided to reduce a manufacturing process time by forming the landing plug contact including a single crystalline silicon layer and a polysilicon layer within a landing contact hole. A silicon substrate(110) including gates having gate spacers(170) and a junction region is prepared. An interlayer dielectric is buried into a gap between the gates. A polysilicon layer(192) is formed on the entire surface of the substrate including the interlayer dielectric. A spacer is formed at both sidewalls of the gate spacers by etching the polysilicon layer and the interlayer dielectric. A landing contact hole for exposing the junction region is formed by removing the residual interlayer dielectric. The junction region of the silicon substrate and the polysilicon layer are grown by performing an SEG(Selective Epitaxial Growth) process.

Description

반도체 소자의 랜딩플러그콘택 형성방법{Method for forming landing plug contact of semiconductor device}Method for forming landing plug contact of semiconductor device

도 1 내지 도 5는 본 발명의 실시예에 따른 반도체 소자의 랜딩플러그콘택 형성방법을 설명하기 위한 공정별 단면도. 1 to 5 are cross-sectional views illustrating processes of forming a landing plug contact of a semiconductor device according to an exemplary embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

110: 실리콘기판 120: 소자분리막110: silicon substrate 120: device isolation film

130: 게이트 절연막 140: 게이트 도전막130: gate insulating film 140: gate conductive film

150: 게이트 하드마스크막 160: 게이트150: gate hard mask layer 160: gate

170: 게이트용 스페이서 180: 층간절연막170: gate spacer 180: interlayer insulating film

190,192: 폴리실리콘막 191: 단결정실리콘막190,192 polysilicon film 191 single crystal silicon film

193: 랜딩플러그콘택 H: 홈193: Landing Plug Contact H: Home

C/H: 랜딩콘택홀 S/D: 접합영역C / H: Landing contact hole S / D: Junction area

본 발명은 반도체 소자의 랜딩플러그콘택 형성방법에 관한 것으로, 보다 상세하게는, 선택적 에피택셜 성장을 이용하는 랜딩플러그콘택 형성시 공정 시간을 단축할 수 있는 반도체 소자의 랜딩플러그콘택 형성방법에 관한 것이다.The present invention relates to a method of forming a landing plug contact of a semiconductor device, and more particularly, to a method of forming a landing plug contact of a semiconductor device capable of shortening a process time when forming a landing plug contact using selective epitaxial growth.

반도체 소자의 고집적화에 따라 소자 크기가 점점 작아지는 추세에서, 콘택 면적이 감소되고 있는 바, 콘택저항 증가 및 동작전류의 감소 현상이 나타나고 있다.As the size of devices increases with increasing integration of semiconductor devices, the contact area decreases, resulting in an increase in contact resistance and a decrease in operating current.

이에, 소자의 콘택저항을 낮추고 동작전류를 향상시키기 위한 방안으로, 상,하부 패턴을 전기적으로 연결시키기 위한 랜딩플러그콘택(Landing Plug Contact)를 단결정실리콘막 에피텍셜 성장시키는 선택적 에피텍셜 성장(Selective Epitaxial Growth: 이하, SEG) 공정과 폴리실리콘막을 사용하여 증착하는 공정으로 2단계의 공정을 적용하고 있다.Accordingly, in order to lower the contact resistance of the device and improve the operating current, selective epitaxial growth for epitaxially growing a landing plug contact for electrically connecting the upper and lower patterns to the single crystal silicon film. Growth: Hereinafter, a two-step process is applied as a process of depositing using a SEG process and a polysilicon film.

일반적으로, 2단계의 공정으로 형성되는 랜딩플러그콘택는, 먼저, 상기 SEG 공정으로 750℃의 낮은 온도에서 ∼9시간 정도의 긴 공정시간으로 증착 공정으로 형성되는 폴리실리콘막에 비해 낮은 두께인 600Å 두께로 단결정실리콘막을 성장시키고, 퍼니스(furnace)에서 ∼6시간 정도의 공정시간으로 폴리실리콘막을 2000Å 두께로 형성시키는 것이 그 특징이다.In general, the landing plug contact formed by the two-step process is, firstly, 600 Å thickness, which is lower than the polysilicon film formed by the deposition process with a long process time of about 9 hours at a low temperature of 750 ° C. in the SEG process. It is characterized by growing a single crystal silicon film and forming a polysilicon film with a thickness of 2000 microseconds in a furnace at a process time of about 6 hours.

전술한 바와 같이, SEG 공정 및 증착 공정으로 랜딩플러그콘택를 형성하는 종래의 기술에서는, 2단계의 공정 진행으로 인해 그 제조 공정시간이 길어지는 특성 및 공정의 복잡화를 안고 있는 특성으로 인해 생산 효율의 저하를 안고 있는 실정이다.As described above, in the conventional technology of forming the landing plug contact by the SEG process and the deposition process, the production process time is long due to the two-step process and the complexity of the process reduces the production efficiency. The situation is holding.

본 발명은 SEG 공정과 증착 공정으로 형성되는 랜딩플러그콘택의 공정 시간 을 단축함과 아울러 공정의 단순화를 이룰 수 있는 반도체 소자의 랜딩플러그콘택 형성방법을 제공함에 그 목적이 있다.It is an object of the present invention to provide a method for forming a landing plug contact of a semiconductor device capable of shortening the process time of the landing plug contact formed by the SEG process and the deposition process and simplifying the process.

상기와 같은 목적을 달성하기 위하여, 본 발명은, 게이트용 스페이서가 구비된 게이트들 및 접합영역이 형성된 실리콘기판을 마련하는 단계; 상기 게이트들 사이에 층간절연막을 일부 매립하는 단계; 상기 게이트를 덮도록 층간절연막을 포함한 기판 전면 상에 폴리실리콘막을 형성하는 단계; 상기 폴리실리콘막 및 층간절연막이 게이트용 스페이서 양측벽에 스페이서 형태로 잔존하도록 폴리실리콘막을 식각함과 아울러 층간절연막을 식각하는 단계; 상기 잔존된 층간절연막을 제거하여 접합영역을 완전히 노출시키는 랜딩콘택홀을 형성하는 단계; 상기 폴리실리콘막을 포함한 기판 결과물에 대해 SEG 공정을 수행하여 상기 랜딩콘택홀의 저면 부분인 실리콘기판의 접합영역을 성장시킴과 아울러 상기 폴리실리콘막 부분을 성장시키는 단계;를 포함하는 반도체 소자의 랜딩플러그콘택 형성방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of providing a silicon substrate having gates and a junction region is provided with a spacer for the gate; Partially filling an interlayer insulating film between the gates; Forming a polysilicon film on the entire surface of the substrate including the interlayer insulating film to cover the gate; Etching the polysilicon film and etching the interlayer insulating film such that the polysilicon film and the interlayer insulating film remain on both sidewalls of the gate spacer; Forming a landing contact hole to completely expose a junction region by removing the remaining interlayer insulating layer; Performing a SEG process on the substrate product including the polysilicon film to grow a junction region of a silicon substrate, which is a bottom portion of the landing contact hole, and to grow the polysilicon film portion; and landing plug contact of a semiconductor device. It provides a formation method.

여기서, 상기 폴리실리콘막은 490∼650℃의 온도에서 SiH4, N2 및 PH3 가스를 사용하여 형성하는 것을 포함한다.Here, the polysilicon film is formed using SiH 4 , N 2 and PH 3 gas at a temperature of 490 ~ 650 ℃.

상기 폴리실리콘막은 500∼1000Å 두께로 형성하는 것을 포함하는 것을 포함한다.The polysilicon film includes those formed to have a thickness of 500 to 1000 GPa.

상기 폴리실리콘막 및 층간절연막이 게이트용 스페이서 양측벽에 스페이서 형태로 잔존하도록 폴리실리콘막을 식각함과 아울러 층간절연막을 식각하는 단계 는, 상기 폴리실리콘막 및 층간절연막이 게이트용 스페이서 양측벽에 100∼200Å 두께로 잔존하도록 수행하는 것을 포함한다.Etching the polysilicon film and etching the interlayer insulating film so that the polysilicon film and the interlayer insulating film remain on both sides of the gate spacer in the form of a spacer may include: Performing to remain at a thickness of 200 mm 3.

상기 잔존된 층간절연막의 제거는, H2SO4:H2O2의 비율이 50:1인 용액과 NH4F:HF의 비율이 9:1인 용액을 사용하여 수행하는 것을 포함한다.The removal of the remaining interlayer insulating film may be performed using a solution having a ratio of H 2 SO 4 : H 2 O 2 of 50: 1 and a solution having a ratio of NH 4 F: HF of 9: 1.

상기 SEG 공정은 700∼1100℃의 온도에서 수행하는 것을 포함한다.The SEG process includes performing at a temperature of 700 to 1100 ° C.

상기 SEG 공정은 100∼300sccm 유량을 갖는 SiH2Cl2 가스와 50∼200sccm 유량을 갖는 HCl 가스 및 1∼500sccm 유량을 갖는 PH3 가스를 사용하여 수행하는 것을 포함한다.The SEG process is SiH 2 Cl 2 gas having a flow rate of 100-300sccm, HCl gas having a flow rate of 50-200sccm and PH 3 having a flow rate of 1-500sccm Performing with gas.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

먼저, 본 발명의 기술적 원리를 설명하면, 본 발명은 SEG 공정을 이용한 랜딩플러그콘택 형성방법에 관한 것으로, 스페이서가 구비된 게이트 양측벽에 선택적으로 폴리실리콘막을 형성하고 나서, 랜딩콘택홀의 저면 부분인 실리콘기판의 접합영역을 포함한 상기 폴리실리콘막 상에 SEG 공정을 수행하여 인-시튜(in-situ)로 랜딩콘택홀 내에 단결정실리콘막과 폴리실리콘막으로 이루어진 랜딩플러그콘택를 형성하는 것을 특징으로 한다.First, the technical principle of the present invention, the present invention relates to a method for forming a landing plug contact using a SEG process, and selectively forming a polysilicon film on both side walls of the gate provided with a spacer, which is a bottom portion of the landing contact hole SEG process is performed on the polysilicon film including the junction region of the silicon substrate to form a landing plug contact made of a single crystal silicon film and a polysilicon film in the landing contact hole in-situ.

이렇게 하면, 상기 SEG 공정을 통해 랜딩콘택홀의 저면 상에는 단결정실리콘이 성장됨에 동시에 폴리실리콘막 상에는 폴리실리콘막이 성장됨으로써, 이를 통 해, 인-시튜(in-situ)로 상기 단결정실리콘막과 폴리실리콘막으로 이루어지는 랜딩플러그콘택를 형성할 수 있게 되어 종래의 기술에 따른 랜딩플러그콘택의 제조 공정 보다 제조 공정 시간을 단축할 수 있으며, 아울러, 공정의 단순화를 이룰 수 있게 된다.In this case, the single crystal silicon is grown on the bottom surface of the landing contact hole through the SEG process and the polysilicon film is grown on the polysilicon film, thereby through the in-situ, the single crystal silicon film and the polysilicon film. It is possible to form a landing plug contact consisting of a shorter manufacturing process time than the manufacturing process of the landing plug contact according to the prior art, and can also simplify the process.

다시말하면, 종래의 기술에 따른 랜딩플러그콘택 형성방법은, SEG 공정과 폴리실리콘막의 증착 공정의 2단계 공정으로 수행하게 되면서, 그에 따른, 제조 공정 시간이 길어지는 특성이 있는데 반하여, 본 발명에서는, SEG 공정만을 수행하여 랜딩콘택홀 내에 단결정실리콘막과 폴리실리콘막으로 이루어지는 랜딩플러그콘택를 형성하게 됨으로써, 종래 기술 대비 제조 공정 시간을 단축할 수 있게 된다.In other words, while the landing plug contact forming method according to the related art is performed in a two-step process of the SEG process and the deposition process of the polysilicon film, the manufacturing process time is long accordingly, whereas in the present invention, By only performing the SEG process to form a landing plug contact made of a single crystal silicon film and a polysilicon film in the landing contact hole, it is possible to shorten the manufacturing process time compared to the prior art.

또한, SEG 공정 및 폴리실리콘막의 증착 공정으로 이루어진 2단계의 공정이 아닌 1단계의 SEG 공정으로 단결정실리콘막과 폴리실리콘막으로 이루어지는 랜딩플러그콘택를 형성함으로써, 그에 따른, 종래 대비 공정의 단순화를 이룰 수 있으며, 아울러, SEG 공정을 통해 선택적으로 폴리실리콘막을 형성할 수 있게 됨으로써, 랜딩플러그콘택 형성을 위한 랜딩플러그콘택용 도전막, 즉, 폴리실리콘막의 화학적기계적연마(Chemical Mechanical Polishing; 이하, CMP)를 스킵 할 수 있으므로, 이 역시 공정의 단순화를 가능케 할 수 있게 된다.In addition, by forming a landing plug contact made of a single crystal silicon film and a polysilicon film in a one-step SEG process instead of a two-step process consisting of an SEG process and a deposition process of a polysilicon film, thereby simplifying a conventional process. In addition, the polysilicon film may be selectively formed through the SEG process, so that the conductive film for the landing plug contact for forming the landing plug contact, that is, the chemical mechanical polishing (CMP) of the polysilicon film, may be formed. Since this can be skipped, this also allows for a simplified process.

자세하게는, 도 1 내지 도 5를 참조하여 본 발명의 실시예에 따른 반도체 소자의 랜딩플러그콘택 형성방법을 설명하도록 한다.In detail, a method of forming a landing plug contact of a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 to 5.

도 1을 참조하면, 표면 내에 액티브영역을 한정하는 소자분리막(120)이 구비된 실리콘기판(110)을 마련한 후, 상기 실리콘기판을 식각하여 게이트 형성 영역 을 갖는 홈(H)을 형성한다. Referring to FIG. 1, after the silicon substrate 110 having the device isolation layer 120 defining the active region is provided on the surface, the silicon substrate is etched to form the groove H having the gate formation region.

그런다음, 상기 홈(H)을 포함한 기판 전면 상에 게이트 절연막(130)을 형성한 후, 상기 게이트 절연막(130)이 형성된 홈이 매립되도록 게이트 절연막(130) 상에 게이트 도전막을(140) 형성하고 나서, 연이어, 상기 게이트 도전막(140) 상에 게이트 하드마스크막(150)을 형성한다.Then, after the gate insulating film 130 is formed on the entire surface of the substrate including the groove H, the gate conductive film 140 is formed on the gate insulating film 130 so that the groove on which the gate insulating film 130 is formed is filled. Subsequently, a gate hard mask film 150 is formed on the gate conductive film 140.

다음으로, 상기 게이트 하드마스크막(150)과 게이트 도전막(140) 및 게이트 절연막(130)을 식각하여 상기 홈(H)을 포함한 게이트 형성 영역 상에 게이트 절연막(130)과 게이트 도전막(140) 및 게이트 하드마스크막(150)으로 이루어진 게이트(160)를 형성한 후, 상기 게이트(160) 양측벽에 게이트용 스페이서(170)를 형성한다.Next, the gate hard mask layer 150, the gate conductive layer 140, and the gate insulating layer 130 are etched to etch the gate insulating layer 130 and the gate conductive layer 140 on the gate formation region including the groove H. ) And a gate spacer 170 formed on both sidewalls of the gate 160 after forming the gate 160 including the gate hard mask layer 150.

이어서, 상기 게이트용 스페이서(170)가 형성된 기판 결과물에 대해 불순물 이온주입을 수행하여 상기 게이트(160) 양측의 기판 표면 내에 접합영역(S/D)을 형성한 후, 상기 게이트(160)를 덮도록 기판 전면 상에 층간절연막(180)을 형성한다.Subsequently, impurity ion implantation is performed on the substrate product on which the gate spacer 170 is formed to form a junction region S / D in the substrate surface on both sides of the gate 160, and then cover the gate 160. The interlayer insulating film 180 is formed on the entire surface of the substrate.

도 2를 참조하면, 상기 층간절연막(180)을 일부 두께 식각한다.Referring to FIG. 2, the interlayer insulating layer 180 is partially etched.

그런다음, 상기 게이트(160)를 덮도록 식각된 층간절연막(180)을 포함한 기판 전면 상에 폴리실리콘막(190)을 형성한다.Then, a polysilicon layer 190 is formed on the entire surface of the substrate including the interlayer insulating layer 180 etched to cover the gate 160.

이때, 상기 폴리실리콘막(190)은 490∼650℃의 온도에서 SiH4, N2 및 PH3 가스를 사용하여 500∼1000Å 두께로 형성하도록 한다. 바람직하게는, 상기 게이트 하드마스크막을 덮는 두께로 형성하도록 한다. At this time, the polysilicon film 190 is formed to a thickness of 500 ~ 1000Å by using SiH 4 , N 2 and PH 3 gas at a temperature of 490 ~ 650 ℃. Preferably, the gate hard mask layer is formed to have a thickness covering the gate hard mask layer.

도 3을 참조하면, 상기 폴리실리콘막(190) 및 층간절연막(180)이 게이트용 스페이서(170) 양측벽에 스페이서(spacer) 형태로 잔존하도록 폴리실리콘막을 식각함과 아울러 층간절연막을 식각한다.Referring to FIG. 3, the polysilicon layer 190 and the interlayer dielectric layer 180 are etched and the interlayer dielectric layer is etched so that the polysilicon layer 190 and the interlayer dielectric layer 180 remain on both sides of the gate spacer 170 in the form of a spacer.

이때, 상기 폴리실리콘막(190) 및 층간절연막(180)은 상기 게이트용 스페이서(170) 양측벽에 100∼200Å 두께만큼 남겨지도록 식각한다.In this case, the polysilicon layer 190 and the interlayer insulating layer 180 are etched so as to be left at a thickness of 100 to 200 에 on both side walls of the gate spacer 170.

도 4를 참조하면, 상기 남겨진 층간절연막을 제거하여 접합영역(S/D)을 노출시키는 랜딩콘택홀(C/H)을 형성한다.Referring to FIG. 4, the remaining interlayer insulating layer is removed to form a landing contact hole C / H exposing the junction region S / D.

이때, 상기 층간절연막은 H2SO4:H2O2의 비율이 50:1인 용액과 NH4F:HF의 비율이 9:1인 용액을 사용하여 제거하도록 한다.In this case, the interlayer insulating layer is removed by using a solution having a ratio of H 2 SO 4 : H 2 O 2 of 50: 1 and a solution having a ratio of NH 4 F: HF of 9: 1.

여기서, 상기 층간절연막을 제거함에 따라 상기 게이트용 스페이서(170) 양측벽에 선택적으로 폴리실리콘막(190)만이 남게 된다.As the interlayer insulating layer is removed, only the polysilicon layer 190 remains on both sidewalls of the gate spacer 170.

도 5를 참조하면, 상기 폴리실리콘막(190)을 포함한 기판 결과물에 대해 SEG 공정을 수행하여 상기 랜딩콘택홀(C/H)의 저면 부분인 실리콘기판의 접합영역(S/D)을 성장시킴과 아울러 상기 폴리실리콘막(190) 부분을 성장시켜 상기 랜딩콘택홀 내에 단결정실리콘막(191)과 폴리실리콘막(192)으로 이루어지는 랜딩플러그콘택(193)를 형성한다.Referring to FIG. 5, a SEG process is performed on a substrate product including the polysilicon layer 190 to grow a junction region S / D of a silicon substrate, which is a bottom portion of the landing contact hole C / H. In addition, the polysilicon layer 190 is grown to form a landing plug contact 193 including a single crystal silicon layer 191 and a polysilicon layer 192 in the landing contact hole.

이때, 상기 SEG 공정은 700∼1100℃의 온도에서 100∼300sccm 유량을 갖는 SiH2Cl2 가스와 50∼200sccm 유량을 갖는 HCl 가스 및 1∼500sccm 유량을 갖는 PH3 가스를 사용하여 수행한다.At this time, the SEG process is SiH 2 Cl 2 gas having a flow rate of 100 to 300sccm and HCl gas having a flow rate of 50 to 200sccm and PH 3 having a flow rate of 1 to 500sccm at a temperature of 700 ~ 1100 ℃ Performed using gas.

이처럼, 인-시튜(in-situ)로 상기 랜딩콘택홀 내에 단결정실리콘막(191)과 폴리실리콘막(192)으로 이루어지는 랜딩플러그콘택(193)를 형성함에 따라 종래의 기술 대비 제조 공정 시간을 단축할 수 있다.As such, by forming the landing plug contact 193 formed of the single crystal silicon film 191 and the polysilicon film 192 in the landing contact hole in-situ, the manufacturing process time is shortened compared to the prior art. can do.

또한, SEG 공정을 통해 선택적으로 폴리실리콘막(192)을 게이트 하드마스크막 부분까지 성장시킬 수 있으므로, 이에 따라, 랜딩플러그콘택 형성을 위한 폴리실리콘막의 CMP를 스킵(skip) 할 수 있게 되어, 이에 따른, 공정의 단순화가 가능하다.In addition, the polysilicon layer 192 may be selectively grown to the gate hard mask layer through the SEG process, and thus, the CMP of the polysilicon layer for forming the landing plug contact may be skipped. Accordingly, the process can be simplified.

구체적으로는, 상기 SEG 공정을 통해 실리콘기판의 접합영역에서 단결정실리콘이 성장되며, 상기 게이트용 스페이서 양측벽에 형성된 폴리실리콘막 상에서 폴리실리콘막이 성장됨에 따라, 이를 통해, 인-시튜로 단결정실리콘막 및 폴리실리콘막으로 이루어진 랜딩플러그콘택를 형성하게 되면서, SEG 공정 및 폴리실리콘막의 증착 공정, 즉, 2단계의 공정 진행으로 랜딩플러그콘택를 형성하는 종래 기술에 비해 제조 공정 시간을 단축할 수 있음은 물론 공정의 단순화를 이룰 수 있게 된다.Specifically, the single crystal silicon is grown in the junction region of the silicon substrate through the SEG process, and as the polysilicon film is grown on the polysilicon film formed on both side walls of the gate spacer, the in-situ single crystal silicon film is thereby grown. And while forming a landing plug contact made of a polysilicon film, SEG process and the deposition process of the polysilicon film, that is, the process can be shortened manufacturing process compared to the prior art of forming a landing plug contact in a two-step process, of course Can be simplified.

이상, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있으며, 그러므로, 이하 특허청구범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다. As described above, specific embodiments of the present invention have been described and illustrated, but modifications and variations can be made by those skilled in the art. Therefore, the following claims are intended to cover all modifications and modifications as long as they fall within the true spirit and scope of the present invention. It is understood to include variations.

이상에서와 같이, 본 발명은, 스페이서가 구비된 게이트 양측벽에 선택적으로 폴리실리콘막을 형성하고 나서, 랜딩콘택홀의 저면 부분인 실리콘기판의 접합영 역을 포함한 상기 폴리실리콘막 상에 SEG 공정을 수행하여 랜딩콘택홀 내에 단결정실리콘막과 폴리실리콘막으로 이루어진 랜딩플러그콘택를 형성함으로써, 종래의 기술 대비 제조 공정 시간의 단축 및 공정의 단순화를 이룰 수 있게 된다.As described above, according to the present invention, a polysilicon film is selectively formed on both side walls of the gate having a spacer, and then a SEG process is performed on the polysilicon film including a junction region of a silicon substrate, which is a bottom portion of the landing contact hole. Thus, by forming a landing plug contact made of a single crystal silicon film and a polysilicon film in the landing contact hole, it is possible to shorten the manufacturing process time and simplify the process compared to the conventional technology.

Claims (7)

게이트용 스페이서가 구비된 게이트들 및 접합영역이 형성된 실리콘기판을 마련하는 단계; Preparing a silicon substrate on which gates including gate spacers and a junction region are formed; 상기 게이트들 사이에 층간절연막을 일부 매립하는 단계;Partially filling an interlayer insulating film between the gates; 상기 게이트를 덮도록 층간절연막을 포함한 기판 전면 상에 폴리실리콘막을 형성하는 단계;Forming a polysilicon film on the entire surface of the substrate including the interlayer insulating film to cover the gate; 상기 폴리실리콘막 및 층간절연막이 게이트용 스페이서 양측벽에 스페이서 형태로 잔존하도록 폴리실리콘막을 식각함과 아울러 층간절연막을 식각하는 단계;Etching the polysilicon film and etching the interlayer insulating film such that the polysilicon film and the interlayer insulating film remain on both sidewalls of the gate spacer; 상기 잔존된 층간절연막을 제거하여 접합영역을 완전히 노출시키는 랜딩콘택홀을 형성하는 단계;Forming a landing contact hole to completely expose a junction region by removing the remaining interlayer insulating layer; 상기 폴리실리콘막을 포함한 기판 결과물에 대해 SEG 공정을 수행하여 상기 콘택홀의 저면 부분인 실리콘기판의 접합영역을 성장시킴과 아울러 상기 폴리실리콘막 부분을 성장시키는 단계; Performing a SEG process on the substrate product including the polysilicon film to grow a junction region of a silicon substrate, which is a bottom portion of the contact hole, and to grow the polysilicon film portion; 를 포함하는 반도체 소자의 랜딩플러그콘택 형성방법.Landing plug contact forming method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 폴리실리콘막은 490∼650℃의 온도에서 SiH4, N2 및 PH3 가스를 사용하여 형성하는 것을 특징으로 하는 반도체 소자의 랜딩플러그콘택 형성방법. The polysilicon film is a landing plug contact forming method of a semiconductor device, characterized in that formed using SiH 4 , N 2 and PH 3 gas at a temperature of 490 ~ 650 ℃. 제 1 항에 있어서,The method of claim 1, 상기 폴리실리콘막은 500∼1000Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 랜딩플러그콘택 형성방법. The polysilicon film is a landing plug contact forming method of a semiconductor device, characterized in that formed to a thickness of 500 ~ 1000Å. 제 1 항에 있어서,The method of claim 1, 상기 폴리실리콘막 및 층간절연막이 게이트용 스페이서 양측벽에 스페이서 형태로 잔존하도록 폴리실리콘막을 식각함과 아울러 층간절연막을 식각하는 단계는,Etching the polysilicon film and the interlayer insulating film so that the polysilicon film and the interlayer insulating film remain in the spacer form on both side walls of the gate spacer, 상기 폴리실리콘막 및 층간절연막이 게이트용 스페이서 양측벽에 100∼200Å 두께로 잔존하도록 수행하는 것을 특징으로 하는 반도체 소자의 랜딩플러그콘택 형성방법. And wherein the polysilicon film and the interlayer insulating film remain on both side walls of the spacer for the gate in a thickness of 100 to 200 Å. 제 1 항에 있어서,The method of claim 1, 상기 잔존된 층간절연막의 제거는, Removal of the remaining interlayer insulating film, H2SO4:H2O2의 비율이 50:1인 용액과 NH4F:HF의 비율이 9:1인 용액을 사용하여 수행하는 것을 특징으로 하는 반도체 소자의 랜딩플러그콘택 형성방법. A method of forming a landing plug contact for a semiconductor device, comprising using a solution having a ratio of H 2 SO 4 : H 2 O 2 of 50: 1 and a solution having a ratio of NH 4 F: HF of 9: 1. 제 1 항에 있어서,The method of claim 1, 상기 SEG 공정은 700∼1100℃의 온도에서 수행하는 것을 특징으로 하는 반도체 소자의 랜딩플러그콘택 형성방법. The SEG process is a landing plug contact forming method of a semiconductor device, characterized in that performed at a temperature of 700 ~ 1100 ℃. 제 1 항에 있어서,The method of claim 1, 상기 SEG 공정은 100∼300sccm 유량을 갖는 SiH2Cl2 가스와 50∼200sccm 유량을 갖는 HCl 가스 및 1∼500sccm 유량을 갖는 PH3 가스를 사용하여 수행하는 것을 특징으로 하는 반도체 소자의 랜딩플러그콘택 형성방법. The SEG process is SiH 2 Cl 2 gas having a flow rate of 100-300sccm, HCl gas having a flow rate of 50-200sccm and PH 3 having a flow rate of 1-500sccm Landing plug contact forming method of a semiconductor device, characterized in that performed using a gas.
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