KR20080072892A - A method, system and computer-readable code for testing of flash memory - Google Patents

Abstract

Methods, systems and devices for testing flash memory dies are disclosed. According to some embodiments, during the post-wafer sort stage of device manufacture, a plurality of flash memory devices, each of which includes a flash controller die and at least one flash memory die associated with a common housing, are subjected to a testing process, for examples, a batch testing process or a mass testing process. During testing, a respective flash controller residing on a respective flash controller die executes at least one test program to test one or more respective flash memory dies of the respective flash device. A testing system including at least 100 of the flash memory devices and a mass-testing board is disclosed. Furthermore, flash memory devices where the flash controller is operative to test one or more of the flash memory dies are disclosed. Exemplary testing includes but is not limited to bad block testing.

Description

A method for testing in flash memory, a storage medium storing system and computer readable code {A METHOD, SYSTEM AND COMPUTER READABLE CODE FOR TESTING OF FLASH MEMORY}

FIELD OF THE INVENTION The present invention generally relates to the manufacture of flash memory devices, and more particularly to the testing of flash memory dies during manufacture.

Single Bit and Multi-Bit Flash Memory Cells

Flash memory devices have been known for many years. In general, each memory cell in a flash memory device stores one bit of information. A common way of storing bits in flash memory cells is by supporting two states of memory cells. One state represents a logical "0" and the other state represents a logical "1".

In a flash memory cell, two states have a floating gate overlying the cell's channel (the region connecting the source and drain elements of the transistor of the cell), and two valid states for the amount of charge stored in the floating gate. It is implemented by having In general, one state has a charge of zero at the floating gate and is the unwritten state of the cell after being erased (generally defined to represent a state of "1"), and the other state is the floating gate Has a positive amount of negative charge (defined to represent a state of "0"). Having a negative charge on the gate causes the threshold voltage of the cell's transistor (i.e., the voltage that must be applied to the transistor's control gate to conduct the transistor) to increase. The stored bits can be read by checking the threshold voltage of the cell. The bit value is "0" when the threshold voltage is higher and the bit value is "1" when the threshold voltage is lower. In practice, it is not necessary to accurately read the threshold voltage of the cell. All that is needed is to correctly identify which of the two states of the cell is currently located. For this purpose, it is sufficient to compare the threshold voltage against a reference voltage value between two states, and as a result, to determine whether the threshold voltage of the cell is below or above the reference value.

1A (prior art) graphically illustrates how this works. In particular, FIG. 1A shows the distribution of the threshold voltages of a large cell population. Because cells in flash devices do not exactly match their characteristics and behavior (for example, due to small variations in impurity concentration, or defects in the silicon structure), the same programming operation is applied to all cells. It is not that all cells have exactly the same threshold voltage. Instead, the threshold voltages are distributed as shown in FIG. 1A. Cells that store a value of "1" generally have a negative threshold voltage, such that most of the cells have a smaller number of cells having a threshold voltage smaller or larger than the center voltage of the left peak, and the left side of FIG. 1A. Have a threshold voltage close to the center voltage peak of the peak (labeled 1). Similarly, cells that store a value of "0" generally have a positive threshold voltage so that most cells have a smaller number of cells that have a threshold voltage that is smaller or larger than the center voltage of the right peak, and FIG. 1A. Have a threshold voltage close to the center voltage of the right peak of (labeled 0).

In recent years, new types of flash devices have emerged on the market, using a technique conventionally referred to as "multi-level cells" or MLC for short. The term " multi-level cell " is misleading because, as described above, a flash memory having a single bit per cell also uses multiple, i.e., two levels. Thus, the term " single bit cell " (SBC) refers hereinafter to two levels of memory cells, and the term " multi-bit cell " (MBC) refers to two or more levels, ie one or more memory cells per cell. Currently, most MBC flash memories are two bits per cell, so an example using this MBC is given below. However, it should be understood that the present invention is equally applicable to flash memory devices that support more than two bits per cell. A single MBC cell that stores two bits of information is in one of four different states. Since the "state" of a cell is represented by its threshold voltage, an MBC cell supports four different effective ranges for the cell's threshold voltage. 1B (Prior Art) shows a threshold voltage distribution for a typical 2 bit MBC cell per cell. As expected, Figure 1B has four peaks, each of which corresponds to one state. For SBC, each state is actually a range of voltages and not a single voltage. When reading the contents of a cell, the cell's threshold voltage must be correctly identified within a defined voltage range. For examples of prior art examples of MBC flash devices, see US Pat. No. 5,434,825 to Harari, which is hereby incorporated by reference in its entirety for reference.

For example, a cell designated for MBC operation in four states is generally operable as an SBC cell with two states. For example, US Pat. No. 6,426,893 to Conley et al., Incorporated herein by reference in its entirety for explanation, uses both MBC and SBC modes within the same device and operates at the highest density in MBC mode. Selecting a particular part of the device, it is disclosed that the other part is used in SBC mode to provide better performance.

MBC devices offer significant cost benefits. MBC devices with 2 bits per cell require about half the silicon wafer area than similar capacity SBCs. However, there are drawbacks to using MBC flash. The average read and write time of MBC memory is longer than SBC memory, resulting in lower performance. In addition, the reliability of MBC is lower than that of SBC. The difference between the threshold voltage ranges in the MBC is much smaller than in the SBC. Thus, disturbances at threshold voltages that were not high in SBC due to the large gaps between the two states (e.g. leakage of stored charges causing threshold voltage drift, interference from operation on neighboring cells, etc.) may cause the MBC cell to fail. Moving from one state to another causes an error bit. The end result is a lower quality specification of the MBC cell in terms of data retention time or durability of the device over multiple write / erase cycles.

Another consequence of the lower reliability of MBC devices compared to SBC devices is the level required for error correction. Manufacturers of SBC NAND flash devices generally recommend that users apply an error correction code (ECC) that allows one-bit error correction on each page of 512 bytes of data. However, data sheets for MBC NAND flash devices generally recommend applying ECC to correct 4-bit errors on each page of 512 bytes of data. For a 2048-byte page, as in the case of a NAND device known as a "high-capacity block device," the suggestion is to apply error correction for each part of 512 of the page. The present invention applies to all types of flash devices regardless of page size. In this application, the term "N-bit ECC" refers to an ECC design that can correct N-bit errors in 512 bytes of data, regardless of whether 512 bytes are one page in size, one page in size, or one page in size. Point to.

Flash memory Of die Testing

Flash memory dies require extensive testing before being used for production. This is especially true for NAND flash. One reason for this is that the flash device may have a bad block that should not be used. A block is the smallest chunk of cells that can be erased in a single erase operation, and it generally contains multiple pages of the smallest chunks of cells that can be written in a single write operation. If a block cannot be reliably erased with all "1" states, or if one or more pages of the block cannot be reliably programmed, the block can be replaced by another block by physically trimming the die or as a bad block. By displaying, it should be possible to prevent software writing to the device from using it.

A given flash memory die can receive other tests as well, but testing on bad blocks is generally the most time-consuming. This is because testing for bad blocks generally involves writing to each page and every page and deleting each and every block of the device. The writing and erasing is generally repeated one or more times to perform bad block testing under different patterns of recorded data, different temperatures, or different variations of testing parameters.

Wafer of manufacture Sort  During the stage Testing

In some cases full testing of the flash memory is completed while the die is part of the silicon wafer from which it is manufactured and before the wafer is separated into multiple dies. The stage is generally referred to as "wafer sort". These dies that have been tested at the wafer sort stage are commonly referred to as Known Good Dies ("KGD"). Using a KGD flash memory die is advantageous when the flash memory die is assembled with an expensive second die such as a microprocessor in a multi-chip package (“MCP”). If the memory die is not fully tested before the MCP assembly, testing for it is completed after the memory and microprocessor are assembled together into one device. Then, if some of the memory dies are found defective in MCP stage testing, these MCP devices must be discarded. This not only results in the loss of memory die (which is discarded in any way), but also the loss of expensive microprocessor die and packaging costs.

However, the manufacture of KGD flash memory dies is not straightforward. The test equipment used for the wafer salting stages is complex and expensive, and the use of such equipment over long periods of time increases the cost of testing. In addition, bad block testing is not well suited to the execution of tests on multiple dies parallel to the waiter sort stage. Unlike the normal signal timing test, where all tested dies on the wafer proceed in exactly the same test sequence and the result of the test is a "go / stop" decision for each die, in bad block testing, each die is located at a different location. With a bad block, it represents different timings during testing, as a result of which the testing equipment must handle each die individually. This complicates bad block testing at the wafer sort stage and makes it more expensive.

Another factor is more significant to further increase the cost of bad block testing at the wafer sort stage. Many flash memory manufacturers require the test to be performed at a temperature different from room temperature. This means that wafer sort testing equipment should be able to perform testing while the tested wafer is maintained at a particular temperature. This also increases the cost of testing equipment and consequently increases the cost of testing per die.

During manufacturing Packaged device  Flash memory Of die Testing

For the above reasons, most flash memory dies are not manufactured as KGD. Instead, the testing of the flash device is divided into two parts. At the wafer sort stage, only a minimal test can be performed and discarded simultaneously for the purpose of identifying clearly bad dies. The wafer is then cut into individual dies, and each die is packaged into the device package type to be sold. For NAND flash devices, this is typically a TSOP, BGA, or LGA package commonly used in electronic assemblies and printed circuit boards (PCBs). The remaining testing, including time-consuming bad block testing, is performed on the packaged flash device during later stages of manufacture (ie, after the wafer sort stage). Thus, any packaged device is mounted on a testing board (ie, in a device-manufacturing facility), and the remaining tests are then run. When testing a packaged device, unlike a wafer salting stage where access to the die in the wafer is difficult, the flash device is conveniently handled and interfaced, eliminating the need for expensive probing equipment, such as the type required for wafer salting. .

However, even if packaged in a convenient package, testing NAND flash devices against bad blocks is a very expensive task. The reason for this is that due to the requirements for individual handling of each device (described above), testing must be performed using an expensive memory tester that can only test a limited number of devices (typically around 100) at the same time. The test time for each device is very long and the testing cost is very high. This is shown in block diagram in FIG.

Thus, referring to FIG. 2, note that the flash memory device 110A to be tested is coupled to the memory tester 106. The flash memory device 110A includes a flash controller residing on the flash controller die 102 (including the processor 104) and a flash memory residing on the one or more flash memory dies 100 including a plurality of memory cells. ). Thus, the flash controller and flash memory are on different dies.

Memory tester 106 includes a processor 108. The testing program is executed by the memory tester 106 (in some examples, the testing program is also stored in nonvolatile memory of the memory tester 106). Testing programs that operate to test flash memory die 100 (eg, individual memory cells of flash memory die 100) are executed by general purpose processor 108 residing within the memory tester. In Fig. 2, the processor 108 executing the test program is indicated by an asterisk. Although only a single flash memory device is shown in FIG. 2, in general, a plurality of devices (generally about 100), as described above, are tested together in a batch (ie, nearly simultaneously).

Note that in general, testing of MBC flash devices takes longer than testing SBC flash devices. This is especially true for bad block testing. This is because flash operations, especially write operations, are much slower in MBC flash. Bad block testing typically requires a number of such operations because each page of the device is written multiple times during the test. Since the number of bits per cell is higher in MBC flash, the write operation is slower. Similarly, testing of SBC flash devices is faster than testing 2-bit MBC flash devices per cell faster than testing 4-bit MBC flash devices per cell. If more MBC devices are used, this means that the cost of flash testing increases.

Thus, having a system and method for testing flash memory devices in a cost effective manner has many advantages. Having a new flash memory device that can be conveniently tested in a cost-effective manner has many advantages.

The foregoing requirements are met by a number of aspects of the present invention.

According to one embodiment of the present invention, it surprisingly discloses to reduce the cost of flash memory device testing by offloading a test from test equipment, thereby eliminating the need for expensive use of expensive memory testers. In particular, this is typically accomplished by setting the flash controller of the flash device (ie, during the 'post-wafer sort' stage of manufacture) to execute a test program executed by the memory tester described above.

Note that device testing is an important manufacturing stage, and that the methods, systems, and devices provided by certain embodiments of the present invention generally reduce the cost of device manufacturing, particularly the testing phase of device manufacturing.

First, a device manufacturing method comprising: (a) each flash memory device (i) each flash memory residing on at least one flash memory die, and (ii) a flash controller separate from each at least one flash memory die Each flash controller residing on an image, wherein each of the at least one flash memory die and each flash controller comprises a flash controller associated with a respective common housing; And (b) subjecting the plurality of manufactured flash memory devices to a testing process, wherein each flash memory controller executes at least one test program to test at least one respective flash memory die. A method is disclosed.

According to some embodiments, the testing process is a mass testing process.

According to some embodiments, placing the flash memory device in a mass testing process comprises combining a plurality of flash memory devices to a single testing board, and using a testing board to transfer power to the plurality of flash memory devices. Include.

According to some embodiments, the presently disclosed method further comprises (c) following the testing process, selling the plurality of flash memory devices as original equipment.

According to some embodiments, each flash memory device is manufactured as a respective multi-chip package.

According to some embodiments, each flash memory device is manufactured as a respective memory card.

According to some embodiments, each flash memory controller and flash memory is installed in a common multi-chip packaging.

According to some embodiments, the flash memory of each flash memory device has a plurality of flash memory dies, and each flash controller tests each of the plurality of flash memory dies by executing at least one test program.

According to some embodiments, for each flash memory device, each flash controller and each at least one flash memory die are installed on each common printed circuit board.

According to some embodiments, for each flash memory device, at least one test program resides at least partially within non-volatile memory of each flash controller.

According to some embodiments, for each flash memory device, the test program resides at least partially within each flash memory.

According to some embodiments, at least one test program executed by each flash controller identifies a bad block in each flash memory.

According to some embodiments, at least one test program executed by each flash controller is valid for bad block testing of multiple memory cells of each flash memory.

According to some embodiments, at least one test program executed by each flash controller is valid for bad block testing of most memory cells of each flash memory.

According to some embodiments, at least one test program executed by each flash controller is valid for bad block testing of almost all memory cells of each flash memory.

According to some embodiments, at least one test program executed by each flash controller tests a memory cell of each flash memory that is multi-bit per cell mode.

According to some embodiments, execution of at least one test program comprises: i) determining whether error correction is successful during a flash memory operation; And ii) if the determination indicates that the error correction failed, recording a test failure.

First, as a testing system, a) each flash memory device resides on a respective flash controller die separate from each flash memory residing on each at least one flash memory die and each at least one flash memory die. Each flash controller, wherein each of the at least one flash memory die and each flash controller die is associated with a respective respective housing in common, and each flash memory controller is configured to test each of the at least one flash memory die. At least one hundred plurality of flash memory devices operative to execute the at least one test program for the purpose; And b) a mass-testing board having at least 100 ports configured to power a flash memory device, wherein each port is configured to power power to each flash memory device.

According to some embodiments, at least one test program executed by each flash controller operates to validate multiple bad block testing of memory cells of each flash memory.

According to some embodiments, at least one test program executed by each flash controller operates to validate a majority of bad block testing of memory cells of each flash memory.

According to some embodiments, at least one test program executed by each flash controller operates to validate bad block testing of almost all memory cells of each flash memory.

According to some embodiments, the system is operative to test at least 100 plurality of flash memory devices at about the same time.

First, a flash memory device, comprising: a) flash memory residing on at least one flash memory die; And b) a flash controller residing on a flash controller die separate from at least one flash memory die, i) the flash memory and the flash controller are associated with a common housing, and ii) the flash controller is a predetermined number of times. Only discloses a flash memory device configured to execute at least one test program for testing at least one flash memory die.

First, a flash memory device, comprising: a) flash memory residing on at least one flash memory die; And b) a flash controller residing on a flash controller die separate from at least one flash memory die, iii) the flash memory and the flash controller being associated with a common housing, and ii) the flash controller being at least one A flash memory device is set up to execute at least one test program for testing a flash memory die and writing at least some test results into the flash memory.

First, a flash memory device, comprising: a) flash memory residing on at least one flash memory die; And b) a flash controller residing on a flash controller die separate from at least one flash memory die, i) the flash memory and the flash controller are associated with a common housing, and ii) the flash controller is connected to the flash memory. A flash memory device set up to validate bad block testing of a plurality of memory cells in a system.

These and further embodiments will be apparent from the detailed description and examples that follow.

1A-1B provide a graphical illustration of the distribution of threshold voltages of a large population of memory cells (prior art).

2 provides a block diagram of a prior art system for testing a flash memory device.

3 provides a block diagram of a system for testing a flash memory device in accordance with an exemplary embodiment of the present invention.

The invention is described according to certain, illustrative embodiments. It will be appreciated that the invention is not limited to the disclosed exemplary embodiments. It will be understood that the described method of manufacturing a flash memory device, a system for testing a flash memory device, and not all features of the flash memory device are essential to implementing the claimed invention in any particular one of the appended claims. Various elements and features of the device are described to fully enable the present invention. It is also to be understood that throughout the present description of the process or method, the steps of the method may be performed in any order or concurrently, unless it is clear that either step is in accordance with another step performed first.

Flash memory device 110 and Testing  system

Referring to FIG. 3, it is described that an embodiment of the invention relates to testing of flash memory die 100 of flash memory device 110B. During testing, the flash memory device 110B is coupled back to the 'bulk' testing board 114 (eg, to exchange data and / or receive power). In general, each mass testing board has a 'multiple' port (e.g., at least, for coupling with a plurality of flash memory devices 110B (e.g., at least 100, or at least 200, or at least 500). 100, or at least 200, or at least 500). The 'bulk' testing board 114, where multiple devices are tested at about the same time, provides an economical scale, thereby helping to reduce the costs associated with the testing stage of device manufacturing.

The flash memory device 110B includes a flash memory residing on at least one flash memory die 100 (each flash memory die 100 having a plurality of flash memory cells), the flash memory die 100 and A flash controller residing on a separate flash controller die 102. The flash controller is operative to, for example, read data from and / or write data to flash cells. Other exemplary functions of the flash controller include error detection and / or correction, and individual devices (eg, host devices such as microcomputers) access memory cells of the flash memory die 100 (read access and / or write access). And providing an interface capable of doing so, including but not limited to a NAND interface and a USB interface.

As shown in FIG. 3, the flash controller 102 is shown to control and test a single flash memory die 100. Nevertheless, embodiments in which the flash controller 102 is configured to test a plurality of flash memory dies 100 (eg, all together or in a common housing 112 together) have also been contemplated by the inventors. Note that

Note that each flash memory die of each flash memory device 110B with each flash controller 102 is associated with a respective “housing” 112. As used herein, when one or more die is associated with a “housing”, each die: (a) resides in the housing, (b) resides on the housing, or (c) or attaches to the housing. Or (d) or any combination of the above.

The term "housing" refers to a printed circuit board (i.e. where the flash memory die and flash controller reside together on the same printed circuit board) and a multi-chip package (i.e. both the flash memory die 100 and the flash controller die 102). Together in a multi-chip package).

There are a number of possible reasons for including the flash controller and flash memory die 100 together in a common housing 112:

a. In many applications, operating a flash device without a controller is not useful. For example, if the flash technology has low reliability, it leads to a high error rate. This is for example the case of MBC flash technology which stores large bits per cell which stores more than 4 bits per cell. In this case, it is useless to connect the flash device directly to the host processor because a number of errors make use of the data read by the host. Instead, a dedicated flash controller is connected between the flash device and the host, which implements the error correction code design. The controller exports to the host an error-free flash device that the host interfaces with, and if it is error-free, it is used to interface with the stand-alone flash device using the same interface. This arrangement is a United States under the name "A NAND FLASH MEMORY CONTROLLER EXPORTING A NAND INTERFACE" of one of the inventors, filed January 6, 2006, which is hereby incorporated by reference in its entirety for purposes of explanation. Patent application 11 / 326,336. The controller die and flash memory die (or dies) are then packaged together as an MCP device and sold as one component.

b. In many cases, it is more convenient to interface the host device to the memory device using some standard interface. For example, the host processor has a built-in USB interface and preferably has a flash memory accessed through this interface. The flash memory is installed on the same board as the processor or in a removable memory device such as a USB flash drive (USB) such as DiskOnKey sold by M-Systems Flash Disk Pioneers, Kpa-Saba, Israel. In this case, there is a need for a USB controller to connect between the host processor and a flash memory die (or dies). The USB controller interfaces to a flash device using an appropriate flash interface and to a host using a USB interface. Here, the USB controller die and the flash memory die may also be packaged together as an MCP device and sold as one component.

Flash memory Of die Testing

After the flash memory die 100 is operated in conjunction with the controller 102 (eg, after the die and the controller are assembled to the common housing 112), the processing power of the controller 102 becomes available. Instead of performing all the tests of the flash memory die by the test equipment (in particular, using the processor 108 of the prior art memory tester 106), some or all of these tests are placed on the flash controller die 102. Is performed by an installed flash controller. Thus, as shown in FIG. 3, the processor 104 of the flash controller 102 configured to execute one or more test programs is indicated by an asterisk.

One non-limiting example of testing performed using a flash controller is bad block testing. This type of testing does not require measurement of timing, analog signals (such as current or voltage) or other complex tasks. All that is needed for bad block testing is to issue blocks for block deletion, data writing and reading, and then comparing the recorded data with the read data. This is within the functionality of a simple processor of the type commonly found in flash controllers. For example, the above comparison is performed by the ALU of the processor 104 of the flash controller, for example.

In general, when bad block testing is performed during the manufacturing process, most or all of the flash memory cells are tested (not just representative samples). This helps to ensure that the high quality flash device is transported and sold on raw equipment.

Thus, in various embodiments, multiple blocks of a given flash memory die 100 are subjected to bad block testing using a test program executed by the flash controller 102. In some embodiments, a majority (ie, at least 75% of a given flash memory die 100) or almost all (ie, at least 90% of a given flash memory die 100), or all blocks of a given flash memory die are flashed. Bad block testing is performed using the controller 102.

Although the related embodiments have been described where testing of flash memory occurs at a time close to the manufacture of the flash memory die, the present invention is not limited to this case. Instead of selling MCP devices or assembled memory cards, flash memory manufacturers sell chipsets of two dies (or more) of controller die and flash memory die (or dies). The buyer of the chipset then mounts the chipset in a memory card or another type of product. In this case, testing of the flash takes place only on the buyer's side, with the assembled card first powered up. After testing, the buyer of the chipset sells the assembled card as a raw device.

block Testing  Board (114)

An additional advantage of this arrangement (ie, shown in FIG. 3) is the structure of the testing board. Since the flash device is individually tested by its controller, there is no need to use a memory tester, so the following benefits are achieved:

The testing board is designed to accommodate a number of devices (eg at least 100, or at least 200, or at least 500), all of which are tested simultaneously in a mass testing process. As used herein, a 'bulk testing process' is a batch testing process performed on multiple devices (eg, at least 100, or at least 200, or at least 500) at about the same time. Note that the bulk testing process can reduce testing costs.

The complexity of the testing board is reduced. Thus, instead of interfacing with a memory tester with strict constraints on circuit design and implementation, the testing board 114 provides only a simple interface with power to the test controller to the device (e.g., a personal computer may host testing). Used for board).

flash Device  Produce, Testing  And transport

A general embodiment of the present invention for flash device testing during a manufacturing process at a manufacturing facility includes the following steps:

a. Wafers with multiple flash memory dies are fabricated.

b. A wafer sort testing stage is performed on the wafer. Only basic "continue / stop" tests are performed for each die. The failed die is marked as bad and is removed from further processing.

c. The wafer is cut into a die.

d. The flash memory die is matched with the controller die and assembled into a multi-chip package (MCP).

e. The MCP device is mounted on a testing board, which is sent to a testing setup and power is supplied to it. The testing setup is a single station such as a personal computer (PC).

f. Within each MCP device, the controller typically starts executing code from ROM memory in the controller.

g. Each controller tests its own flash memory die or dies. The bad blocks found are written to flash memory as an intermediate list of associated blocks or all bad blocks. In addition to the bad block testing, other tests are also performed.

h. The testing station reads the results of the test for each device as reported by its controller. A failed device (eg by having too many bad blocks) is identified. Tested devices mark their bad blocks as needed according to their specifications. For example, each bad block is marked by writing a specific byte of its first page as " 0 ".

Testing of the flash memory die 100 by the controller 102 is not limited to bad block testing, and any test (e.g., no special equipment is needed and is easily implemented by the processor of the controller). Note that this is done to save additional testing costs.

After testing in a manufacturing facility, the flash memory device 110 is transferred and sold as 'raw equipment' in some embodiments. The original equipment may include one or more flash memory dies 100 that operate to link within a common housing 112 to a flash controller 102 that is used to execute a test program of flash memory die (s) 100. Include. Thus, in some embodiments, it is important to perform full bad block testing of the device before transferring it from the manufacturing facility, as described above. "Original equipment" refers to electronic products that are not distributed to end users. Thus, as used herein, 'raw equipment' refers to flash in terms of 'user data' (ie, testing the flash device and / or setting up the flash device (ie, 'preloading' the software into the flash device). Data different from the data recorded in the memory cell) refers to equipment which is not recorded.

Flash memory Of die 100  Memory cell Testing  For computer readable code storage

Note that the testing program executed by the flash controller 102 is stored in any nonvolatile memory, volatile memory, and / or any combination thereof. Thus, in one example, the testing program is stored in a ROM in the controller 102. According to another example, a testing program can be stored in a flash device and the controller can be loaded into its RAM upon power up and then run. In this case, the testing program is written to flash memory at the end of the wafer sort stage.

In some embodiments, the flash memory device 110 is preferably set to execute only in the first case, rather than the controller 102 executing each time the device is powered up. This particularly includes directives to allow the test program to validate 'complete' or 'large' bad block testing (ie, at least a large number of flash memory cells of flash memory die 100). For this termination, in some embodiments, the device 110, when the controller 102 has completed testing, indicates that the controller 102 indicates that a particular testing stage has already been performed (ie, flash memory die 100). In one or more memory cells). On powering up the device, the controller 102 checks the flag (e.g., the controller 102 always checks the flag on powering up the device) and runs the testing program only if the flag is not set. do.

The method provided by a particular embodiment of the present invention reduces the cost of flash memory testing since time-consuming tests such as bad block testing are performed using simple and inexpensive equipment, unlike conventional methods. When a flash device fails, we save even more in the cost of testing, even in the case of the cost loss of its accompanying controller and package, to compensate for this loss.

ECC Use of

In many devices, the flash controller installed on the die of the flash controller 102 includes an ECC. Thus, in some embodiments, ECC may also be used during testing. For example, ECC is used for testing, and the ECC reports a failure for data correction, and the test program reports a test failure. In many embodiments, this eliminates the need to compare each bit of data with its "true" value. Thus, in accordance with these embodiments, it is possible to query the ECC circuit for a result of "yes / no" without incurring a time penalty associated with data bit comparison.

Thus, in one example, it is determined that the occurrence of a two bit error in the page should not be considered a failure since the ECC used can correct for two errors. Implementing these criteria in prior art test equipment is cumbersome and expensive. Running the test using the controller makes this very simple, causes the controller 102 to correct the data read from the flash, and is reported as a failure only if the controller fails to correct the error.

Further discussion

In some embodiments, the flash memory device uses both SBC and MBC modes, both of which are tested and the SBC and MBC tests are separated at the testing stage. Thus, according to some examples, testing of the flash cells in the wafer sort stage includes testing the cells in SBC mode, which is a high speed operation. Testing of the flash cell in MBC mode, which is a relatively long operation, is delayed with respect to the MCP stage. Of course, various modifications are possible in the art, such as, for example, performing a small sample of the MBC test at the wafer sort stage and performing a bulk of the MBC test at the MCP stage.

Note that the present invention is not limited to MCP devices. Any method in which the controller is in contact with the flash memory and which controller is used to perform a test of the flash memory is within the scope of the present invention. For example, in the manufacture of memory cards such as secure digital ("SD") or multimedia cards ("MMC"), flash memory devices (or devices) and controllers are mounted on small cards. The component is a packaged die or bare die. In this case, the card replaces the MCP and functions as a common 'housing' 112, and upon powering the card, the controller executes the flash testing program as described above.

Although a NAND type floating-gate flash memory device has been explicitly described, the present invention also relates to other flash memories such as NOR-type floating gate flash memory or NROM-type flash memory without using floating gates.

In the description and claims of the present application, each verb "including", "comprises", "having" and its conjugation forms include that the object or object of the verb is the subject or member of the verb, member, element, element or Used to indicate that some parts do not need to be fully listed.

All references cited in this text are incorporated by reference in their entirety. Citations of references do not constitute an admission that the references are prior art.

"a" and "an" are used in the text to refer to one or more (ie, at least one) of the grammatical objects in the paragraph. By way of example, “an element” means one or more elements.

The word "comprising" means "including but not limited to" in the text and is used interchangeably.

The meaning of "or" means "and / or" and is used interchangeably unless expressly indicated otherwise.

The word "such" means "such as, but not limited to," and is used interchangeably therewith.

The invention has been described using the detailed description of the embodiments provided by way of illustration and not intended to limit the scope of the invention. The described embodiments have different features, but not all of them are necessary in all embodiments of the present invention. Some embodiments of the present invention utilize only some features, or possible combinations thereof. It will be apparent to those skilled in the art that embodiments of the invention having different combinations of the features mentioned in the described embodiments and variations of the embodiments of the invention described.

Claims (25)

In the device manufacturing method, a) manufacturing a plurality of flash memory devices, each flash memory device being Iii) each flash memory residing on at least one respective flash memory die, and (Ii) each flash controller residing on a flash controller die separate from each of said at least one flash memory die, wherein each said at least one flash memory die and each flash controller die are associated with a respective common housing; Manufacturing a plurality of flash memory devices having a flash controller; And (b) subjecting the plurality of manufactured flash memory devices to a subject of a testing process, wherein each of the flash memory controllers test at least one of the at least one respective flash memory die Device manufacturing method characterized in that for executing. The method of claim 1, And wherein said testing process is a mass testing process. The method of claim 2, Passing the flash memory device through the mass testing process includes coupling the plurality of flash memory devices to a single testing board, and using a testing board to transfer power to the plurality of flash memory devices. Device manufacturing method, characterized in that. The method of claim 1, (c) subsequent to the testing process, selling the plurality of flash memory devices as original equipment. The method of claim 4, wherein Wherein each flash memory device is fabricated as a respective multi-chip package. The method of claim 4, wherein Wherein each flash memory device is manufactured as a respective memory card. The method of claim 1, Wherein each flash memory controller and flash memory are installed in a common respective multi-chip packaging. The method of claim 1, Each of the flash memories of each of the flash memory devices has a plurality of flash memory dies, and each of the flash controllers test each of the plurality of flash memory dies by executing the at least one test program. Device manufacturing method. The method of claim 1, For each of the flash memory devices, each of the flash controller and each of the at least one flash memory die is installed on a respective common printed circuit board. The method of claim 1, For each flash memory device, at least one said test program resides at least partially within non-volatile memory of each said flash controller. The method of claim 1, For each flash memory device, the test program resides at least partially within each flash memory. The method of claim 1, At least one said test program executed by each said flash controller identifies a bad block in said each flash memory. The method of claim 1, And at least one said test program executed by each said flash controller performs bad block testing of a plurality of memory cells of said each flash memory. The method of claim 1, At least one said test program executed by each said flash controller performs bad block testing of most of the memory cells of said each flash memory. The method of claim 1, At least one said test program executed by each said flash controller performs bad block testing of almost all memory cells of said each flash memory. The method of claim 1, At least one said test program executed by each said flash controller tests memory cells of each said flash memory at multiple bits per cell mode. The method of claim 1, Execution of the at least one test program is: Iii) determining whether error correction is successful while the flash memory is operating; And Ii) if the determination indicates that the error correction failed, recording a test failure. In the testing system, a) at least 100 plurality of flash memory devices, each flash memory device being separate from each flash memory residing on each at least one flash memory die and each at least one flash memory die; Each flash controller residing on a lash controller die, wherein each of the at least one flash memory die and each flash controller die is associated with a respective respective housing in common, and each of the flash memory controllers is associated with each of at least At least one hundred plurality of flash memory devices operative to execute at least one test program for testing one said flash memory die; And b) a mass-testing board having at least 100 ports configured to supply power to said flash memory device such that each said port supplies power to each said flash memory device; Testing system, characterized in that. The method of claim 18, At least one said test program executed by each said flash controller is operative to perform bad block testing of a plurality of memory cells of each said flash memory. The method of claim 18, At least one said test program executed by each said flash controller is operative to perform bad block testing of a plurality of memory cells of each said flash memory. The method of claim 18, At least one said test program executed by each said flash controller is operative to perform bad block testing of almost all memory cells of each said flash memory. The method of claim 18, And the system is operative to test the at least 100 plurality of flash memory devices at about the same time. As a flash memory device, a) flash memory residing on at least one flash memory die; And b) a flash controller residing on a flash controller die separate from said at least one flash memory die, Iii) the flash memory and the flash controller are associated with a common housing, Ii) the flash controller is configured to execute at least one test program for testing the at least one flash memory die only a predetermined number of times. In a flash memory device, a) flash memory residing on at least one flash memory die; And b) a flash controller residing on a flash controller die separate from said at least one flash memory die, Iii) the flash memory and the flash controller are associated with a common housing, Ii) the flash controller is configured to execute at least one test program for testing at least one of the flash memory dies and writing at least some test results in the flash memory. In a flash memory device, a) flash memory residing on at least one flash memory die; And b) a flash controller residing on a flash controller die separate from said at least one flash memory die, Iii) the flash memory and the flash controller are associated with a common housing, Ii) the flash controller is configured to perform bad block testing of a plurality of memory cells of the flash memory.

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