JPS6447148A - Relay line data control system between packet exchange and packet composing/ decomposing device - Google Patents

Relay line data control system between packet exchange and packet composing/ decomposing device

Info

Publication number
JPS6447148A
JPS6447148A JP20320787A JP20320787A JPS6447148A JP S6447148 A JPS6447148 A JP S6447148A JP 20320787 A JP20320787 A JP 20320787A JP 20320787 A JP20320787 A JP 20320787A JP S6447148 A JPS6447148 A JP S6447148A
Authority
JP
Japan
Prior art keywords
relay line
decomposing
packet
line data
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20320787A
Other languages
Japanese (ja)
Inventor
Takayuki Teratsu
Shigehiro Konno
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20320787A priority Critical patent/JPS6447148A/en
Publication of JPS6447148A publication Critical patent/JPS6447148A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the discrepancy of relay line information between a decomposing device and an exchange, by transferring relay line information by using a non-number control information transfer frame in an information link control procedure in the line speed synchronously with a prescribed clock to set the relay line information from a packet exchange to a packet composition/ decomposition equipment. CONSTITUTION:A UI frame 6 in the HDLC procedure is used for the transmission of a relay line data such as a link parameter specifying the logical specification of the link or the line speed between the packet exchange 3 and the packet composing/decomposing device 4 and the frame is sent in the speed synchronously with the clock. The UI frame 6 is identified by the UI code inserted to a control field 8 and a relay line data 7 is inserted to the information field 10 and then sent. The decomposing device 4 fetches the UI frame 6 in the line speed synchronously with the clock 5 and the relay line data 7 is set to the memory. Through the constitution above, it is not required to register the relay line data directly at the remote decomposing device and the discrepancy of the relay line data is not generated for the communication.
JP20320787A 1987-08-17 1987-08-17 Relay line data control system between packet exchange and packet composing/ decomposing device Pending JPS6447148A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20320787A JPS6447148A (en) 1987-08-17 1987-08-17 Relay line data control system between packet exchange and packet composing/ decomposing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20320787A JPS6447148A (en) 1987-08-17 1987-08-17 Relay line data control system between packet exchange and packet composing/ decomposing device

Publications (1)

Publication Number Publication Date
JPS6447148A true JPS6447148A (en) 1989-02-21

Family

ID=16470239

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20320787A Pending JPS6447148A (en) 1987-08-17 1987-08-17 Relay line data control system between packet exchange and packet composing/ decomposing device

Country Status (1)

Country Link
JP (1) JPS6447148A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5711901A (en) * 1996-06-05 1998-01-27 Walbro Corporation Carburetor having temperature-compensated purge/primer
US6981179B1 (en) 1999-04-23 2005-12-27 Sharp Kabushiki Kaisha Microcomputer having built-in nonvolatile memory and check system thereof and IC card packing microcomputer having built-in nonvolatile memory and check system thereof
US7042243B2 (en) 2003-05-30 2006-05-09 Sharp Kabushiki Kaisha Device test apparatus and test method including control unit(s) between controller and test units
JP2009514088A (en) * 2005-11-01 2009-04-02 サンディスク アイエル リミテッド Method, system, and computer readable code for testing flash memory

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5711901A (en) * 1996-06-05 1998-01-27 Walbro Corporation Carburetor having temperature-compensated purge/primer
US6981179B1 (en) 1999-04-23 2005-12-27 Sharp Kabushiki Kaisha Microcomputer having built-in nonvolatile memory and check system thereof and IC card packing microcomputer having built-in nonvolatile memory and check system thereof
US7042243B2 (en) 2003-05-30 2006-05-09 Sharp Kabushiki Kaisha Device test apparatus and test method including control unit(s) between controller and test units
JP2009514088A (en) * 2005-11-01 2009-04-02 サンディスク アイエル リミテッド Method, system, and computer readable code for testing flash memory

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