KR20080065473A - Multilayer chip capacitor - Google Patents

Abstract

A multilayer chip capacitor is provided to reduce ESL(Equivalent Series Inductance) thereof and prevent ESR(Equivalent Series Resistance) from being excessively lowered, thereby stabilizing power supply to a high frequency circuit when the multilayer chip capacitor is applied as a decoupling capacitor. A mutlilayer chip capacitor(100) includes a capacitor body(101), a plurality of internal electrodes, and external electrodes(131-134). The capacitor body is formed by stacking a plurality of dielectric layers and has a bottom surface(A) serving as a mounting surface. The internal electrodes are opposed to each other with the dielectric layers interposed therebetween in the capacitor. The external electrodes are formed on the bottom surface and are connected to the corresponding internal electrodes. The internal electrodes are disposed perpendicular to the bottom surface. Leads of the internal electrodes having different polarities adjacent to each other in a stacking direction are disposed to be adjacent to each other.

Description

Multilayer Chip Capacitors {MULTILAYER CHIP CAPACITOR}

1A and 1B are perspective views illustrating a stacked chip capacitor according to the prior art.

2 is a perspective view showing the external appearance of a stacked chip capacitor according to an embodiment of the present invention.

3 is a cross-sectional view illustrating an internal electrode disposed in the stacked chip capacitor of FIG. 2.

Fig. 4 is a bottom view showing the arrangement of leads drawn out to the bottom surface of the stacked chip capacitor according to the embodiment (a) and the prior art example (b) of the present invention.

5 is a perspective view showing the external appearance of a stacked chip capacitor according to another embodiment of the present invention.

6 is a cross-sectional view illustrating an internal electrode disposed in the stacked chip capacitor of FIG. 5.

7 are cross-sectional views illustrating internal electrodes disposed in stacked chip capacitors according to another exemplary embodiment of the present disclosure.

8 are cross-sectional views illustrating internal electrodes disposed in stacked chip capacitors according to yet another exemplary embodiment.

FIG. 9 is a graph schematically illustrating an impedance change according to a frequency of the red chip capacitor of FIG. 8.

10 is a schematic diagram schematically showing an example of using a stacked chip capacitor according to an embodiment of the present invention as a decoupling capacitor.

11 are cross-sectional views illustrating internal electrodes disposed in an integrated chip capacitor according to still another embodiment of the present invention.

12 is a perspective view showing an appearance of a stacked chip capacitor according to still another embodiment of the present invention.

<Code Description of Main Parts of Drawing>

100: stacked chip capacitor 101: capacitor body

131 to 134: external electrode 1000: dielectric layer

1010 to 1040: internal electrode 1010a to 1040a: lead

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to stacked chip capacitors, and in particular, internal electrodes are disposed perpendicular to the mounting surface, and have a low equivalent series inductance (ESL) and a suitable equivalent series resistance (ESR). It relates to a chip capacitor.

Stacked chip capacitors are usefully used as decoupling capacitors disposed in high frequency circuits such as power supply circuits of LSIs. The stacked chip capacitors include capacitors in which internal electrodes are disposed perpendicular to the mounting surface, and capacitors arranged horizontally. In order to stabilize the power supply circuit, stacked chip capacitors must have a lower ESL value. These demands are increasing according to the tendency of high frequency and high current of electronic devices. The stability of the power supply circuit depends on the ESL of the stacked chip capacitor, especially at low ESL. The stability of the power supply circuit also depends on the ESR as well as the ESL of the stacked chip capacitors. If the ESR has a value that is too small, the stability of the power supply circuit is weakened and the voltage changes rapidly when resonance occurs. Therefore, it is desirable that the ESR maintain an appropriate value.

In order to reduce ESL, U. S. Patent No. 5,880, 925 proposed a method of arranging the leads of the first inner electrode and the second inner electrode having different polarities in an interdigitated arrangement adjacent to each other. However, according to this US patent, since the resistances generated in the four leads of each internal electrode are connected in parallel with each other, the resistance of the entire capacitor becomes very low. As a result, it is difficult to satisfy the target impedance and causes instability of the power supply circuit.

To prevent the ESR from becoming too low, US Pat. No. 6,441,459 proposes using only one lead for one internal electrode. However, according to this US patent, in the interblock boundary region of the inner electrode patterns, the direction of the current flowing to the adjacent inner electrode becomes the same. Accordingly, there is a problem that the magnetic flux is not canceled and the ESL becomes large between some adjacent internal electrodes.

1A and 1B show examples of conventional stacked chip capacitors having vertically disposed internal electrodes. Referring first to FIG. 1A, the capacitor 10 includes a capacitor body 11 formed by stacking a plurality of dielectric layers 11A and 11B and external electrodes 31 to 34 formed on the mounting surface A of the body 11. (Indicated by a dotted line). FIG. 1A may be considered to be an inverted capacitor so that the mounting surface (lower surface: A) is visible. Inside the main body 11, the internal electrodes 12 and 13 are alternately arranged with the dielectric layers 11A and 11B interposed therebetween. Each internal electrode 12, 13 has two leads 16, 18, 17, 19 connected to the corresponding external electrodes 31, 33, 32, 34.

1B is a perspective view showing another example of a conventional capacitor having internal electrodes in a vertical arrangement. Referring to FIG. 1B, the capacitor 20 includes a capacitor body 21 and external electrodes 3a, 3b, 3c, and 3d formed on upper and lower surfaces thereof. The first and second inner electrodes 22 and 23 having heterogeneous polarities are drawn to the upper and lower surfaces thereof, and are connected to the four leads 1b, 1c, 1d, and 1e, 1b ', 1c', 1d ', and 1e. Has')

According to the capacitor having the vertically arranged inner electrodes of FIGS. 1A and 1B, by arranging leads of heterogeneous polarity adjacently, magnetic fluxes caused by currents flowing through the leads are offset against each other, thereby reducing ESL. However, there is a problem that the ESR is excessively lowered because many leads are connected in parallel. In particular, in the capacitor of FIG. 1B, although the effect of reducing ESL is high, the ESR is excessively reduced, making it difficult to implement a stable high frequency power supply circuit in a decoupling application.

In order to solve the above problems, an object of the present invention is to provide a multilayer chip capacitor having an appropriate ESR while implementing low ESL.

In order to achieve the above object, the stacked chip capacitor of the present invention comprises: a capacitor body formed by laminating a plurality of dielectric layers, the capacitor body having a lower surface as a mounting surface; A plurality of internal electrodes disposed in the capacitor body so as to face each other with a dielectric layer interposed therebetween and each having only one lead drawn out to the bottom surface; And three or more external electrodes formed on the lower surface and connected to the corresponding inner electrodes through the leads, wherein the inner electrodes are disposed perpendicular to the lower surface, and the leads of the inner electrodes having different polarities adjacent in the stacking direction are always in the horizontal direction. Are arranged adjacent to each other.

According to the exemplary embodiment of the present invention, the external electrodes formed on the lower surface are alternately arranged with each other, and the leads drawn out to the lower surface may be arranged in a zigzag shape along the stacking direction.

The capacitor may be a four-terminal capacitor. In this case, six internal electrodes continuously arranged in the stacking direction form one block, and the blocks may be repeatedly stacked.

In the four-terminal capacitor having the block, first to fourth external electrodes may be sequentially disposed on the bottom surface of the capacitor body. Each of the blocks may include first to fourth internal electrodes each having one lead drawn out to the bottom surface, wherein the leads of the first to fourth internal electrodes are respectively connected to the first to fourth external electrodes. The first to fourth internal electrodes may be sequentially stacked in the order of the first, second, third, fourth, third and second internal electrodes in each block. By the lead arrangement, the leads drawn out to the bottom surface are arranged in a zigzag form along the stacking direction.

According to an embodiment of the present invention, the capacitor may further include three or more external electrodes formed on the upper surface. In this case, each of the inner electrodes may further have only one lead drawn to the upper surface and connected to the corresponding outer electrode.

The external electrodes formed on the upper and lower surfaces may be alternately arranged with each other on different surfaces of the upper and lower surfaces, and the leads drawn to the upper and lower surfaces may be arranged in a zigzag form on each of the leading surfaces. In particular, the external electrodes formed on the upper surface and the external electrodes formed on the lower surface are the same number, and the external electrodes of different polarities may be disposed to face each other on the upper and lower surfaces.

The capacitor may be an eight-terminal capacitor. In this case, six internal electrodes continuously arranged in the stacking direction form one block, and the blocks may be repeatedly stacked.

In the eight-terminal capacitor having the block, first to fourth external electrodes may be sequentially disposed on the lower surface of the capacitor body, and fifth to eighth external electrodes may be sequentially disposed on the upper surface. Each of the blocks may include first to fourth internal electrodes each having only one lead drawn out to the bottom surface and only one lead drawn out to the top surface, and the first to fourth drawn out to the bottom surface. Leads of internal electrodes are connected to the first to fourth external electrodes, and the first to fourth internal electrodes may be sequentially stacked in the order of the first, second, third, fourth, third and second internal electrodes in each block. have. By the lead arrangement, the leads drawn out to the bottom surface are arranged in a zigzag form along the stacking direction. In the same manner, the leads drawn to the upper surface may be arranged in a zigzag form along the stacking direction.

When the capacitor has an outer electrode formed on the upper and lower surfaces and a lead connected thereto, the inner electrode of one polarity among the inner electrodes may be divided into an upper electrode plate and a lower electrode plate in the same plane. All internal electrodes may be divided into upper and lower polarizing plates in the same plane. The upper and lower electrode plates divided in the same plane may have the same area. Alternatively, it may have a different area.

According to the embodiment of the present invention, the length of the capacitor body along the stacking direction may be shorter than the distance between two sides parallel to the stacking direction. Alternatively, the length of the capacitor body along the stacking direction may be longer than the distance between two sides parallel to the stacking direction.

In the present specification, the 'lower surface' of the capacitor body refers to a surface mounted on the circuit board when the capacitor is mounted on the circuit board, and the upper surface of the capacitor body refers to a surface opposite to the lower surface. Therefore, if the inner electrode is perpendicular to the lower surface, the inner electrode is disposed perpendicular to the mounting surface. In the present specification, the split slot refers to a slit portion that physically separates the inner electrode layer.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and size of elements in the drawings may be exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings are the same elements.

FIG. 2 is a perspective view illustrating an external shape of a stacked chip capacitor according to an exemplary embodiment of the present disclosure, and FIG. 3 is a cross-sectional view illustrating internal electrodes disposed in the capacitor of FIG. 2. These cross sections correspond to cross sections cut along the plane in which the internal electrodes extend.

2 and 3, the four-terminal capacitor 100 includes a capacitor body 101 formed by stacking a plurality of dielectric layers 1000 and first to fourth surfaces formed on a lower surface (ie, a mounting surface; A) of the body. External electrodes 131 to 134 are included. On the lower surface of the main body, the external electrodes 131 to 134 of different polarities are alternately arranged. In addition, since the lower surface A is parallel to the stacking direction (X direction), the internal electrodes 1010, 1020, 1030 and 1040 are disposed perpendicular to the lower surface A. The lower surface A, the upper surface B, and the first and second side surfaces C and D of the capacitor body 101 are parallel to the stacking direction (X direction).

In particular, each internal electrode 1010, 1020, 1030, 1040 has only one lead drawn out to the bottom surface. In addition, the leads of different polarities adjacent in the stacking direction are always arranged to be adjacent over the entire inner electrode. This reduces the ESL and prevents excessive degradation of the ESR. In FIG. 3, the dashed-dotted line extends in the stacking order.

Specifically, the internal structure of the capacitor will be described. A total of six internal electrodes 1010, 1020, 1030, 1040, 1030, and 1020 stacked in series form one block. This block is repeatedly stacked as a unit of a periodic structure. That is, the lead 1010a of the first internal electrode 1010 is connected to the first external electrode 131, the lead 1020a of the second internal electrode 1020 is connected to the second external electrode 132, The lead 1030a of the third internal electrode 1030 is connected to the third external electrode 133, and the lead 1040a of the fourth internal electrode 1040 is connected to the fourth external electrode 134. Then, the third and second internal electrodes 1030 and 1020 are sequentially arranged again. Accordingly, four electrode patterns (first to fourth internal electrodes) are stacked six times according to the stacking order of the first, second, third, fourth, third, and second internal electrodes, thereby forming one block. The blocks are repeatedly stacked in the stacking direction.

According to the lead arrangement of the internal electrodes as described above, the leads of heterogeneous polarities are always adjacent to each other. Since adjacent leads of different polarities allow currents in opposite directions to flow, the magnetic flux is offset by this and the ESL is reduced. Each internal electrode also has only one lead to suppress excessive reduction in ESR.

Furthermore, as shown in Fig. 4A, since the leads drawn out to the bottom surface are arranged in a zigzag form (see the dotted lines), the distance between adjacent leads connected to the same external electrode becomes relatively large. For example, the distance D between adjacent leads 1010a (in the stacking direction) connected to the external electrode 131 corresponds to six dielectric layer thicknesses. Accordingly, mutual inductance due to magnetic coupling between leads of the same polarity adjacent in the stacking direction (X direction) is reduced. This contributes to ESL reduction.

In contrast, as shown in FIG. 4B, in the case of the conventional capacitor (see FIG. 1A), the distance between adjacent leads (eg, adjacent leads 16) connected to the same external electrode (eg, 31) is determined. Only two dielectric layer thicknesses (d) result in relatively high mutual inductance between leads of the same polarity adjacent in the stacking direction.

5 is a perspective view illustrating an external shape of a stacked chip capacitor according to another exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view illustrating an internal electrode of the capacitor of FIG. 5. Referring to FIG. 5, the capacitor 200 may further include not only external electrodes 231 to 234 formed on the bottom surface A of the capacitor body 201, but four external electrodes 235 to 238 formed on the top surface B. (8-terminal capacitor).

In this embodiment, each of the internal electrodes 2010, 2020, 2030, and 2040 is connected to the lower surface and only one lead drawn to the lower surface in order to connect the inner electrodes to the corresponding outer electrodes 231 to 238 on the lower surface and the upper surface. Only one lead is drawn out. Also in this embodiment, the leads drawn out to the lower surface A are arranged in a zigzag form along the stacking direction (X direction) (see Fig. 4 (a)). In addition, it can be seen from FIG. 6 that the leads drawn to the upper surface B are also arranged in a zigzag form along the stacking direction Y. FIG.

Specifically, the leads 2010a and 2010b of the first internal electrode 2010 are connected to the first external electrode 231 and the eighth external electrode 238, and the leads 2020a and 220 of the second internal electrode 2020. 2020b is connected to the second external electrode 232 and the seventh external electrode 237, and the leads 2030a and 2030b of the third internal electrode 2030 are connected to the third external electrode 233 and the sixth external electrode ( 236 and the leads 2040a and 2040b of the fourth internal electrode 2040 are connected to the fourth external electrode 234 and the fifth external electrode 235. The first to fourth internal electrodes are sequentially arranged in the order of the first, second, third, fourth, third, and second internal electrodes to form one block, and the blocks are repeatedly stacked.

In the embodiments of FIGS. 5 and 6, not only can the ESL be reduced due to the adjacent arrangement characteristics and the zigzag arrangement between the leads of different polarities, but also the excessive reduction of the ESR due to the multiple resistances connected in parallel can be suppressed. .

FIG. 7 is a modification of the internal electrode arrangement structure of FIG. 6, in which the internal electrodes of one polarity (in this case, -polarity which forms a ground potential) are divided up and down. Referring to FIG. 7, instead of the second and fourth internal electrodes 2020 and 2040 of FIG. 6, internal electrodes 2020 ′ and 2040 ′ divided by a split slot parallel to the Y direction are used. As described above, by dividing each of the monopolar internal electrodes 2020 'and 2040' into upper and lower electrode plates 2022, 2021 and 2042 and 2041, two capacitors separated from each other can be connected in parallel. Other internal electrode structures and external structures are the same as in FIG.

FIG. 8 is a variant of FIG. 7, in particular the upper and lower electrode plates 2024, 2023, 2044, 2043 on the same plane of the divided monopolar (here -polar) internal electrodes 2020 '', 2040 ''. Have different areas. Thus, by dividing the internal electrodes on the same plane with different areas, the capacitances of the respective electrode plates can be made different. If the 'separate capacitors' disposed in the same chip structure exhibit different capacitances, as described below, low impedance can be made in a wider frequency range (see FIG. 9). Other internal electrode structures and external structures are the same as in FIG.

FIG. 9 is a diagram illustrating an impedance versus frequency graph of a capacitor having the internal electrode structure of FIG. 8. FIG. The dotted line curve (a) shows the impedance curve of the capacitor by the electrode plate of the large area among the electrode plates of different areas, and the dashed-dotted line curve (b) shows the impedance curve of the capacitor by the electrode plate of the narrow area. The two impedance curves combine to represent the (solid line) impedance curve of FIG. 9, and as shown, the frequency range wf representing the impedance lower than the target impedance Z _T is represented by each component curve (a, b). It is wider than the frequency range below the target impedance at. This means that a stable power circuit can be realized in a wider frequency range.

The embodiment of FIG. 6 provides the advantage of functioning as a feedthrough type capacitor when used as a decoupling capacitor in a power supply circuit of an LSI such as a CPU. That is, as shown in FIG. 9, when the capacitor 100 of FIG. 6 is mounted between the wiring board 53 (for example, a CPU package) on which the CPU 51 is mounted and the motherboard 55, the capacitor 100 of FIG. 6 is used as a decoupling capacitor. In addition, the power supply current i may flow between the power supply terminal 55a of the motherboard 55 and the power connection terminal 53a of the wiring board 53 through the internal electrode. Therefore, in addition to the current i1 from the other power supply terminal 55b or the current i2 to the ground terminal 55c, the current i passing through the internal electrode is additionally provided. As a result, by increasing the number of current paths flowing through the CPU package, power loss of the CPU package released into heat can be reduced.

FIG. 11 is a variation of FIG. 6, in which the positive polarity internal electrodes 2010 'and 2030' are divided into upper and lower electrode plates 2012, 2011, and 2032 and 2031 on the same plane by the split slots. do. Both -polar and + polar internal electrodes may be divided into upper and lower electrode plates on the same plane.

12 is a stacked chip capacitor according to another embodiment of the present invention. The stacked chip capacitor 100 ′ of FIG. 12 is a view except that the length W of the main body along the stacking direction (X direction) is larger than the distance L between two sides parallel to the stacking direction. It is the same as that of 2 embodiment. Even when external electrodes are disposed on the upper and lower surfaces, the length L may be greater than the distance L. In this way, by making the length W larger than the distance L, the number of stacked layers can be increased more stably (increasing the number of stacked layers, the circuit board can be expanded without changing the height of the capacitor). The mounting of the capacitors to is stable). In addition, as the number of stacked layers increases, the ESL becomes lower. This is because, unlike a capacitor having horizontally disposed internal electrodes, current can flow directly from the mounting surface to the leads of the internal electrodes without going through a separate current path regardless of the number of stacked layers.

The present invention is not limited by the above-described embodiment and the accompanying drawings. It is intended that the scope of the invention be defined by the appended claims, and that various forms of substitution, modification, and alteration are possible without departing from the spirit of the invention as set forth in the claims. Will be self-explanatory.

According to the present invention, the ESL of the stacked chip capacitor is reduced, and excessive drop of ESR is prevented. Accordingly, when applied as a decoupling capacitor, it is possible to further stabilize the power supply to the high frequency circuit.

Claims (16)

A capacitor body formed by laminating a plurality of dielectric layers, the capacitor body having a bottom surface as a mounting surface; A plurality of internal electrodes disposed in the capacitor body so as to face each other with a dielectric layer interposed therebetween, each having only one lead drawn to the bottom surface; And 3 or more external electrodes formed on the bottom surface and connected to the corresponding internal electrodes through the leads, The internal electrode is disposed perpendicular to the lower surface, and the stacked chip capacitor, characterized in that the leads of the internal electrodes of different polarities adjacent in the stacking direction are always disposed adjacent to each other in the horizontal direction. The method of claim 1, The external electrodes formed on the lower surface are alternately arranged with each other with different polarities, Leads drawn to the lower surface is stacked chip capacitor, characterized in that arranged in a zigzag form along the stacking direction. The method of claim 2, The capacitor is a four-terminal capacitor, the laminated chip capacitor, characterized in that the six internal electrodes arranged in the stacking direction is formed in one block, the block is repeatedly stacked. The method of claim 3, First to fourth external electrodes are sequentially disposed on the bottom surface of the capacitor body, Each of the blocks includes first to fourth internal electrodes each having one lead drawn out to the bottom surface, Leads of the first to fourth internal electrodes are connected to the first to fourth external electrodes, respectively, and the first to fourth internal electrodes are connected to the first, second, third, four, three, and two internal electrodes in each block. Stacked chip capacitors, characterized in that arranged in succession. The method of claim 1, The capacitor further comprises three or more external electrodes formed on the upper surface, Each of the inner electrodes further has only one lead drawn to the upper surface and connected to the corresponding outer electrode. The method of claim 5, External electrodes formed on the upper and lower surfaces are alternately arranged with each other on different surfaces of the upper and lower surfaces, Leads drawn to the top and bottom surfaces are arranged in a zigzag form on each lead surface. The method of claim 6, The external electrode formed on the upper surface and the external electrode formed on the lower surface is the same number, Stacked chip capacitors, characterized in that the outer electrode of the heterogeneous polarity on the upper and lower surfaces are disposed facing each other. The method of claim 6, The capacitor is an 8-terminal capacitor, the stacked chip capacitor, characterized in that the six internal electrodes arranged in the stacking direction is formed of one block, the block is repeatedly stacked. The method of claim 8, First to fourth external electrodes are sequentially disposed on the lower surface, and fifth to eighth external electrodes are sequentially disposed on the upper surface, Each of the blocks includes first to fourth internal electrodes each having only one lead drawn out to the bottom surface and only one lead drawn out to the top surface, Leads of the first to fourth internal electrodes drawn out to the bottom surface are connected to the first to fourth external electrodes, and the first to fourth internal electrodes are connected to the first, second, third, four, three, and the like in each block. 2. The stacked chip capacitor of claim 2, wherein the multilayer chip capacitor is sequentially stacked in the order of the internal electrodes. The method of claim 9, The internal electrodes are sequentially connected to the fifth, sixth, seventh, eighth, seventh, and sixth external electrodes, and the connection structure between the internal and external electrodes is repeated. The method of claim 5, The monopolar inner electrode of the inner electrode is divided chip capacitor, characterized in that divided into the upper electrode plate and the lower electrode plate in the same plane. The method of claim 11, The stacked chip capacitor of claim 1, wherein the upper and lower electrode plates divided in the same plane have the same area. The method of claim 11, And the upper and lower electrode plates divided in the same plane have different areas. The method of claim 5, Stacked chip capacitors, characterized in that each of the internal electrodes are divided into upper and lower electrode plates in the same plane. The method of claim 1, The length of the capacitor main body along the stacking direction is shorter than the distance between two sides parallel to the stacking direction. The method of claim 1, The length of the capacitor main body along the stacking direction is longer than the distance between the two sides parallel to the stacking direction.

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