KR20080064338A - Liquid crystal display and method of driving the same - Google Patents

Abstract

A liquid crystal display device and a method for driving the same are provided to prevent a malfunction of a back light assembly by driving an inverter assembly in synchronism with a timing signal of the liquid crystal display device. A liquid crystal display device includes a liquid crystal panel(100), a back light assembly(200), a timing controller(310), and a lamp driver(320). The liquid crystal panel displays images. The back light assembly is composed of at least one light source, and provides light to the liquid crystal panel. The timing controller generates and provides a gate signal, a data signal, and an output enable signal to the liquid crystal panel. The lamp driver operates according to the output enable signal to generate a lamp driving signal from an external signal, and drives the back light assembly using the generated lamp driving signal.

Description

Liquid crystal display and method of driving the same {Liquid crystal display and method of driving the same}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal panel of FIG. 1.

3 is a block diagram of the lamp driver of FIG. 1.

4 is an example of a circuit diagram of the controller of FIG. 3.

5 is a driving timing diagram of the liquid crystal display of FIG. 1.

(Explanation of symbols for the main parts of the drawing)

400: liquid crystal display device 100: liquid crystal panel

200: backlight assembly 300: drive assembly

310: timing control unit 320: lamp driving unit

321: DC / DC converter 323: R-C filter

325: control unit 327: drive current feedback unit

The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof that can prevent a malfunction of the backlight assembly.

Liquid crystal display is one of the most widely used flat panel displays. It consists of two substrates on which electrodes are formed and a liquid crystal layer interposed between them. The display device is applied to rearrange the liquid crystal molecules of the liquid crystal layer to control the amount of light transmitted.

The liquid crystal display device supplies power to a backlight assembly including a liquid crystal panel for displaying an image and a plurality of fluorescent lamps providing light to the liquid crystal panel, and an upper / lower storage container and a backlight assembly for housing the liquid crystal panel and the backlight assembly. The inverter assembly is supplied.

Recently, a light emitting diode (LED) is used as a light source of a backlight assembly. The backlight assembly using the light emitting diode may use a lower level driving voltage than the backlight assembly using the fluorescent lamp. This can simplify the circuit of the inverter assembly and can also be embedded in a printed circuit board connected to the liquid crystal panel. The inverter assembly generates a lamp driving voltage capable of driving a predetermined driving voltage, for example, a light emitting diode, from a signal provided from the outside, and may drive the backlight assembly using the lamp driving voltage.

In this case, the inverter assembly may operate independently of another unit of the printed circuit board, for example, a timing controller and the like, and thus the backlight assembly may malfunction. In detail, in the case of poor output due to the initial driving of the liquid crystal display or noise, the liquid crystal panel may not perform a normal operation, but the backlight assembly may be normally driven. Accordingly, a screen defect, for example, a whitening phenomenon, may occur in the liquid crystal display.

An object of the present invention is to provide a liquid crystal display device which can prevent the malfunction of the backlight assembly.

Another object of the present invention is to provide a method of driving such a liquid crystal display.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a liquid crystal panel for displaying an image; a backlight assembly configured to provide light to the liquid crystal panel; A timing control unit for generating a data signal and an output enable signal OE and providing the same to the liquid crystal panel; an operation of the output enable signal; and generating a lamp driving signal from a predetermined signal provided from the outside. It includes a lamp driving unit for driving the backlight assembly using.

According to another aspect of the present invention, there is provided a driving method of a liquid crystal display device comprising: a liquid crystal panel configured to display an image; and a backlight assembly configured to provide light to the liquid crystal panel; A timing control unit for generating and providing a gate signal, a data signal, and an output enable signal OE to the liquid crystal panel, and an output enable signal, and generating a lamp driving signal from a predetermined signal provided from the outside. Preparing a liquid crystal display including a lamp driver for driving the backlight assembly by using the lamp driving signal, providing an output enable signal to the lamp driver, and whether the output enable signal is normal or abnormal Generating a control signal by using the control signal, and operating the lamp driver by using the control signal. And a step of controlling.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only the embodiments make the disclosure of the present invention complete, and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal panel of FIG. 1.

First, referring to FIG. 1, a liquid crystal display device 400 according to an exemplary embodiment may include a liquid crystal panel 100, a backlight assembly 200, and a driving assembly 300. Although not shown in the drawings, the driving assembly 300 may be formed on a printed circuit board (not shown) disposed on one side of the liquid crystal panel 100.

The liquid crystal panel 100 may include a plurality of display signal lines G1 to Gn and D1 to Dm, connected thereto, and a plurality of unit pixels arranged in a matrix form. Can be. The display signal lines G1 to Gn and D1 to Dm include a plurality of gate lines G1 to Gn for transmitting gate signals and a plurality of data lines D1 to Dm for transmitting data signals. Here, the gate lines G1 to Gn extend in the row direction and are substantially parallel to each other, and the data lines D1 to Dm extend in the column direction and are substantially parallel to each other.

Each unit pixel includes a switching element Q connected to the display signal lines G1 to Gn and D1 to Dm, a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. The sustain capacitor Cst may be omitted as necessary.

Referring to FIG. 2, the switching element Q has two terminals, a pixel electrode PE of the first display panel 111 and a common electrode CE of the second display panel 113, and two electrodes PE and CE. The liquid crystal layer (not shown) interposed therebetween functions as a dielectric. The pixel electrode PE is connected to the switching element Q, and the common electrode CE is formed on the entire surface of the second display panel 113, and receives the common voltage Vcom. In addition, the common electrode CE may be provided in the first display panel 111. In this case, both electrodes PE and CE may be formed in a linear or bar shape.

The storage capacitor Cst is formed by overlapping a separate signal line (not shown) and the pixel electrode PE provided on the first display panel 111. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. (Independent wiring system). In addition, the storage capacitor Cst may be formed such that the pixel electrode PE overlaps the front-end gate line directly above the insulator (shear gate method).

Meanwhile, in order to implement color display, each unit pixel should display a color, which is possible by providing a red, green, or blue color filter CF in a region corresponding to the pixel electrode PE. The color filter CF may be formed in a corresponding region of the second display panel 113 and may be formed above or below the pixel electrode PE of the first display panel 111.

A polarizer (not shown) for polarizing light may be attached to an outer surface of at least one of the first display panel 111 and the second display panel 113 of the liquid crystal panel 100.

Referring back to FIG. 1, the liquid crystal panel 100 may receive light from the backlight assembly 200 to display an image. Here, the backlight assembly 200 may include at least one light source for emitting light, for example, a light source composed of a plurality of light emitting diodes (LEDs). The backlight assembly 200 may be disposed under the liquid crystal panel 100. In addition, the backlight assembly 200 may be operated by the driving assembly 300 described below, for example, the lamp driver 320. The operation of the backlight assembly 200 will be described later in detail.

On the printed circuit board disposed on one side of the liquid crystal panel 100, a driving assembly 300 for providing driving and control signals to the liquid crystal panel 100 may be formed. The driving assembly 300 may include a timing controller 310, a lamp driver 320, a driving voltage generator 330, a gate driver 340, a data driver 350, and a gamma voltage generator 355. Can be.

The timing controller 310 may generate a control signal for controlling operations of the gate driver 340, the data driver 350, and the lamp driver 320. The timing controller 310 may generate a control signal corresponding to each of the control signals. The driving unit 350 and the lamp driving unit 320 may be provided.

The lamp driver 320 receives a predetermined voltage provided from the outside, for example, the driving voltage BLU_VDD, and generates a lamp driving signal L_S by appropriately processing the lamp driver 320. The lamp driving signal L_S generated as described above may be provided as a driving voltage of the backlight assembly 200. Herein, the operation of the lamp driver 320 may be controlled by a predetermined control signal provided from the timing controller 310, for example, an output enable (OE) signal. The lamp driver 320 will be described in detail later with reference to FIGS. 3 to 5.

The driving voltage generator 330 may generate a plurality of driving voltages and provide them to the gate driver 340 and the liquid crystal panel 100. The driving voltage generated by the driving voltage generator 330 may include, for example, a gate on voltage Von, a gate off voltage Voff, a common voltage Vcom, and the like.

The gate driver 340 is connected to the gate lines G1 to Gn formed in the liquid crystal panel 100, and is a combination of the gate-on voltage Von and the gate-off voltage Voff provided from the driving voltage generator 330. The gate driving signal may be provided to the gate lines G1 to Gn.

The data driver 350 is connected to the data lines D1 to Dm formed in the liquid crystal panel 100, and generates and generates a plurality of gray voltages based on the plurality of gamma voltages provided from the gamma voltage generator 355. The selected gray voltage is selected and applied to the unit pixel as a data driving signal, and may be formed of a plurality of integrated circuits.

The gate driver 340 and the data driver 350 may be mounted on the liquid crystal panel 100 in the form of a plurality of driving integrated circuit chips, or may be mounted on a flexible printed circuit film (FPC). The tape may be attached to the liquid crystal panel 100 in the form of a tape carrier package (TCP). In addition, the gate driver 340 and / or the data driver 350 may be integrated with the liquid crystal panel 100 together with the display signal lines G1 to Gn and D1 to Dm and the switching element Q.

The gamma voltage generator 355 may generate two sets of gamma voltages related to transmittance of the unit pixel. That is, one of the two sets is the positive voltage, and the other is the negative voltage. Herein, the positive voltage and the negative voltage mean voltages having opposite polarities with respect to the common voltage Vcom, and may be alternately provided to the liquid crystal panel 100 during inversion driving.

As described above, the driving assembly 300 receives the driving and control signals from the outside and processes them appropriately to provide the driving and control signals of the liquid crystal panel 100. Hereinafter, the operation of the driving assembly 300 will be described in more detail.

The timing controller 310 is an input control signal for controlling the R, G, and B image signals R, G, and B and their display from an external, for example, external graphic controller (not shown), for example, a vertical synchronization signal. Signals such as Vsync, horizontal sync signal Hsync, main clock MCLK, and data enable signal DE may be provided.

Accordingly, the timing controller 310 generates a gate control signal CONT1 and a data control signal CONT2 based on the input signals, and applies the image signals R, G, and B to operating conditions of the liquid crystal panel 100. Treat it properly. In addition, the gate control signal CONT1 generated by the timing controller 310 is provided to the gate driver 340, and the data control signal CONT2 and the image data signals R ', G', and B 'are the data driver 350. ) May be provided.

Here, the gate control signal CONT1 generated from the timing controller 310 is a vertical synchronization signal STV indicating the start of output of the gate on pulse (gate on voltage section), and a gate clock signal for controlling the output timing of the gate on pulse. And an output enable signal OE defining a width of the CPV and the gate-on pulse.

In addition, the data control signal CONT2 may be configured to apply a horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B ', and a data driving signal corresponding to the data lines D1 to Dm. The data signal may include a load signal LOAD, an inversion driving signal RVS for inverting the polarity of the data driving signal with respect to the common voltage Vcom, a data clock signal HCLK, and the like.

The data driver 350 sequentially receives image data R ', G', and B 'corresponding to one row of unit pixels according to the data control signal CONT2 provided from the timing controller 310, and among the gray voltages. The image data R ', G', B 'is converted into the corresponding data driving signal by selecting the gray scale voltage corresponding to each of the image data R', G ', and B'.

The gate driver 340 is connected to the gate lines G1 to Gn by applying the gate-on voltage Von to the gate lines G1 to Gn according to the gate control signal CONT1 provided from the timing controller 310. Turn on (Q).

Here, while a gate-on voltage Von is applied to one gate line G1 to Gn, and a row of switching elements Q connected thereto is turned on (this period is '1H' or '1 horizontal period'). Is equal to one period of the horizontal synchronizing signal STH, the data enable signal DE, and the gate clock signal CPV], and the data driver 400 associates each data driving signal with a corresponding data line D1. Supply to ~ Dm). The data driving signal thus supplied is applied to the corresponding unit pixel through the turned-on switching element Q.

In addition, the liquid crystal molecules constituting the liquid crystal layer interposed between the first and second display panels change their arrangement according to the change in the electric field generated by the pixel electrode PE and the common electrode CE, thereby passing through the liquid crystal layer. The polarization of light changes. This change in polarization is represented by a change in light transmittance by polarizers (not shown) attached to the first and second display panels.

In this manner, the gate-on voltages Von are sequentially applied to all the gate lines G1 to Gn during one frame to apply data driving signals to all unit pixels. When one frame ends, the next frame starts, and the inversion driving signal RVS applied to the data driving unit 400 is applied so that the polarity of the data driving signal applied to each unit pixel is opposite to that of the data driving signal in the previous frame. The state is controlled ('frame inversion'). In this case, the polarity of the data driving signal flowing through one data line D1 to Dm is changed ('line inversion') in one frame according to the characteristics of the inversion driving signal RVS, or the data driving signal applied to one pixel row. The polarities of can also be different ('dot reversal').

The lamp driver 320 generates the lamp driving signal L_S from a predetermined voltage BLU_VDD provided from the outside. The lamp driving signal L_S is provided to the backlight assembly 200 and may operate with the driving voltage of the backlight assembly 200. The ramp driving signal L_S may be controlled by a predetermined control signal signal provided from the timing controller 310, for example, the output enable signal OE.

In detail, the lamp driver 320 receives an output enable signal OE from the timing controller 310. The output enable signal OE may be a control signal for controlling the output timing of the gate driving signal provided from the timing controller 310 to the gate driver 340. Subsequently, the operation of the lamp driver 320 may be controlled according to the provided output enable signal OE. In other words, if the output enable signal OE provided to the lamp driver 320 is a normal signal, the lamp driver 320 may operate to generate a lamp drive signal L_S, and such a lamp drive signal L_S. May be provided as a driving signal to the backlight assembly 200. In addition, if the output enable signal OE provided to the lamp driver 320 is an abnormal signal, the lamp driver 320 does not operate and does not generate the lamp driving signal L_S. Accordingly, the backlight assembly 200 does not operate.

Hereinafter, the lamp driving unit described above will be described in more detail with reference to FIGS. 3 and 4.

3 is a block diagram of the lamp driver of FIG. 1, and FIG. 4 is an example of a circuit diagram of the controller of FIG. 3.

First, referring to FIG. 3, the lamp driver 320 may largely include a DC / DC converter 321, a controller 325, and a driving current feedback unit 327.

The DC / DC converter 321 generates a lamp driving signal L_S from a predetermined voltage BLU_VDD provided from the outside. The lamp driving signal L_S generated from the DC / DC converter 321 may be, for example, a lamp driving voltage having a magnitude of about 19 to 25V. The magnitude of the voltage BLU_VDD provided to the DC / DC converter 321 may be approximately 10 to 12V.

In addition, the DC / DC converter 321 may include a control terminal for controlling the operation, for example, shutdown of the operation of the DC / DC converter 321, and a lamp driving signal provided to the backlight assembly 200. L_S) may include a feedback terminal receiving feedback. The control terminal and the feedback terminal are electrically connected to the control unit 325 and the driving current feedback unit 327 which will be described later, and the operation thereof may be controlled by them.

The controller 325 may generate a control signal C_V for controlling the operation of the DC / DC converter 321. In more detail, the control unit 325 controls the operation of the DC / DC converter 321 by using a predetermined signal provided from an external, for example, timing control unit 310, that is, an output enable signal OE. C_V) can be generated. The control signal C_V may be provided to the control terminal of the DC / DC converter 321, and the DC / DC converter 321 may be shut down by the control signal C_V.

Hereinafter, an operation of the DC / DC converter 321 according to the operation of the controller 325 will be described in detail with reference to FIGS. 3 and 4.

3 and 4, the controller 325 may further include an RC filter 323 connected in parallel from a signal input terminal, for example, an input terminal of the output enable signal OE provided from the timing controller 310. have. The R-C filter 323 may serve to block and / or pass an input output enable signal OE.

First, the timing controller 310 generates an output enable signal OE from signals provided from the outside, and provides the generated output enable signal OE to an input terminal of the controller 325. As described above, the controller 325 may include an R-C filter 323.

In this case, when the normal output enable signal OE, for example, a signal having a predetermined frequency value is provided to the input terminal of the controller 325, for example, the output enable signal OE of a square wave pulse of 48 kHz, the controller 325. RC filter 323 blocks it. Accordingly, the switching element Q1 of the controller 325 is turned off, and accordingly, the controller 325 may generate and output a predetermined control signal C_V. In other words, the control signal C_V generated from the controller 325 may be represented as a value obtained by passing the controller driving voltage Vcc provided to the controller 325 through the second resistor R2. In addition, the generated control signal C_V is input to the control terminal of the DC / DC converter 321 to drive the DC / DC converter 321, the DC / DC converter 321 is a voltage (BLU_VDD) provided from the outside The ramp drive signal L_S can be generated from

Next, an output enable signal OE having an abnormal output enable signal OE at the input terminal of the controller 325, for example, a continuous high value on the time t axis, and substantially represented as a direct current value. If is provided, the RC filter 323 of the control unit 325 passes it. Therefore, the switching element Q1 of the controller 325 is turned on, so that the controller 325 does not generate the control signal C_V. In other words, as the switching element Q1 is turned on, the control unit driving voltage Vcc provided to the control unit 325 may be provided to the switching element Q1 via the second resistor R2. Therefore, the output terminal of the controller 325 substantially outputs a value of 0, and thus a signal having a value of 0 may be input to the control terminal of the DC / DC converter 321. In addition, the operation of the DC / DC converter 321 is shut down by a signal provided from the controller 325, that is, a signal of 0, so that the DC / DC converter 321 cannot generate the lamp driving signal L_S. Therefore, the backlight assembly 200 does not operate.

Here, the diode D1, which is illustrated in the drawing but not described, prevents a voltage or current from flowing backward to the input terminal of the controller 325, and the capacitor C2 removes an AC value of the signal generated from the switching element Q1. Can operate as a smoothing device. In addition, the R-C filter 323 used in the above embodiment may be, for example, a low-pass filter for passing low frequencies.

Referring to FIG. 3 again, the lamp driver 320 may further include a driving current feedback unit 327. The driving current feedback unit 327 receives the current after the lamp driving signal L_S generated from the DC / DC converter 321 passes through the backlight assembly 200, and receives the feedback current L_S 'from the initial current. That is, it compares the initial current of the lamp driving signal L_S generated by the DC / DC converter 321. The feedback current can then be adjusted to substantially the same magnitude as the initial current. That is, the driving current feedback unit 327 receives the lamp driving signal L_S 'passed through the backlight assembly 200 and is substantially the same size as the lamp driving signal L_S generated by the DC / DC converter 321. It can be calibrated to have.

Hereinafter, timing of a plurality of signals of the liquid crystal display including the lamp driver 320 described above will be described with reference to FIG. 5.

5 is a driving timing diagram of the liquid crystal display of FIG. 1.

1, 3, and 5, first, the lamp driving signal L_S generated from the lamp driver 320 has a value of 0 from time t0 to t3, and the output enable signal OE at time t3. The signal may be controlled to appear as a signal having a predetermined voltage, for example, to drive the backlight assembly 200.

In detail, the driving assembly 300 of the liquid crystal display device 400 may operate by a predetermined driving voltage Vcc from the outside, for example, a driving voltage Vcc provided to a predetermined size at a time t0. The driving voltage Vcc may correspond to each component of the driving assembly 300, for example, the timing controller 310, the lamp driver 320, the driving voltage generator 330, the gate driver 340, and the data driver 350. ) May be a driving voltage.

Subsequently, the output enable signal OE may appear as a high value at a time substantially equal to the time when the driving voltage Vcc is provided, that is, from time t0 to t2. This may prevent the gate driver 340 and the lamp driver 320 from operating before the timing controller 310 operates normally. That is, the time period t0 to t2 may be a time for preparing to drive the timing controller 310 and the respective driving units, for example, the gate driver 340 and the lamp driver 320.

Subsequently, at time t1, the gate driver 340 may be operated by an initial driving signal of the gate driver 340, that is, a driving voltage Vcc provided from the outside to output the gate-on voltage Von and the gate-off voltage Voff. have. Here, the gate off signal Voff may be maintained from time t1 to t2. In addition, the initial driving signal of the gate driver 340 may be controlled so as not to be output to the liquid crystal panel 100 by the output enable signal OE, that is, the output enable signal OE having a high value.

Subsequently, at time t3, the output enable signal OE in the form of a pulse having a predetermined frequency, that is, a normal frequency, may be output from the timing controller 310. Accordingly, the gate driver 340 and the lamp driver 320 may operate. That is, the normal output enable signal OE may be output from the timing controller 310 and input to the gate driver 340 and the lamp driver 320. Accordingly, the gate driver 340 may provide the gate-on voltage Von to the liquid crystal panel 100, and turn on a plurality of switching elements, for example, thin film transistors. In addition, the lamp driver 320 operates by the output enable signal OE, generates the lamp driving signal L_S from a predetermined voltage provided from the outside, and generates the generated lamp driving signal L_S by the backlight assembly 200. ) Can be output as a drive signal.

That is, by substantially synchronizing the operation of the lamp driver 320 to the output enable signal OE, the initial driving of the liquid crystal display 400, that is, the normal output enable signal OE is output from the timing controller 310. Driving failure of the backlight assembly 200, which may occur before the time point at which the liquid crystal display device 400 is operated, may be prevented.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the liquid crystal display device and the driving method thereof, the inverter assembly is driven in synchronization with the timing signal of the liquid crystal display device, thereby preventing malfunction of the backlight assembly that may occur at the initial stage of driving the liquid crystal display device. can do.

Claims (12)

A liquid crystal panel displaying an image; A backlight assembly comprising at least one light source and providing light to the liquid crystal panel; A timing controller configured to generate a gate signal, a data signal, and an output enable signal OE and provide the same to the liquid crystal panel; And And a lamp driving unit operated by the output enable signal, generating a lamp driving signal from a predetermined signal provided from the outside, and driving the backlight assembly using the generated lamp driving signal. The method of claim 1, wherein the lamp drive unit, A DC / DC converter for generating the lamp driving signal having a predetermined size by using the signal provided from the outside; And And a controller configured to generate a control signal according to the operation of the output enable signal and to feed back the control signal to the DC / DC converter to control the operation of the DC / DC converter. The method of claim 2, wherein the control unit, When the output enable signal is operating normally, the control signal is generated to drive the DC / DC converter, And the control signal is not generated when the output enable signal is abnormally operated. The method of claim 3, wherein And the control signal is a drive control signal for driving the DC / DC converter. The method of claim 2, The controller further comprises an R-C filter. The method of claim 2, wherein the lamp driver further comprises a drive current feedback, The driving current feedback unit receives the lamp driving signal passing through the light source and compares the lamp driving signal generated from the DC / DC converter, and the lamp driving signal passing through the light source is from the DC / DC converter. And a liquid crystal display for correcting substantially the same as the generated lamp driving signal. According to claim 1, A printed circuit board disposed on one side of the liquid crystal panel to generate driving and control signals of the liquid crystal panel; And the timing controller and the lamp driver are mounted on the printed circuit board, respectively. According to claim 1, The light source is a light emitting diode (LED). A liquid crystal panel configured to display an image, a backlight assembly configured to provide light to the liquid crystal panel, and to generate and provide a gate signal, a data signal, and an output enable signal (OE) to the liquid crystal panel. A liquid crystal including a timing controller and a lamp driver operated by the output enable signal, generating a lamp driving signal from a predetermined signal provided from the outside, and driving the backlight assembly using the generated lamp driving signal Preparing a display device; Providing the output enable signal to the lamp driver; Generating a control signal by determining whether the output enable signal is normal or abnormal; And And controlling the operation of the lamp driver by using the control signal. The method of claim 9, The lamp driving unit may generate a control signal according to an operation of the output enable signal and a DC / DC converter for generating the lamp driving signal having a predetermined size using the signal provided from the outside, and the control signal. A control unit for controlling an operation of the DC / DC converter by feeding back to the DC / DC converter, And the controller generates the control signal to drive the DC / DC converter when the output enable signal is normally operated, and does not generate the control signal when the output enable signal is abnormally operated. The method of claim 10, And the control signal is a drive control signal for driving the DC / DC converter. The method of claim 10, wherein the lamp driver further comprises a drive current feedback, The driving current feedback unit receives the lamp driving signal passing through the light source and compares the lamp driving signal generated from the DC / DC converter, and the lamp driving signal passing through the light source is from the DC / DC converter. And a method of correcting the generated lamp driving signal to be substantially the same.

Images