KR20080062734A - Method for fabricating capacitor in semiconductor device - Google Patents

Abstract

A method for fabricating a capacitor in a semiconductor device is provided to improve the properties of the device by preventing lifting defect for dropping an etching stopper. A method for fabricating a capacitor in a semiconductor device comprises the steps of: forming an interlayer dielectric film(202) on a semiconductor substrate(200); forming a hard mask layer pattern for selectively exposing the interlayer dielectric film; forming a contact hole(225) by etching the interlayer dielectric film with the hard mask layer pattern as a mask; forming a contact plug(214) for embedding the contact hole; fabricating a TEOS(Tetraethyl Ortho Silicate) oxidation layer(216) on the contact plug and the interlayer dielectric layer; fabricating an etching stopper on the TEOS oxidation layer; and fabricating a storage node electrode(222), a dielectric film(224), and a plate electrode(226) on the etching stopper.

Description

Method for fabricating capacitor in semiconductor device

1 and 2 are SEM (SEM) photographs shown to explain a phenomenon in which the etch stop film is lifted in the capacitor according to the prior art.

3 to 8 are diagrams illustrating the formation of a capacitor of a semiconductor device according to an embodiment of the present invention.

10A to 10D illustrate a defect map of a wafer when a capacitor is formed in a semiconductor device according to the present invention.

11a and 11b show images of defects occurring in the wafer.

The present invention relates to a semiconductor device, and more particularly, to a method of forming a capacitor of a semiconductor device capable of suppressing a lifting defect of an etch stop film.

Recently, as semiconductor devices have been highly integrated, one of the issues in the process of developing devices of 100 nm or less is a lifting defect in which an etch stop film falls during the formation of a capacitor. Lifting defects do not occur in the cell region but mainly occur in the peripheral region.

1 and 2 are SEM (SEM) photographs shown to explain a phenomenon in which the etch stop film is lifted in the capacitor according to the prior art.

Referring to FIGS. 1 and 2, it can be seen that a lifting defect A, in which the etch stop layer falls at the interface of the lower interlayer dielectric (ILD), occurs. When such a lifting stop film A falls in which the etch stop film falls, when depositing a titanium nitride (TiN) film based on carbon tetrachloride (TiCl ₄ ) used as a barrier metal film in the process of forming a metal wiring after forming a capacitor Titanium nitride (TiN) films are deposited through cracks caused by lifting defects, which may cause bridge defects.

As a cause of such lift defects, a hard mask film and an etch stop film forming method used in an etching process for forming a contact plug connected to a storage node electrode may be a main cause.

In the process of forming the contact hole by etching the interlayer insulating film to form the contact plug, a silicon rich oxy-nitride (hereinafter referred to as SRON) containing a large amount of silicon is used as an etching mask film. In the thermal process that proceeds while forming the SRON film, excessive silicon (Si) from the SRON film changes the interlayer insulating film adjacent to the SRON film into an oxide film containing a large amount of silicon while having low strength. Thereafter, when the etch stop film is formed on the oxide film having such a low strength, a lifting defect may occur while the etch stop film falls while the adhesion between the interlayer insulating film and the adhesion decreases due to the stress caused by the high tension of the nitride film grown in the furnace at a low pressure. . When such a lifting defect occurs, it may affect subsequent processes, such as bridging defects, thereby degrading the characteristics of the device.

An object of the present invention is to provide a method for forming a capacitor of a semiconductor device that can improve the characteristics of the device by suppressing the lifting defect falling off the etch stop film.

In order to achieve the above technical problem, a method of forming a capacitor of a semiconductor device according to the present invention, forming an interlayer insulating film on a semiconductor substrate; Forming a hard mask film pattern to selectively expose the interlayer insulating film; Forming a contact hole by etching the interlayer insulating layer using the hard mask pattern as a mask; Forming a contact plug to fill the contact hole; Forming a TEOS oxide layer on the contact plug and the interlayer dielectric layer; Forming an etch stop layer on the TEOS oxide layer; And forming a storage node electrode, a dielectric layer, and a plate electrode on the etch stop layer.

In the present invention, it is preferable that the hard mask film pattern uses an oxynitride film (SRON) containing a large amount of silicon.

The TEOS oxide film may be formed to a thickness of 400-500 kPa, and preferably not to exceed the thickness of 500 kPa.

Forming the TEOS oxide film is supplied with a nitrogen (N ₂ ) gas at a flow rate of 1000-2000sccm at a process temperature of 350-450 ° C. and a pressure of 2.0-2.5 Torr, and nitrous oxide (N ₂ O) Gas may be supplied at a flow rate of 9500-15000 sccm, and silane (SiH ₄ ) gas may be supplied at a flow rate of 150-250 sccm.

The etch stop layer may be formed using a plasma enhanced chemical vapor deposition (PECVD) method.

The etching stop layer may be formed by applying a power of 450-500 W while supplying a silane (SiH ₄ ) gas, an ammonium (NH ₃ ) gas, and a nitrogen (N ₂ ) gas.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

3 to 8 are diagrams illustrating the formation of a capacitor of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3, an interlayer insulating film 202 is formed on a semiconductor substrate 200 on which substructures (not shown) such as transistors and bit lines are formed. Subsequently, a hard mask film 204 is deposited over the interlayer insulating film 202. The hard mask layer 204 then serves as an etching mask in an etching process for forming a contact plug. The hard mask layer 204 may be formed of a silicon rich oxy-nitride (hereinafter referred to as SRON) film containing a large amount of silicon. In this case, the hard mask layer 204 may be formed using a plasma enhanced chemical vapor deposition (PECVD) method. In addition, the interlayer insulating film 202 may be formed of a high density plasma oxide film (HDP).

Meanwhile, in the process of forming the SRON film, excessive silicon (Si) from the SRON film affects the interface between the SRON film and the interlayer insulating film 202 adjacent to the SRON film, and the strength is increased at the interface between the interlayer insulating film 202 and the hard mask film 204. An oxide film 206 that is weak and contains a large amount of silicon is formed. Next, a photoresist film is applied and patterned on the hard mask film 204 to form a photoresist pattern 208 that exposes a predetermined region of the hard mask film 204.

Referring to FIG. 4, the hard mask layer 204 is etched using the photoresist layer pattern 208 as a mask to form a hard mask layer pattern 210 exposing a predetermined region of the oxide layer 206. The exposed region of the oxide film 206 is a region where a contact plug will be formed later. Next, the photoresist pattern 208 is removed by performing a strip process.

Referring to FIG. 5, a contact hole 212 is formed by etching the exposed regions of the oxide layer 206 and the interlayer insulating layer 202 using the hard mask layer pattern 210 as an etch mask.

Referring to FIG. 6, a conductive film is deposited on the semiconductor substrate 200 to fill a contact hole with a conductive material. Subsequently, a planarization process is performed on the semiconductor substrate 200 to form a contact plug 214 connected to the underlying structure and the capacitor to be formed later. The contact plug 214 may be formed of a conductive material, for example, a polysilicon film. In this case, the planarization process may be performed by using an etch-back or chemical mechanical polishing (CMP) method. As a result of the planarization process, the hard mask layer pattern 210 is removed.

Referring to FIG. 7, a TEOS oxide film (TEOS; Tetra ethyl ortho silicate) 216 is formed on the interlayer insulating film 202 on which the contact plug 214 and the oxide film 206 are formed. The TEOS oxide layer 216 serves as a buffer layer to alleviate stress between the TEOS oxide layer 206 formed at the interface of the interlayer insulating layer 202 that has been in contact with the SRON layer and the etch stop layer to be formed later. Accordingly, the lifting phenomenon in which the etch stop film falls may be suppressed.

The TEOS oxide film 216 supplies nitrogen (N ₂ ) gas at a flow rate of 1000-2000 sccm at a process temperature of 350-450 ° C. and a pressure of 2.0-2.5 Torr, and nitrous oxide (N ₂ O) gas at 9500-15000 sccm The silane (SiH ₄ ) gas may be formed by using a plasma enhanced chemical vapor deposition (PECVD) method while supplying a flow rate of 150-250 sccm. In addition, it can be formed by applying a suitable power, for example RF power of 1000-1200W. The TEOS oxide film 216 may be deposited to a thickness of 400-500 kV. At this time, the TEOS oxide film 216 is preferably deposited so as not to exceed the thickness of 500 kPa.

Referring to FIG. 8, an etch stop layer 218 is formed on the TEOS oxide layer 216. The etch stop layer 218 prevents the etch of the interlayer insulating layer 202 and the contact plug 214 from being excessively etched during the etching process to form the contact hole for the storage node. The etch stop layer 218 is preferably formed using a PECVD method. In this case, the etch stop layer 218 may be formed of a nitride layer by applying a power of 450-500 W while supplying a silane (SiH ₄ ) gas, an ammonium (NH ₃ ) gas, and a nitrogen (N ₂ ) gas. The etch stop film 218 formed using this PECVD method has a high compressive force, for example, -8E9 dyne / cm 2. By the change of the stress mode, it is possible to prevent the lifting defects resulting from the high tension compared to the nitride film formed under the conventional low pressure conditions as the etch stop film.

Referring to FIG. 9, a capacitor 228 is formed on a semiconductor substrate 200.

In detail, the sacrificial insulating layer 220 is deposited on the etch stop layer 218 at a height sufficient to form a capacitor. Subsequently, the sacrificial insulating layer 220 is etched to form the storage node contact hole 225 in the sacrificial insulating layer 220. Next, the storage node electrode 222 is formed in the storage node contact hole 225, and the dielectric film 224 and the plate electrode 226 are sequentially formed on the storage node electrode 222 to form the capacitor 228. do.

By applying the TEOS oxide film and the etch stop film formed by changing the stress mode, a weak oxide film is formed on the interface by the SRON film, thereby suppressing the lifting defect (A, FIG. 1) in which the etch stop film falls during the semiconductor device manufacturing process. Can be. This will be described with reference to the drawings shown by examining defects generated on the wafer.

10A to 10D illustrate a defect map of a wafer when a capacitor is formed in a semiconductor device according to the present invention. Here, the number of dishes ea represents the number of defects generated on the wafer. And 11a and 11b show images of defects occurring in the wafer.

Referring to FIG. 10A, it can be seen that the defect 300 appears over the entire wafer region as a defect map of the wafer on which the capacitor is formed without using the buffer film including the TEOS oxide film. 10B to 10D illustrate a defect map of a wafer on which a capacitor is formed by applying a buffer film and an etch stop film. Compared with FIG. 10A, the number of defects is significantly reduced when the buffer film is applied. Also, referring to FIGS. 10B and 10C, the number of defects found on the wafer of FIG. 10B in which a nitride film is formed by using an undoped silicate glass (USG) oxide film as a buffer film and a PECVD method as an etch stop film is shown. It can be seen that a smaller number of defects found on the wafer of FIG. 10C formed by using the TEOS oxide film as the buffer film and omitting the etch stop film.

10D is a view showing the number of defects in a wafer formed using a TEOS oxide film as a buffer film and an etch stop film using a PECVD method according to an embodiment of the present invention. Comparing the number of defects of FIGS. 10A to 10C with FIG. 10D, it can be seen that the number of defects is significantly reduced when the etch stop layer is formed by applying the TEOS oxide film and the PECVD method. In addition, it can be seen that the PETEOS oxide film of TEOS atmosphere is more effective than the USG oxide film of silane (SiH ₄ ) atmosphere as the buffer film. Such a defect can be confirmed with reference to the image in which the defect B of FIG. 11A occurs and FIG. 11B in which the defect does not occur.

Meanwhile, referring to FIG. 10D, it can be seen that as the thickness of the buffer film increases, the number of defects decreases. When the buffer film is formed to a thickness of 100 ms, the number of defects is found to be twelve, whereas the number of defects is reduced when the thickness is 300 ms, and no defects are found when the buffer film is formed to a thickness of 500 ms. On the other hand, since the etching stop occurs when the thickness of the buffer film is set to 500 kPa or more, the buffer film is preferably formed so as not to exceed the thickness of 500 kPa.

In the method for forming a capacitor of a semiconductor device according to the present invention, a lifting defect in which the etch stop film falls by forming a TEOS oxide film between the contact plug and the etch stop film using a plasma method can be suppressed. In addition, the etching stop film is formed by using a PECVD method to form a nitride film having a high extrusion force to change the stress mode to prevent the lifting defect.

As described above, according to the method of forming a capacitor of a semiconductor device according to the present invention, a nitride defect having a high extrusion force is formed by using a TEOS oxide film and a PECVD method in the formation of a capacitor, thereby preventing a lifting defect in which the etch stop film falls. can do. Thereby, the characteristic of an element can be improved.

Claims (7)

Forming an interlayer insulating film on the semiconductor substrate; Forming a hard mask film pattern to selectively expose the interlayer insulating film; Forming a contact hole by etching the interlayer insulating layer using the hard mask pattern as a mask; Forming a contact plug to fill the contact hole; Forming a TEOS oxide layer on the contact plug and the interlayer dielectric layer; Forming an etch stop layer on the TEOS oxide layer; And And forming a storage node electrode, a dielectric layer, and a plate electrode on the etch stop layer. The method of claim 1, The hard mask film pattern is a method of forming a capacitor of the semiconductor device, characterized in that using a silicon-containing oxynitride film (SRON). The method of claim 1, The TEOS oxide film is a capacitor forming method of a semiconductor device, characterized in that formed to a thickness of 400-500Å. The method of claim 1, The TEOS oxide film is a capacitor formation method of a semiconductor device, characterized in that formed not to exceed the thickness of 500 kHz. The method of claim 1, Forming the TEOS oxide film is supplied with a nitrogen (N ₂ ) gas at a flow rate of 1000-2000sccm at a process temperature of 350-450 ° C. and a pressure of 2.0-2.5 Torr, and nitrous oxide (N ₂ O) The gas is supplied at a flow rate of 9500-15000sccm, and the silane (SiH ₄ ) gas is supplied at a flow rate of 150-250sccm. The method of claim 1, The etch stop layer is formed using a plasma enhanced chemical vapor deposition (PECVD) method. The method of claim 1, The forming of the etch stop layer may include forming a capacitor by applying a power of 450-500 W while supplying a silane (SiH ₄ ) gas, an ammonium (NH ₃ ) gas, and a nitrogen (N ₂ ) gas. Formation method.

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