KR20080061724A - Array substrate of liquid crystal display device and method for fabricating the same, and method for an examination of a line of the same - Google Patents

Abstract

An array substrate of an LCD, a manufacturing method thereof, and a line inspection method thereof are provided to achieve rework by easily grasping a fault of gate patterns, thereby preventing deterioration of manufacture yield and reliability caused by a line defect and a point defect. A gate line(104) is formed on a substrate(101). A gate electrode(111) is defined in a part of the gate line. A storage line(131) is formed in parallel to the gate line. A gate insulating layer covers the front of the substrate where the gate line and the storage line are formed. The gate insulating layer has an open unit(114) for exposing the substrate between the gate lines at one end of the gate line. A semiconductor layer pattern is formed on the gate electrode. A data line(128) defines a pixel area by crossing the gate line. A source electrode(125) is protruded from the data line and overlapped with one side of the semiconductor layer pattern. A drain electrode(127) is spaced from the source electrode and overlapped with the other side of the semiconductor layer pattern. A pixel electrode(143) is connected with the drain electrode and formed in the pixel area.

Description

Array substrate of liquid crystal display device and method for fabricating the same, and method for an examination of a line of the same

1 is a plan view showing an array substrate of a liquid crystal display according to the present invention.

2A is a plan view illustrating a process of forming gate patterns in an array substrate of a liquid crystal display according to the present invention.

FIG. 2B is a cross-sectional view taken along the line II ′ of FIG. 2A; FIG.

3A is a plan view illustrating a process of forming data patterns in an array substrate of a liquid crystal display according to the present invention.

3B is a cross-sectional view taken along the line II ′ of FIG. 2A;

4A is a plan view illustrating a process of forming a passivation layer and an open portion in an array substrate of a liquid crystal display according to the present invention.

4B is a cross-sectional view taken along the line II ′ of FIG. 4A;

5A is a plan view illustrating a pixel electrode forming process in an array substrate of a liquid crystal display according to the present invention.

5B is a cross-sectional view taken along the line II ′ of FIG. 5A.

6 is a flowchart illustrating a manufacturing process including a gate pattern inspection process in an array substrate of a liquid crystal display according to the present invention.

<Description of Signs of Major Parts of Drawings>

101: substrate 104: gate wiring

105: gate inspection wiring 111: gate electrode

113: gate insulating film 114: open portion

115: semiconductor layer 117: protective film

125 source electrode 127 drain electrode

128: data wiring 131: storage wiring

133: common voltage supply line 135: pixel contact hole

143 pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate of a liquid crystal display device, a method of manufacturing the same, and a wiring inspection method of a liquid crystal display device for preventing a driving failure caused by a short of gate wiring forming metal layer patterns. will be.

Recently, with the rapid development of the information society, the necessity of flat panel displays having excellent characteristics such as thinning, light weight, and low power consumption has emerged. Among them, liquid crystal displays have a resolution. It is excellent in color display and image quality, and is actively applied to notebooks and desktop monitors.

In general, a liquid crystal display device arranges two substrates on which electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injects a liquid crystal material between the two substrates, and applies a voltage to the two electrodes to generate an electric field. By moving the liquid crystal molecules, the image is expressed by the transmittance of light that varies accordingly.

The liquid crystal display includes a liquid crystal panel in which liquid crystal is injected between two substrates, a backlight disposed under the liquid crystal panel and used as a light source, and a driving unit for driving the liquid crystal panel, which is located outside the liquid crystal panel.

Here, the driving unit includes a driving circuit (hereinafter referred to as a drive integrated circuit (D-IC)) for applying a signal to the wiring of the liquid crystal panel, and according to a method of packaging the D-IC in the liquid crystal panel, the chip It is divided into on glass (COG), tape carrier package (TCP), chip on film (COF), and the like.

The COG method is a method of directly attaching a D-IC to an array substrate of a liquid crystal display device to directly connect an output electrode of the D-IC to a gate or a data pad on the array substrate. The advantages are simple and low manufacturing costs.

On the other hand, in the structure in which the common wiring is formed on the array substrate in the above-described COG type liquid crystal display device, since the common wiring and the gate wiring are formed adjacent to each other, a short occurs between the two wirings during the gate wiring formation process. Since the case is often frequent, there is a problem that a defect occurs and the reliability is low.

SUMMARY OF THE INVENTION The present invention has a first object to provide an array substrate of a liquid crystal display device capable of reworking a defect of a gate pattern easily and a method of manufacturing the same.

The present invention has a second object to provide a wiring inspection method of a liquid crystal display device which can easily detect a short between the gate wiring and the storage wiring.

In order to achieve the first object described above, an array substrate of a liquid crystal display according to the present invention includes a gate wiring formed on the substrate and a gate electrode defined in a part of the gate wiring; A storage wiring formed in parallel with the gate wiring; A gate insulating layer covering an entire surface of the substrate on which the gate wiring and the storage wiring are formed, and having an open portion exposing the substrate between the gate wiring at one end of the gate wiring; A semiconductor layer pattern formed on the gate electrode; A data line crossing the gate line to define a pixel area; A source electrode protruding from the data line and overlapping with one side of the semiconductor layer pattern and a drain electrode spaced apart from the source electrode and overlapping with the other side of the semiconductor layer pattern; And a pixel electrode connected to the drain electrode and formed in the pixel region.

In addition, in order to achieve the above-described first object, a method of manufacturing an array substrate of a liquid crystal display according to the present invention includes: gate wirings including a gate electrode on the substrate, and storage wirings formed in parallel with the gate wirings. Forming a gate test wiring connected to one end of the gate wirings; Forming a gate insulating film on an entire surface of the substrate on which the gate wiring and the storage wiring are formed; Forming a semiconductor layer pattern on the gate insulating layer corresponding to the gate electrode; A data line defining a pixel area crossing the gate line and a source electrode protruding from the data line and overlapping one side of the semiconductor layer pattern, and a drain electrode spaced apart from the source electrode and overlapping the other side of the semiconductor layer pattern. Forming; Forming a passivation layer on a front surface of the substrate including the source electrode and the drain electrode, and forming a pixel contact hole exposing a portion of the drain electrode and an open portion exposing the gate inspection line between the gate line; And depositing and patterning a transparent conductive metal layer on the passivation layer to form a pixel electrode connected to the drain electrode through the pixel contact hole, and removing and disconnecting the gate inspection wiring exposed through the open portion. It is characterized by.

In addition, the wiring inspection method of the liquid crystal display according to the present invention in order to achieve the second object, the gate wirings on the substrate, the storage wirings parallel to the gate wirings, the gate connected to one end of the gate wirings Forming a test wiring and a common voltage supply line connected to the storage wirings; Checking whether the gate line and the storage line are short by measuring an electrical value of the gate check line; If a short occurs between the gate line and the storage line, the gate line and the storage line are removed. If a short does not occur between the gate line and the storage line, the data line crosses the gate line and the gate line. Forming a thin film transistor connected to the data line; Forming an open portion on the entire surface of the substrate and exposing the gate inspection wiring; And removing and disconnecting the gate test wiring exposed through the open part.

According to the present invention, the defects of the gate patterns on the array substrate of the liquid crystal display device can be easily recognized and reworked, thereby reducing manufacturing yields and reliability decreases due to line defects and point defects.

The present invention can easily inspect whether or not a short between the storage wiring and the gate wiring, and the process is simple by disconnecting at the time of forming the pixel electrode without a separate process for removing the inspection wiring for inspection.

Hereinafter, an array substrate of a liquid crystal display according to the present invention and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

1 is a plan view showing an array substrate of a liquid crystal display according to the present invention.

As shown in FIG. 1, the array substrate 100 of the liquid crystal display device is divided into a display area AA inside the dotted line on which an image is displayed and a non-display area NA outside the dotted line.

First, a plurality of gate wirings 104 and data wirings 128 are formed in the display area AA, and the gate wirings 104 and the data wirings 128 intersect to define the pixel region P. FIG. . Although not shown, a thin film transistor (not shown), which is a switching element, is formed at a point where the gate line 104 and the data line 128 intersect, and the thin film transistor (not shown) in each pixel region P is shown. And a pixel electrode (not shown) are formed.

Next, in the non-display area NA, gate and data link wirings 105 and 137 connected to one end of the gate line 104 and the data line 128 are formed, respectively, and the gate and data link wirings ( The gate pad electrode 107 and the data pad electrode 140 are connected to one end of each of the 105 and 137, and the gate pad electrode 107 and the data pad electrode 140 are mounted on the array substrate 100. Connected to the gate D-IC 163 and the data D-IC 160, respectively.

The gate D-IC 163 and the data D-IC 160 may be connected to an external printed circuit board (PCB) (not shown) through a flexible printed circuit (FPC) 170 and 172. Each is connected.

In the non-display area, the gate lines 104 are disconnected by an open part 114 formed between the gate lines 104 at the other end of the gate line 104 to which the gate D-IC is not connected. ..

A gate test wiring 105 extends from the gate wiring 104 to the open portion 114 between the gate wiring 104 and the gate wiring 104.

Therefore, the gate inspection wiring 105 is formed on both sides of the open portion 114 spaced apart from each other.

Storage wirings 131 are formed in the same direction as the gate wirings 104, and the storage wirings 131 are tied to the common voltage supply line 133 and connected to each other.

Since the gate wiring 104 and the storage wiring 131 are formed at positions adjacent to each other in the same process, the gate wiring 104 and the storage wiring 131 may be shorted during the process. Therefore, the gate lines 104 may be bundled to apply a test signal to check whether the gate lines 104 have a short with the storage lines 131.

In addition, since the storage wirings 131 are bundled because the same common voltage is applied, the storage wirings 131 apply the test signal to the storage wirings 131 by using the same common voltage. You can check whether a short has occurred.

Hereinafter, the manufacturing process and the inspection process of the array substrate of the liquid crystal display according to the present invention will be described in order.

2A is a plan view illustrating a process of forming gate patterns in an array substrate of a liquid crystal display according to the present invention, and FIG. 2B is a cross-sectional view taken along the line II ′ of FIG. 2A.

Here, the gate patterns refer to the gate wiring 104, the gate electrode 111, the storage wiring 131, and the like, which are formed by patterning a deposited metal layer to form the gate wiring 104.

As shown in FIGS. 2A and 2B, the array substrate 100 of the liquid crystal display according to the present invention has the same direction as the gate wiring 104 and the gate wiring 104 in one direction on the substrate 101. The storage wiring 131 is formed.

A portion of the gate wire 104 protrudes to form the gate electrode 111.

The gate electrode 111 is not necessarily protruded from the gate line 104, and may be a portion or an area capable of receiving a gate signal from the gate line 104.

One end of the storage wires 131 is connected to the common voltage supply line 133 and is connected to the first test pad outside the substrate 101.

One end of the gate lines 104 is connected to the gate test line 105 and is connected to a second test pad outside the substrate 101.

The gate test line 105 formed at one end of the gate lines 104 and the common voltage supply line 133 formed at one end of the storage lines 131 are disposed at different positions, for example, facing substrates. It may be formed at the corners of the 101, respectively.

Materials forming the gate wiring 104, the storage wiring 131, the common voltage supply line 133, and the gate inspection wiring 105 may include copper (Cu), aluminum (Al), and aluminum alloy (AlNd: Aluminum). Neodymium, molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta) and molybdenum-tungsten (MoW) may include at least one selected from the group consisting of.

The gate wiring 104 and the storage wiring 131 may not only be formed of a metal layer of a single layer, but may also be formed of a double layer, a triple layer, or a multilayer metal line.

Here, the gate test line 105 connected to the gate lines 104 is connected to a second test pad. The common voltage supply line 133 connected to the storage lines 131 is connected to a first test pad. The resistance value may be measured at the second test pad and the first test pad, respectively, to check whether a short occurs between the storage wiring 131 and the gate wiring 104.

In this case, when a short occurs between the gate line 104 and the storage line 131, the gate patterns may be removed and the gate patterns may be formed again, thereby reworking.

The liquid crystal display array substrate 100 has a mass production system (MPS) inspection that inspects defects such as line defects and point defects such as the gate or data wiring before completion thereof. The first test pad is advantageous in that it can also be used for applying a signal for MPS inspection after fabricating the array substrate of the liquid crystal display.

3A is a plan view illustrating a process of forming data patterns in an array substrate of a liquid crystal display according to the present invention, and FIG. 3B is a cross-sectional view taken along the line II ′ of FIG. 2A.

The data patterns refer to the data line 128, the source electrode 125, and the drain electrode 127 formed by patterning the deposited metal layer to form the data line 128.

As shown in FIGS. 3A and 3B, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the entire surface of the substrate 101 by, for example, a plasma enhanced chemical vapor deposition (PECVD) method. Thus, the gate insulating film 113 is formed.

An amorphous silicon layer and an amorphous silicon layer implanted with impurities are sequentially formed on the gate insulating layer 113.

The semiconductor layer 115 is formed at a position corresponding to the gate electrodes by patterning the amorphous silicon layer and the amorphous silicon layer in which the impurities are implanted.

Thereafter, a data line forming metal layer is formed on the gate insulating layer 113 on which the semiconductor layer 115 is formed.

The data line forming metal layer is patterned to simultaneously form the data line 128 on the substrate 101 in a direction crossing the gate line 104.

The source electrode 125 overlapping one end of the semiconductor layer 115 and the drain electrode 127 spaced apart from the source electrode 125 at the other end of the semiconductor layer 115 are disposed from the data line 128. Form.

As a result, the gate line 104 and the data line 128 define the pixel region P while crossing each other with the gate insulating layer 113 interposed therebetween.

The source electrode 125 branched from the data line 128 extends to one end of the semiconductor layer 115 above the gate electrode 111, and the source electrode 125 is formed at the other end of the semiconductor layer 115. A drain electrode 127 is formed spaced apart from the 125.

The gate electrode 111, the semiconductor layer 115, the source electrode 125, and the drain electrode 127 form a thin film transistor TFT.

The semiconductor layer 115 and the data patterns may be formed by a single mask process using a diffraction mask or a half-tone mask.

In this case, the semiconductor layer 115 pattern is essentially formed under the data line 128.

4A is a plan view illustrating a process of forming a passivation layer and an open portion in an array substrate of an LCD according to the present invention, and FIG. 4B is a cross-sectional view taken along the line II ′ of FIG. 4A.

4A and 4B, a passivation layer 117 is formed on the gate insulating layer 113.

In addition, an open part 114 for opening the gate inspection line 105 is formed in the passivation layer 117 and the gate insulating layer 113 to expose a portion of the gate inspection line 105.

The open part 114 is formed on the gate test wiring 105 between the gate wiring 104 and the gate wiring 104.

A pixel contact hole 135 exposing a portion of the drain electrode 127 is also formed when the open portion 114 is formed.

5A is a plan view illustrating a pixel electrode forming process in an array substrate of a liquid crystal display according to the present invention, and FIG. 5B is a cross-sectional view taken along the line II ′ of FIG. 5A.

As shown in FIGS. 5A and 5B, a pixel electrode 143 is formed in the pixel region P. As shown in FIG.

The pixel electrode 143 is connected to the drain electrode 127 through the pixel contact hole 135.

In order to form the pixel electrode 143, a transparent conductive metal is deposited and patterned on the entire surface of the substrate 101 to form the pixel electrode 143.

The transparent conductive metal may include at least one selected from the group of transparent conductive metals consisting of indium-tin-oxide (ITO) and indium-zinc-oxide (IZO).

When the transparent conductive metal is patterned, an unnecessary portion of the transparent conductive metal is etched by wet etching, wherein the gate inspection wiring 105 exposed through the open portion 114 is also etched.

Thus, the gate test wiring 105 is disconnected by the open portion 114 between the gate wiring 104 and the gate wiring 104 and consequently the gate wiring 104 and the gate wiring 104. ) Is cut off electrically.

Since the gate signals are applied to each of the gate lines 104, the gate lines 104 should not be electrically connected to each other.

One end of the gate lines 104 is connected by the gate test line 105 to check whether the gate lines 104 and the storage lines 131 are shorted, but after the inspection of the gate patterns is completed. The gate wiring 104 should be electrically disconnected from each other. The gate inspection line 105 may be exposed through the open part 114, and the exposed gate inspection line 131 may be removed when the pixel electrode 143 is patterned.

6 is a flowchart illustrating a manufacturing process including a gate pattern inspection process in an array substrate of a liquid crystal display according to the present invention.

First, gate patterns are formed on the substrate 101 (S100).

The gate patterns refer to a gate wiring 104, a gate electrode 111, a storage wiring 131, and the like, formed by patterning a deposited metal layer to form the gate wiring 104.

The gate wiring 104 is formed on the substrate in one direction, and the storage wiring 131 is formed in the same direction as the gate wiring 104.

One end of the storage wires 131 is connected to the common voltage supply line 133 and is connected to the first test pad outside the substrate 101.

One end of the gate lines 104 is connected to the gate test line 105 and is connected to the second test pad outside the substrate 101.

Thereafter, the gate patterns formed on the substrate 101 are inspected (S110).

Since the gate wiring 104 and the storage wiring 131 are formed in close proximity to each other, a short may occur during the process, and thus the second test pad may be formed after the process of forming the gate wiring 104 and the storage wiring 131. Perform the inspection using.

For example, when the resistance of the second test pad rises sharply or a change is detected in the signal, it may be determined that a short has occurred between the gate line 104 and the storage line 131.

The first test pad connected to the common voltage supply line 105 may be used to check whether the storage line 131 and the gate line 104 are shorted.

At least one test pad of the first test pad and the second test pad may be used to check whether the gate patterns are shorted, and a signal may be applied to both the first test pad and the second test pad to be compared. It can also detect whether it is short.

In this case, when a short occurs between the gate line 104 and the storage line 131, the gate patterns may be removed and the gate patterns may be formed again, thereby reworking.

Thereafter, data patterns are formed on the substrate 101 on which the gate patterns are formed (S120).

Here, the data patterns refer to the data line 128, the source electrode 125, and the drain electrode 127 formed by patterning the deposited metal layer to form the data line.

The data line 128 crosses the gate line 104 to define a pixel region P, and the gate electrode 111 and the source and drain electrodes 125 and 127 constitute a thin film transistor.

Thereafter, a passivation layer 117 is formed over the substrate 101 on which the thin film transistor is formed, and the pixel contact hole 135 exposing a part of the drain electrode 127 to the passivation layer 117 and the gate insulating layer 113. ) And an open portion 114 exposing a portion of the gate test wiring 105 (S130).

The open part 114 is formed in the gate test wiring 105 between the gate wiring 104 and the gate wiring 104.

Thereafter, a pixel electrode 143 is formed through the pixel contact hole 135 to be connected to the drain electrode 127 and patterned in the pixel region P (S140).

When the pixel electrode 143 is patterned, the gate inspection wiring 105 exposed through the open portion 114 is etched to open the gate inspection wiring 105 in the open portion 114 so as to open the gate wiring. The 104 and the gate wiring 104 are electrically disconnected.

Although the present invention has been described in detail through specific embodiments, this is for explaining the present invention in detail, and the array substrate and the manufacturing method thereof of the liquid crystal display device according to the present invention are not limited thereto, and within the technical spirit of the present invention. It is apparent that modifications and improvements are possible by those skilled in the art.

According to the present invention, since the defects of the gate patterns on the array substrate of the liquid crystal display device can be easily recognized and reworked, the first effect of preventing manufacturing yield degradation and reliability reduction due to line defects and point defects is prevented. have.

The present invention can easily inspect whether or not a short between the storage wiring and the gate wiring, and has a second effect in that the process is simple by disconnecting at the time of forming the pixel electrode without a separate process for removing the inspection wiring for inspection.

Claims (14)

A gate wiring formed on the substrate and a gate electrode defined in part of the gate wiring; A storage wiring formed in parallel with the gate wiring; A gate insulating layer covering an entire surface of the substrate on which the gate wiring and the storage wiring are formed, and having an open portion exposing the substrate between the gate wiring at one end of the gate wiring; A semiconductor layer pattern formed on the gate electrode; A data line crossing the gate line to define a pixel area; A source electrode protruding from the data line and overlapping with one side of the semiconductor layer pattern and a drain electrode spaced apart from the source electrode and overlapping with the other side of the semiconductor layer pattern; And And a pixel electrode connected to the drain electrode and formed in the pixel area. The method of claim 1, And a passivation layer formed over the substrate on which the source and drain electrodes are formed, the passivation layer including a pixel contact hole exposing the drain electrode and an open portion exposing the substrate. The method of claim 1, And an gate inspection wiring disconnected by the open portion is formed at the one end of the gate wiring. The method of claim 1, And a common voltage supply line connecting one end of the storage wires. Forming gate wirings including a gate electrode on the substrate, storage wirings formed in parallel with the gate wirings, and a gate test wiring connected to one end of the gate wirings; Forming a gate insulating film on an entire surface of the substrate on which the gate wiring and the storage wiring are formed; Forming a semiconductor layer pattern on the gate insulating layer corresponding to the gate electrode; A data line defining a pixel area crossing the gate line and a source electrode protruding from the data line and overlapping one side of the semiconductor layer pattern, and a drain electrode spaced apart from the source electrode and overlapping the other side of the semiconductor layer pattern. Forming; Forming a passivation layer on a front surface of the substrate including the source electrode and the drain electrode, and forming a pixel contact hole exposing a portion of the drain electrode and an open portion exposing the gate inspection line between the gate line; And Depositing and patterning a transparent conductive metal layer on the passivation layer to form a pixel electrode connected to the drain electrode through the pixel contact hole, and removing and disconnecting the gate inspection wiring exposed through the open part. A method of manufacturing an array substrate of a liquid crystal display device. The method of claim 5, And a common voltage supply line connecting one end of the storage lines to the storage substrate. The method of claim 6, And said common voltage supply line is formed on a side different from said gate test wiring. Forming gate wirings, storage wirings parallel to the gate wirings, a gate test wiring connected to one end of the gate wirings, and a common voltage supply line connected to the storage wirings on a substrate; Checking whether the gate line and the storage line are short by measuring an electrical value of the gate check line; If a short occurs between the gate line and the storage line, the gate line and the storage line are removed. If a short does not occur between the gate line and the storage line, the data line crosses the gate line and the gate line. Forming a thin film transistor connected to the data line; Forming an open portion on the entire surface of the substrate and exposing the gate inspection wiring; And And disconnecting the gate inspection wiring exposed through the open part, and disconnecting the wiring. The method of claim 8, In the forming of the thin film transistor, Forming a semiconductor layer pattern on the gate insulating layer corresponding to the gate electrode protruding from the gate wiring; And And forming a source electrode protruding from the data wire and overlapping with one side of the semiconductor layer pattern and a drain electrode spaced apart from the source electrode and overlapping with the other side of the semiconductor layer pattern. Wiring inspection method. The method of claim 8, In the forming of the open portion, And a pixel contact hole exposing a portion of the drain electrode and forming a passivation layer on the entire surface of the substrate including the source electrode and the drain electrode. The method of claim 8, In the step of removing and disconnecting the gate test wiring, Depositing a transparent conductive metal layer on the substrate on which the thin film transistor is formed; And Patterning the transparent conductive metal layer to form a pixel electrode connected to the thin film transistor, and removing the gate inspection wiring exposed through the open portion. The method of claim 8, And the common voltage supply line is formed on a side different from the gate inspection line. The method of claim 8, In the step of checking whether the gate wiring and the storage wiring is short by measuring the electrical value of the gate test wiring, And inspecting whether the gate wiring and the storage wiring are short by measuring an electrical value of the common voltage supply line. The method of claim 8, And the electrical value is a resistance value.

Images