KR20080060633A - Method of forming semiconductor device using the tungsten layer - Google Patents

Method of forming semiconductor device using the tungsten layer Download PDF

Info

Publication number
KR20080060633A
KR20080060633A KR1020060134974A KR20060134974A KR20080060633A KR 20080060633 A KR20080060633 A KR 20080060633A KR 1020060134974 A KR1020060134974 A KR 1020060134974A KR 20060134974 A KR20060134974 A KR 20060134974A KR 20080060633 A KR20080060633 A KR 20080060633A
Authority
KR
South Korea
Prior art keywords
tungsten film
tungsten
forming
trench
film
Prior art date
Application number
KR1020060134974A
Other languages
Korean (ko)
Other versions
KR100866669B1 (en
Inventor
김정주
Original Assignee
동부일렉트로닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 동부일렉트로닉스 주식회사 filed Critical 동부일렉트로닉스 주식회사
Priority to KR1020060134974A priority Critical patent/KR100866669B1/en
Publication of KR20080060633A publication Critical patent/KR20080060633A/en
Application granted granted Critical
Publication of KR100866669B1 publication Critical patent/KR100866669B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A manufacturing method of a semiconductor device using a tungsten film is provided to eliminate defects caused by a key hole and a void/seam completely by forming uniform tungsten wiring. An insulating layer(120) is formed on a semiconductor substrate(110). A contact hole and a trench are formed by removing the insulating layer selectively. A barrier layer(130) is formed on the entire surface of the insulating layer. A first tungsten film(140) is formed on the barrier layer by ALD(Atomic Layer Deposition). A second tungsten film(150) is formed on the first tungsten film by CVD(Chemical Vapor Deposition). Tungsten wiring is formed within the trench and the contact hole.

Description

텅스텐 막을 이용한 반도체 소자 형성 방법{METHOD OF FORMING SEMICONDUCTOR DEVICE USING THE TUNGSTEN LAYER}Method of forming semiconductor device using tungsten film {METHOD OF FORMING SEMICONDUCTOR DEVICE USING THE TUNGSTEN LAYER}

도 1a 내지 도 1d는 본 발명의 실시 예에 따른 텅스텐 막을 이용한 반도체 소자 형성 방법을 단계적으로 나타내는 도면.1A through 1D are diagrams illustrating a method of forming a semiconductor device using a tungsten film according to an exemplary embodiment of the present invention.

<도면의 주요 부분에 대한 설명>Description of the main parts of the drawing

110 : 반도체 기판 120 : 절연막110 semiconductor substrate 120 insulating film

122 : 콘택홀 124 : 트렌치122: contact hole 124: trench

130 : 베리어층 140 : 제 1 텅스텐 막130: barrier layer 140: the first tungsten film

150 : 제 2 텅스텐 막 152 : 텅스텐 배선150: second tungsten film 152: tungsten wiring

본 발명은 반도체 소자의 형성 방법에 관한 것으로, 특히 작은 크기의 콘택홀에 텅스텐을 채울 수 있도록 한 텅스텐 막을 이용한 반도체 소자 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor device, and more particularly, to a method for forming a semiconductor device using a tungsten film to fill tungsten in a small contact hole.

반도체 소자에 있어서, 플러그 및 배선등은 저항이 작은 알루미늄, 구리 및 텅스텐 등과 같은 금속으로 형성된다. 금속들 중에 텅스텐은 우수한 스텝 커버리지 특성을 가지므로 반도체 소자의 고집적화에 따라 점점 사용 빈도가 높아지고 있다. In semiconductor devices, plugs and wirings are made of metals such as aluminum, copper, tungsten, and the like having low resistance. Among the metals, tungsten has excellent step coverage characteristics, and thus the frequency of use of tungsten increases with increasing integration of semiconductor devices.

또한 텅스텐은 융점이 3400℃ 이상으로 매우 높아 내열성이 좋으며 전자이동(Electro-migration)에 대한 저항이 매우 큰 장점을 갖는다.In addition, tungsten has a very high melting point of more than 3400 ℃ good heat resistance and has a very large resistance to electro-migration (Electro-migration).

반도체 소자에서 텅스텐막을 형성하는 방법은 화학기상증착(Chemical Vapor Deposition, CVD) 방법 또는 원자박막증착(Atomic Layer Deposition, ALD) 방법 등이 있다.A method of forming a tungsten film in a semiconductor device includes a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method.

화학기상증착 방법의 경우 반도체 소자의 크기가 작아지면서 점점 작아지는 콘택홀에 텅스텐막을 채우는 것은 매우 어렵다.In the case of the chemical vapor deposition method, it is very difficult to fill a tungsten film in a contact hole that is getting smaller as the size of the semiconductor device becomes smaller.

원자박막증착 방법의 경우 그 자체의 우수한 스텝 커버리지를 갖고 있어서 콘택홀을 충전하는데 매우 유리하나 콘택홀과 트렌치 구조를 채우기에는 그 쓰루풋(throughput)이 작기 때문에 실제 공정에 적용하기에는 어렵다.The atomic thin film deposition method has an excellent step coverage of its own, which is very advantageous for filling contact holes, but its throughput is small for filling contact holes and trench structures, and thus it is difficult to apply to actual processes.

본 발명은 상기와 같은 문제점을 해결하기 위한 것으로, 작은 크기의 콘택홀에 텅스텐을 채울 수 있도록 한 텅스텐 막을 이용한 반도체 소자 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and an object thereof is to provide a method of forming a semiconductor device using a tungsten film to fill tungsten in a small contact hole.

상기와 같은 목적을 달성하기 위한 본 발명에 따른 텅스텐 막을 이용한 반도체 소자의 형성 방법은 반도체 기판 상에 절연막을 형성하는 단계와, 상기 절연막을 선택적으로 제거하여 콘택홀 및 트렌치를 형성하는 단계와, 상기 콘택홀 및 상기 트렌치가 형성된 상기 절연막의 전면에 베리어층을 형성하는 단계와, 원자박막 증착 공정을 이용하여 상기 베리어층에 제 1 텅스텐 막을 형성하는 단계와, 화학기상증착 공정을 이용하여 제 1 텅스텐 막에 제 2 텅스텐 막을 형성하는 단계와, 평탄화 공정을 수행하여 상기 콘택홀 및 상기 트렌치 내부에 텅스텐 배선을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.A method of forming a semiconductor device using a tungsten film according to the present invention for achieving the above object comprises the steps of forming an insulating film on a semiconductor substrate, selectively removing the insulating film to form contact holes and trenches, Forming a barrier layer on the entire surface of the insulating film on which the contact hole and the trench are formed, forming a first tungsten film on the barrier layer using an atomic thin film deposition process, and using a chemical vapor deposition process; And forming a second tungsten film in the film, and forming a tungsten wire in the contact hole and the trench by performing a planarization process.

상기 제 1 텅스텐 막은 상기 베리어층 상에 1000Å 이하의 두께로 형성되는 것을 특징으로 한다.The first tungsten film is formed on the barrier layer to a thickness of less than 1000Å.

상기 제 1 텅스텐 막은 상기 콘택홀에 채워짐과 아울러 상기 트렌치의 측벽에 형성됨을 특징으로 한다.The first tungsten film is formed on the sidewalls of the trench while being filled in the contact hole.

상기 제 1 텅스텐 막은 상기 제 2 텅스텐 막의 시드층인 것을 특징으로 한다.The first tungsten film is characterized in that the seed layer of the second tungsten film.

상기 제 2 텅스텐 막은 상기 트렌치의 나머지 부분에 형성됨을 특징으로 한다.The second tungsten film is formed in the remaining portion of the trench.

상기 베리어층은 Ti, TiN, Ta, TaN 및 WNx 중 어느 하나의 재질인 것을 특징으로 한다.The barrier layer is characterized in that the material of any one of Ti, TiN, Ta, TaN and WNx.

이하, 첨부된 도면을 참고하여 본 발명에 의한 텅스텐 막을 이용한 반도체 소자의 형성방법을 보다 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a semiconductor device using a tungsten film according to the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1d는 본 발명의 실시 예에 따른 텅스텐 막을 이용한 반도체 소자 형성 방법을 단계적으로 나타내는 도면이다.1A to 1D are diagrams illustrating a method of forming a semiconductor device using a tungsten film according to an exemplary embodiment of the present inventive concept.

먼저, 도 1a에 도시된 바와 같이, 반도체 기판(110) 상에 절연막(120)을 형성한 후, 절연막(120)의 표면이 소정부분 노출되도록 듀얼 다마신(dual damascene) 공정에 의해 절연막(120)을 선택적으로 제거하여 콘택홀(122) 및 트렌치(124)를 형성한다. 여기서, 포토 및 식각공정을 이용하여 콘택홀(122)과 트렌치(124)를 각각 형성한다. 이때, 콘택홀(122)을 형성한 후 그 인접영역을 선택적으로 제거하여 트렌치(124)를 형성하거나 트렌치(124)를 형성한 후 트렌치(124) 폭보다 좁게 콘택홀(122)을 형성한다.First, as shown in FIG. 1A, after the insulating film 120 is formed on the semiconductor substrate 110, the insulating film 120 is formed by a dual damascene process to expose a predetermined portion of the surface of the insulating film 120. ) May be selectively removed to form the contact hole 122 and the trench 124. The contact holes 122 and the trenches 124 are formed using photo and etching processes, respectively. In this case, after the contact hole 122 is formed, the adjacent region is selectively removed to form the trench 124 or the trench 124 is formed, and then the contact hole 122 is formed to be narrower than the width of the trench 124.

이어, 트렌치(124) 및 콘택홀(122)이 형성된 절연막(120)의 전면에 텅스텐(W) 증착을 위한 베리어층(130)을 형성한다. 이때, 베리어층(130)은 Ti, TiN, Ta, TaN, WNx 등의 재질로 형성된다.Subsequently, a barrier layer 130 for depositing tungsten (W) is formed on the entire surface of the insulating layer 120 on which the trench 124 and the contact hole 122 are formed. At this time, the barrier layer 130 is formed of a material such as Ti, TiN, Ta, TaN, WNx.

이어, 도 1b에 도시된 바와 같이, 원자박막증착 공정을 이용하여 콘택홀(122)만을 채우는 것을 목적으로 베리어층(130) 상에 약 1000Å 이하의 두께로 제 1 텅스텐 막(140)을 증착한다. 원자박막증착 공정에 의한 제 1 텅스텐 막(140)의 증착은 소스 가스 공급 공정과, 1차 퍼지 공정과, 환원 가스 공급 공정, 2차 퍼지 공정을 순차 수행하는 증착 사이클을 통하여 원하는 두께의 막이 얻어질 때까지 반복적으로 수행한다. 이때 원자박막증착 공정에 의해서 콘택홀(122) 부분에는 제 1 텅스텐 막(140)이 완전히 채워지게 되고, 트렌치(124) 부분에는 아직 두께가 충분하지 않아 제 1 텅스텐 막(140)이 완전히 채워지지 않은 상태로 증착된다. 또한 원자박막증착 공정은 스텝 커버리지가 매우 좋기 때문에 제 1 텅스텐 막(140)이 트렌치(124)의 측벽(sidewall)에 균일하게 증착된다. 이러한, 제 1 텅스텐 막(140)은 시드층(seed layer)의 역할을 한다.Subsequently, as illustrated in FIG. 1B, the first tungsten film 140 is deposited on the barrier layer 130 to a thickness of about 1000 μs or less for the purpose of filling only the contact hole 122 using an atomic thin film deposition process. . The deposition of the first tungsten film 140 by the atomic thin film deposition process obtains a film having a desired thickness through a deposition cycle in which a source gas supply process, a primary purge process, a reducing gas supply process, and a secondary purge process are sequentially performed. Repeatedly until lost. In this case, the first tungsten film 140 is completely filled in the contact hole 122 by the atomic thin film deposition process, and the first tungsten film 140 is not completely filled in the trench 124 because the thickness is not sufficient. Undeposited. In addition, in the atomic thin film deposition process, since the step coverage is very good, the first tungsten film 140 is uniformly deposited on the sidewall of the trench 124. The first tungsten film 140 serves as a seed layer.

이어, 도 1c에 도시된 바와 같이, 화학기상증착 공정을 이용하여 트렌 치(124)의 나머지 부분을 채우기 위한 목적으로 제 1 텅스텐 막(140)이 증착된 반도체 기판(110) 상에 제 2 텅스텐 막(150)을 증착한다. 이때, 트렌치(124)의 측벽에는 원자박막증착 공정에 의해 시드층 역할을 하는 제 1 텅스텐 막(140)이 매우 균일하게 증착되어 있으므로, 시드층 역할을 하는 제 1 텅스텐 막(140)에 매우 균일하게 증착된다. 이때, 비록 트렌치(124)라 하더라도 콘택홀(122)보다 좀 더 텅스텐을 채우는데 용이하지만 0.15um급에서는 그 폭이 0.19um 이하이고 두께가 3000Å 이상이므로, 화학기상증착 공정을 이용함으로써 후속 공정인 화학적 기계 연마 공정시 키-홀(key-hole)이 드러나지 않도록 무리 없이 증착할 수 있다.Subsequently, as shown in FIG. 1C, the second tungsten is deposited on the semiconductor substrate 110 on which the first tungsten film 140 is deposited for the purpose of filling the remaining portion of the trench 124 using a chemical vapor deposition process. A film 150 is deposited. In this case, since the first tungsten film 140 serving as the seed layer is deposited very uniformly on the sidewall of the trench 124 by the atomic thin film deposition process, the first tungsten film 140 serving as the seed layer is very uniform. Is deposited. At this time, although the trench 124 is easier to fill the tungsten than the contact hole 122, but in the 0.15um class the width is less than 0.19um and the thickness is more than 3000Å, the subsequent process by using a chemical vapor deposition process In the chemical mechanical polishing process, the key-holes can be deposited without difficulty.

이어, 도 1d에 도시된 바와 같이, 제 2 텅스텐 막(150)이 형성된 반도체 기판(110)의 전면에 화학적 기계 연마(CMP: Chemical Mechanical Polishing) 공정을 실시하여 트렌치(124) 및 콘택홀(122)의 내부에 텅스텐 배선(152)을 형성하여 완성한다.Subsequently, as illustrated in FIG. 1D, a chemical mechanical polishing (CMP) process is performed on the entire surface of the semiconductor substrate 110 on which the second tungsten film 150 is formed, thereby forming the trench 124 and the contact hole 122. The tungsten wiring 152 is formed inside of the c).

그리고 화학적 기계 연막 공정에 의해 유발된 표면결함 및 불순물입자(particle)를 제거하기 위하여 세정공정을 실시한다.In addition, a cleaning process is performed to remove surface defects and impurity particles caused by the chemical mechanical smoke process.

한편, 이상에서 설명한 본 발명은 상술한 실시예 및 첨부된 도면에 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention It will be apparent to those of ordinary skill in Esau.

이상에서 설명한 바와 같은 본 발명의 실시 예에 따른 텅스텐 막을 이용한 반도체 소자의 형성방법은 다음과 같은 효과가 있다.The method of forming a semiconductor device using a tungsten film according to the embodiment of the present invention as described above has the following effects.

첫째, 작은 크기의 콘택홀에 텅스텐을 채울 수 있다.First, small contact holes can be tungsten-filled.

둘째, 원자박막증착 공정을 트렌치에 텅스텐을 채우기 위한 시드층을 형성하는 공정으로 사용할 수 있다.Second, the atomic thin film deposition process may be used as a process for forming a seed layer for filling tungsten in the trench.

셋째, 원자박막증착 공정의 낮은 쓰루-풋을 작은 크기의 콘택홀에 텅스텐을 채우는데 사용함으로써 필요에 따라서 콘택홀의 크기를 원자박막증착 공정에 맞추어 작게 맞추도록 설계에 반영할 수 있으므로 반도체 소자의 크기를 감소시킬 수 있다.Third, the size of the semiconductor device can be reflected in the design so that the low through-put of the atomic thin film deposition process is used to fill tungsten in the small sized contact hole, so that the size of the contact hole can be made small according to the atomic thin film deposition process if necessary. Can be reduced.

넷째, 원자박막증착 공정과 화학기상증착을 조합하여 균일한 텅스텐 배선을 형성함으로써 후속 공정인 화학적 기계 연막 공정 후 키-홀 또는 보이드(void )/심(seam)에 의한 결함을 완벽히 제거할 수 있다.Fourth, by combining the atomic thin film deposition process and chemical vapor deposition to form a uniform tungsten wiring, defects caused by key-holes or voids / seams can be completely removed after the subsequent chemical mechanical smoke deposition process. .

Claims (6)

반도체 기판 상에 절연막을 형성하는 단계와,Forming an insulating film on the semiconductor substrate, 상기 절연막을 선택적으로 제거하여 콘택홀 및 트렌치를 형성하는 단계와,Selectively removing the insulating layer to form contact holes and trenches; 상기 콘택홀 및 상기 트렌치가 형성된 상기 절연막의 전면에 베리어층을 형성하는 단계와,Forming a barrier layer on an entire surface of the insulating layer on which the contact hole and the trench are formed; 원자박막증착 공정을 이용하여 상기 베리어층에 제 1 텅스텐 막을 형성하는 단계와,Forming a first tungsten film on the barrier layer using an atomic thin film deposition process, 화학기상증착 공정을 이용하여 제 1 텅스텐 막에 제 2 텅스텐 막을 형성하는 단계와,Forming a second tungsten film on the first tungsten film using a chemical vapor deposition process, 평탄화 공정을 수행하여 상기 콘택홀 및 상기 트렌치 내부에 텅스텐 배선을 형성하는 단계Forming a tungsten wire in the contact hole and the trench by performing a planarization process 를 포함하는 텅스텐 막을 이용한 반도체 소자 형성 방법.Method of forming a semiconductor device using a tungsten film comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제 1 텅스텐 막은 상기 베리어층 상에 1000Å 이하의 두께로 형성되는 것을 특징으로 하는 텅스텐 막을 이용한 반도체 소자 형성 방법.And the first tungsten film is formed on the barrier layer to a thickness of 1000 Å or less. 제 1 항에 있어서,The method of claim 1, 상기 제 1 텅스텐 막은 상기 콘택홀에 채워짐과 아울러 상기 트렌치의 측벽 에 형성됨을 특징으로 하는 텅스텐 막을 이용한 반도체 소자 형성 방법.And the first tungsten film is filled in the contact hole and formed on the sidewall of the trench. 제 1 항에 있어서,The method of claim 1, 상기 제 1 텅스텐 막은 상기 제 2 텅스텐 막의 시드층인 것을 특징으로 하는 텅스텐 막을 이용한 반도체 소자 형성 방법.And the first tungsten film is a seed layer of the second tungsten film. 제 3 항에 있어서,The method of claim 3, wherein 상기 제 2 텅스텐 막은 상기 트렌치의 나머지 부분에 형성됨을 특징으로 하는 텅스텐 막을 이용한 반도체 소자 형성 방법.And the second tungsten film is formed in the remainder of the trench. 제 1 항에 있어서,The method of claim 1, 상기 베리어층은 Ti, TiN, Ta, TaN 및 WNx 중 어느 하나의 재질인 것을 특징으로 하는 텅스텐 막을 이용한 반도체 소자 형성 방법.The barrier layer is a method of forming a semiconductor device using a tungsten film, characterized in that the material of any one of Ti, TiN, Ta, TaN and WNx.
KR1020060134974A 2006-12-27 2006-12-27 Method of forming semiconductor device using the tungsten layer KR100866669B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020060134974A KR100866669B1 (en) 2006-12-27 2006-12-27 Method of forming semiconductor device using the tungsten layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060134974A KR100866669B1 (en) 2006-12-27 2006-12-27 Method of forming semiconductor device using the tungsten layer

Publications (2)

Publication Number Publication Date
KR20080060633A true KR20080060633A (en) 2008-07-02
KR100866669B1 KR100866669B1 (en) 2008-11-04

Family

ID=39813137

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060134974A KR100866669B1 (en) 2006-12-27 2006-12-27 Method of forming semiconductor device using the tungsten layer

Country Status (1)

Country Link
KR (1) KR100866669B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019103995A1 (en) * 2017-11-22 2019-05-31 Applied Materials, Inc. Methods of reducing or eliminating defects in tungsten film

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100680940B1 (en) * 2000-12-28 2007-02-08 주식회사 하이닉스반도체 Method for forming metal line in semiconductor device
KR20050012580A (en) * 2003-07-25 2005-02-02 매그나칩 반도체 유한회사 Method for forming metal interconnection line of semiconductor device
KR100557626B1 (en) * 2003-12-23 2006-03-10 주식회사 하이닉스반도체 Method for Forming Bit-Line of Semiconductor Device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019103995A1 (en) * 2017-11-22 2019-05-31 Applied Materials, Inc. Methods of reducing or eliminating defects in tungsten film
CN110622283A (en) * 2017-11-22 2019-12-27 应用材料公司 Method for reducing or eliminating defects in tungsten films
US10879081B2 (en) 2017-11-22 2020-12-29 Applied Materials, Inc. Methods of reducing or eliminating defects in tungsten film

Also Published As

Publication number Publication date
KR100866669B1 (en) 2008-11-04

Similar Documents

Publication Publication Date Title
JP5430946B2 (en) Interconnect structure forming method
KR100475931B1 (en) Method for manufacturing a multi metal line in semiconductor device
US6541374B1 (en) Method of depositing a diffusion barrier for copper interconnection applications
US7470612B2 (en) Method of forming metal wiring layer of semiconductor device
KR20030000821A (en) Method for forming dual-damascene interconnect structures
JP2006510195A (en) Method for depositing a metal layer on a semiconductor interconnect structure having a cap layer
US20090026626A1 (en) Method for fabricating semiconductor device and semiconductor device
KR100672731B1 (en) Method for forming metal wiring in semiconductor device
JP4339152B2 (en) Method for forming wiring structure
US7732304B2 (en) Method of manufacturing semiconductor device
JP2005197637A (en) Method for forming metal wiring of semiconductor device
KR100866669B1 (en) Method of forming semiconductor device using the tungsten layer
JP2008305921A (en) Semiconductor device and manufacturing method therefor
US20090001579A1 (en) Multi-layered metal line having an improved diffusion barrier of a semiconductor device and method for forming the same
KR100732747B1 (en) Method for Forming Copper Wires in Semiconductor Device
KR100720401B1 (en) Method for Forming Cu lines in Semiconductor Device
KR100593125B1 (en) Method of forming a contact plug in a semiconductor device
KR20010061583A (en) A method for forming damascene metal wire in semiconductor device
KR101158059B1 (en) Method for forming metal line of semiconductor device
KR20100036008A (en) Method for forming metal wiring of semiconductor device
KR100639457B1 (en) Method for fabricating metal line in semiconductor device
US20090057271A1 (en) Manufacturing method of metal interconnection
KR100752167B1 (en) A method for fabricating wiring line of semiconductor device
KR100753420B1 (en) Method of manufacturing semiconductor device
KR20020048720A (en) A method for forming damascene metal wire using copper

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110920

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20120926

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee