KR20080060396A - Method of setting an inspection area - Google Patents

Abstract

A method of setting an inspection area is provided to set the inspection area at uniform accuracy always by automatically setting the inspection area in an inspection apparatus. A method of setting an inspection area includes the steps of: radiating light on a semiconductor substrate and detecting the light reflected from the semiconductor substrate(S1); obtaining an image of a pre-inspection area and generating a gray level profile for the pre-inspection area(S2); detecting positions out of a threshold by applying the threshold to the gray level profile(S3); and generating an inspection map by connecting the detected positions with a line on the gray level profile(S4).

Description

Method of setting an inspection area

1 is a block diagram showing an inspection apparatus according to an embodiment of the present invention.

2 is a plan view illustrating an example of a semiconductor substrate on which a pattern is formed.

3 is a plan view illustrating a preliminary inspection area in the pattern of FIG. 2.

4 is a flowchart illustrating a method for setting a test area, according to an exemplary embodiment.

5A and 5B are diagrams illustrating two-dimensional gray level profiles obtained from the preliminary inspection region of FIG. 3 according to an inspection region setting method according to an exemplary embodiment of the present invention.

6 is a diagram illustrating an example of an inspection map formed from FIGS. 5A and 5B by an inspection region setting method according to an exemplary embodiment of the present invention.

FIG. 7 is a diagram illustrating a 3D gray level profile obtained from the preliminary inspection region of FIG. 3 according to an inspection region setting method according to an exemplary embodiment of the present invention.

8 is a flowchart illustrating a test area setting method according to another exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1 semiconductor substrate 10 chuck

20 detection unit 21 light receiving unit

22: light emitting portion 25: design data (25)

30: setting unit 100: preliminary inspection area

110: cell area 111: unit cell

112: first boundary region 120: peripheral region

200: two-dimensional gray level profile

300: 3D gray level profile 400: inspection map

411: inspection region 412: second boundary region

The present invention relates to a method for setting an inspection region for a semiconductor substrate, and more particularly, to a method for setting an inspection region including a cell region for inspecting a defect on the pattern on a semiconductor substrate on which a pattern is formed.

In recent years, with the rapid spread of information media such as computers, semiconductor devices are also rapidly developing. In terms of its function, the semiconductor device is required to operate at a high speed and to have a large storage capacity. In response to these demands, semiconductor processing technologies have been developed in the direction of improving integration, reliability, response speed, and the like of the semiconductor device.

In general, a semiconductor device includes a Fab process for forming an electrical circuit including electrical elements on a silicon substrate used as a semiconductor substrate, and an EDS (electrical) for inspecting electrical characteristics of the semiconductor devices formed in the fab process. die sorting) and a package assembly process for encapsulating and individualizing the semiconductor devices with an epoxy resin.

The fab process includes a deposition process for forming a film on a semiconductor substrate, a chemical mechanical polishing process for planarizing the film, a photolithography process for forming a photoresist pattern on the film, and the photoresist pattern. An etching process for forming the film into a pattern having electrical characteristics, an ion implantation process for implanting specific ions into a predetermined region of the semiconductor substrate, a cleaning process for removing impurities on the semiconductor substrate, and the film or pattern Inspection process for inspecting the surface of the formed semiconductor substrate;

In order to achieve high integration and high performance of the semiconductor device, the inspection process must be performed in addition to accurately forming the microstructure constituting the electric circuit on the semiconductor substrate.

A cell area functioning as a circuit on the semiconductor substrate, a pad area in which structures for applying a voltage to the cell area are formed, and the bad cell when a bad cell occurs in the cell area And a fuse area in which structures such as a redundancy cell and an extra dummy cell are formed to replace the cell. In this case, the pad region and the fuse region are formed around the cell region. Therefore, inspections are performed on the cell region, the pad region, and the fuse region, respectively.

The cell region has a pattern in which a plurality of cells are spaced at the same interval and repeated. The pad region and the fuse region are irregularly formed patterns. In addition, the patterns formed in the pad area or the fuse area have substantially the same shape as each other.

In order to inspect the defects of the pad pattern and the fuse pattern that are irregularly positioned in this way, a task of setting the inspection area is first performed on a portion where the pad pattern and the fuse pattern are formed.

In the related art, in order to set the inspection area, the operator sets the inspection area while checking the patterns with the naked eye.

In the conventional inspection area setting method, since a difference may occur according to the skill of the operator, there is a problem that a lot of work time and human resources are required to set the inspection area. In addition, even if the worker is different or even if the same worker is done, the inspection area can be set differently, there is a problem that the reliability of the inspection area setting is lowered.

An object of the present invention for solving the above problems is to provide a test area setting method for reducing the setting time of the test area, and to improve the reliability and accuracy of the test area setting.

In order to achieve the object of the present invention, an inspection region setting method according to the present invention includes obtaining an image of a preliminary inspection region on a semiconductor substrate on which a circuit pattern is formed; Creating, acquiring coordinates corresponding to pixels deviating from a predetermined threshold on the gray level profile, forming an inspection map for the preliminary inspection area using the coordinates, and the inspection map Selecting an inspection area.

In an embodiment, the gray level profile can be created in two dimensions. Here, the preliminary inspection area may include a plurality of sub areas, and the gray level profile may be formed by a change of gray levels with respect to the sub area and the boundary area with respect to the preliminary inspection area.

In an embodiment, the gray level profile can be created in three dimensions. Here, the gray level profile may include a 3D image formed by raising a gray level for each corresponding position of the preliminary inspection area as a height.

In an embodiment, the inspection map can be formed by connecting coordinates corresponding to pixels deviating from a threshold on the gray level profile with lines.

On the other hand, in order to achieve the object of the present invention, the inspection area setting method according to another embodiment of the present invention, the step of obtaining the design data for the preliminary inspection area divided into a plurality of sub-regions, and on the design data Obtaining boundary coordinates for the sub-regions, creating an inspection map for the preliminary inspection region using the boundary coordinates, and selecting an inspection region on the inspection map.

In an embodiment, the inspection map may include an image formed by a line connecting the boundary coordinates.

According to the present invention described above, since the inspection area can be easily and automatically set, the time required for setting the inspection area can be shortened, and accuracy and reliability can be improved. In addition, as the inspection area is set correctly, the accuracy and reliability of defect inspection can be improved. It is also possible to automatically set the inspection area in the inspection apparatus.

Hereinafter, an inspection area setting method according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing the embodiments of the present invention, the embodiments of the present invention may be embodied in various forms and It should not be construed as limited to the embodiments described.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

1 is a block diagram illustrating an example of an inspection apparatus according to an exemplary embodiment of the present disclosure, and FIG. 2 is a plan view briefly illustrating an example of a semiconductor substrate on which a pattern to be inspected is formed.

Hereinafter, an inspection apparatus according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2. In the present invention, an inspection apparatus for detecting a defect on the pattern on the semiconductor substrate on which the pattern is formed will be described as an example.

The inspection apparatus includes a chuck 10 for supporting the semiconductor substrate 1 to be inspected, a detector 20 for detecting information for setting an inspection region on the semiconductor substrate 1 supported by the chuck 10, And a setting unit 30 for setting an inspection area by using the information obtained from the detection unit 20.

For example, the semiconductor substrate 1 may include a semiconductor substrate on which a pattern is formed. Meanwhile, the semiconductor substrate 1 is not limited to a semiconductor substrate, and may be substantially various substrates including an LCD substrate.

The detection unit 20 may obtain an image of the inspection area on the semiconductor substrate 1 by irradiating light onto the semiconductor substrate 1. For example, the detector 20 may include a light emitter 22 for irradiating light onto the semiconductor substrate 1 and a light receiver 21 for detecting light reflected from the semiconductor substrate 1. .

As shown in FIG. 2 and FIG. A plurality of microstructures are formed on the semiconductor substrate 1. Specifically, it includes a cell area 110 that functions as a circuit and a peripheral area 120. The cell region 110 may include a plurality of unit cells 111 and a first boundary region 112 between the unit cells 111. In addition, the peripheral area 120 may include a pad area in which structures for applying a voltage to the cell area 110 are formed, and a replacement of the defective cell when a defective cell occurs in the cell area. It may include a fuse area in which structures such as a redundancy cell and an extra dummy cell are formed. In addition, the pad region and the fuse region are formed around the cell region 110.

For example, in the cell region 110, a plurality of unit cells 111 are spaced at the same interval to form a repeating pattern.

Hereinafter, a method of setting the cell region 110 as an inspection region for defect inspection will be described in detail.

In particular, in the present embodiment, an image is obtained by irradiating light onto the semiconductor substrate 1, a gray level profile is created on the obtained image information, and inspection is performed by using characteristics of an inspection area on the gray level profile. Setting the inspection area by creating the inspection map 400 for the area will be described.

Referring to FIG. 4, first, a semiconductor substrate 1 having a pattern to be inspected is formed. Microstructures formed by a series of semiconductor manufacturing processes are formed on the semiconductor substrate 1, and the microstructures include a cell region 110, a first boundary region 112, and a peripheral region 120. Repeating patterns can be formed.

Light is irradiated onto the semiconductor substrate 1, and light reflected from the semiconductor substrate 1 is detected (S1).

An image of the semiconductor substrate 1 may be obtained through the substrate scanning step S1. Here, the obtained image includes a plurality of pixels, each of which has gray level information. For example, the gray level may have a gray level value having a value between 0 and 225. That is, an image may be acquired using information such as the number of pixels, the size of each pixel, and the gray level of each pixel.

In particular, the image sufficiently includes the cell region 110 to be inspected on the semiconductor substrate, and it is preferable to acquire an image from an area wider than the cell region 110 to be inspected.

For example, the image may be obtained by using a kind of sensor array. Here, the optical sensor array has a lower resolution than a conventional scanning electron microscope (SEM), but has an advantage of obtaining an image in a short time compared to the SEM. That is, the image may be sufficient to have a resolution sufficient to obtain boundary information about the cell region 110 and the like.

In particular, the entire image consists of a plurality of pixels, each of which has its own gray level. In this case, the gray level of each pixel plays an important role in setting up the inspection area later, which will be described later.

The preliminary inspection area 100 for setting the inspection area is set using the image.

For example, as illustrated in FIG. 3, the preliminary inspection region 100 may be a portion of a pattern formed on the semiconductor substrate 1. Here, since the preliminary inspection region 100 forms a pattern in which a predetermined region is repeated, only a portion of the pattern can be inspected by setting the preliminary inspection region, thereby reducing the time for setting the region. have. Meanwhile, the preliminary inspection region 100 may be an entire pattern formed on the semiconductor substrate 1.

A gray level profile for the set preliminary inspection area 100 is created from the obtained image (S2).

For example, as shown in FIGS. 5A and 5B, the gray level profile 200 shows a change in gray level along one direction axis (eg, x-axis or y-axis on the image) on the image. It may include a graph shown.

Here, in the case of creating the two-dimensional gray level profile 200, the x-axis and the y-axis should be created respectively.

Alternatively, as shown in FIG. 7, the gray level profile 300 may include a three-dimensional image 300 expressing a gray level of a corresponding position as a height on the image.

A predetermined threshold H is applied in the 3D gray level profile 300 to detect a position outside the threshold H (S3).

For example, as shown in FIG. 5A, it may be seen that the gray level values of the cell region 110 and the first boundary region 112 are different from each other in the 2D gray level profile 200. In addition, a predetermined threshold H may be applied on the two-dimensional gray level profile 200 to distinguish pixels having different gray level values.

The inspection map 400 may be generated by connecting the positions detected in the threshold value H application step S3 by a line (S4).

For example, as shown in FIG. 5B, when a predetermined threshold H is applied on the two-dimensional gray level profile 200, coordinates of points P1 and P2 which are positions out of the threshold H may be detected. In addition, P1 and P2 may be connected in a line. Similarly, coordinates of a plurality of points corresponding to a position outside the threshold H on the 2D gray level profile 200 may be detected, and the detected points may be connected in a line. Here, in the inspection map 400 connecting coordinates detected on one two-dimensional gray level profile 200, the cell region 110 and the first boundary region 112 for the corresponding direction may be represented. Therefore, in order to prepare the inspection map 400 for the preliminary inspection area 100, a gray level profile 200 is created for both the x-axis and the y-axis, and a threshold value on each gray level profile 200 is generated. H) can be applied to detect the out of position. Here, the threshold value H applied to each gray level profile 200 preferably uses the same value.

On the other hand, as shown in Figure 7, in the three-dimensional gray level profile 300, as in the two-dimensional gray level profile 200, by applying a predetermined threshold (H) coordinates of the position outside the threshold (H) The detection map 400 may be generated by connecting the detected positions with lines. However, the three-dimensional gray level profile 300, as shown in the figure, since the parts corresponding to the cell region 110 and the first boundary region 120 can be easily distinguished with the naked eye, the threshold value ( The step of applying H) may be omitted. For example, on the three-dimensional gray level profile 300 illustrated in FIG. 7, the high height is the first boundary region 112, and the low height can be easily identified as the cell region 110. The inspection map 400 may be created on the image information.

The inspection map 400 is an image in which boundaries of inspection regions for inspecting defects are represented by lines, for example, an inspection region 411 corresponding to the cell region 110, and each inspection region 411. ) May include a second boundary region 412. The selected area on the inspection map 400 may be set as an inspection area, and a subsequent inspection process is performed on the set inspection area.

Meanwhile, in the above-described embodiments, image information is obtained from a pattern to create an inspection map 400 for setting an inspection region, a gray level profile is created from the image, and the cell region 110 is formed on the gray level profile. ) And coordinate information about the inspection area such as the first boundary area 112. However, given the design data 25 for the pattern (S11), boundary coordinates for the cell region 110 and the first boundary region 112 for the preliminary inspection region can be obtained from the design data 25. There will be (S12). Accordingly, the inspection map 400 may be directly generated using the boundary coordinates obtained from the design data 25 (S13), and a subsequent inspection process may be performed on the selected area on the created inspection map 400. There will be.

As described above, the inspection region setting method according to the preferred embodiment of the present invention can easily set the inspection region for defect inspection, and improve the accuracy of defect inspection by setting the inspection region accurately. In addition, since the inspection region can be automatically set in the inspection apparatus, the inspection region can be always set with uniform accuracy, and the time required for setting the inspection region can be shortened.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (8)

Obtaining an image of the preliminary inspection area on the substrate on which the circuit pattern is formed; Creating a gray level profile for the preliminary inspection area from the image; Obtaining coordinates corresponding to pixels deviating from a predetermined threshold on the gray level profile; Forming an inspection map for the preliminary inspection region using the coordinates; And And selecting an inspection region from the inspection map. The method of claim 1, wherein the gray level profile is created in two dimensions. The inspection area of claim 2, wherein the preliminary inspection area includes a plurality of sub-regions, and the gray level profile is formed by a change of gray levels with respect to the sub-region and a boundary area with respect to the preliminary inspection area. How to set up. The method of claim 1, wherein the gray level profile is created in three dimensions. The method of claim 4, wherein the gray level profile comprises a three-dimensional image formed by raising a gray level for each corresponding position of the preliminary inspection area as a height. The method of claim 1, wherein the inspection map is formed by connecting, in a line, coordinates corresponding to pixels deviating from a threshold on the gray level profile. Acquiring design data for a preliminary inspection area divided into a plurality of sub areas; Obtaining boundary coordinates for the sub-regions on the design data; Creating an inspection map for the preliminary inspection region using the boundary coordinates; And And selecting an inspection area on the inspection map. The method of claim 7, wherein the inspection map comprises an image formed by a line connecting the boundary coordinates.

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