KR102583036B1 - Method of inspecting a substrate - Google Patents

Abstract

A substrate inspection method is disclosed. The method includes obtaining an inspection image from a substrate on which circuit patterns are formed, detecting at least one defect candidate area by comparing a reference image and an inspection image, and analyzing an analysis area including a portion of the defect candidate area. It includes calculating a standard deviation and comparing the standard deviation with a preset value to determine whether the defect candidate area is a defect.

Description

Method of inspecting a substrate}

Embodiments of the present invention relate to a method of inspecting a substrate. More specifically, it relates to a substrate inspection method for detecting defects on a substrate on which circuit patterns are formed.

In general, an inspection process for a substrate on which circuit patterns are formed, such as a semiconductor wafer, glass substrate, printed circuit board, etc., may be performed to detect defects such as opens, shorts, scratches, foreign substances, etc. from the substrate. For example, an inspection image obtained from the substrate can be compared to a reference image, through which defects on the substrate can be detected.

The reference image may be obtained from the substrate, or alternatively, may be prepared using design data of the circuit patterns. The defects may be detected through gray level differences between pixels of the inspection image and the reference image.

However, in the case of marginal defects in which the gray level difference between the defects and the background image of the substrate is relatively small, detection is very difficult only by comparing the inspection image and the reference image as described above. For example, when the gray level difference between the defects and the background image of the substrate is approximately 10 or less, there is a problem in that normal areas are detected as defects.

Republic of Korea Patent Publication No. 10-2006-0128277 (December 14, 2006) Republic of Korea Patent Publication No. 10-2011-0020437 (2011.03.03)

The purpose of embodiments of the present invention is to provide a substrate inspection method that can easily detect limited defects in which the gray level difference between defects on a substrate and a background image of the substrate is relatively small.

A substrate inspection method according to an aspect of the present invention for achieving the above object includes obtaining an inspection image from a substrate on which circuit patterns are formed, and detecting at least one defect candidate area by comparing the reference image and the inspection image. It may include calculating a standard deviation for an analysis area including a portion of the defect candidate area, and comparing the standard deviation with a preset value to determine whether the defect candidate area is a defect. .

According to embodiments of the present invention, detecting the defect candidate area includes obtaining a binary image from the inspection image using a preset threshold, and comparing the binary image with the reference image to determine the defect. It may include detecting a candidate region.

According to embodiments of the present invention, the analysis area may include a portion of the outline of the defect candidate area.

According to embodiments of the present invention, calculating the standard deviation includes detecting an outline of the defect candidate area, detecting feature points on the outline, and selecting one of the feature points. It may include designating an analysis area and calculating the standard deviation for the gray levels of pixels in the analysis area.

According to embodiments of the present invention, the selected feature point may be located at the outermost part of the defect candidate area in the X-axis direction or the Y-axis direction.

According to embodiments of the present invention, the analysis area may include a portion of a circuit pattern to which the selected feature point among the circuit patterns belongs.

According to embodiments of the present invention, the substrate inspection method may further include designating a region of interest to include the selected feature point, and a circuit pattern to which the selected feature point belongs among circuit patterns in the region of interest. At least a portion of may be designated as the analysis area.

A substrate inspection method according to another aspect of the present invention for achieving the above object includes obtaining an inspection image from a substrate on which circuit patterns are formed, and obtaining a first binary image from the inspection image using a preset threshold. Comparing the first binary image with a reference image to obtain a second binary image including at least one defect candidate area, the inspection to correspond to at least a portion of the defect candidate area of the second binary image Specifying an analysis area in an image, calculating a standard deviation for the gray levels of pixels in the analysis area, and comparing the standard deviation with a preset value to determine whether the defect candidate area is a defect. It may include steps.

According to embodiments of the present invention, the reference image may be prepared using design data of the circuit patterns.

According to embodiments of the present invention, a part of the defect candidate area may include a part of the outline of the defect candidate area.

According to embodiments of the present invention, the step of designating the analysis area includes detecting a contour of the defect candidate area, detecting feature points on the outline, and selecting one of the feature points of interest. It may include designating an area and designating the analysis area to include a point corresponding to the selected feature point within a partial area of the inspection image corresponding to the area of interest of the second binary image.

According to embodiments of the present invention, the selected feature point may be located at the outermost part of the defect candidate area in the X-axis direction or the Y-axis direction.

According to embodiments of the present invention, the analysis area may include at least a portion of the circuit pattern to which the point belongs among the circuit patterns.

According to embodiments of the present invention, when a plurality of defect candidate areas are detected, a step of removing defect candidate areas smaller than a preset size may be further performed, and in this case, the defect candidate area having a relatively small size may be further performed. Before and after removal, a step of assigning numbers to the detected defect candidate areas and a step of assigning numbers to the remaining defect candidate regions among the detected defect candidate regions may be further performed, respectively. .

According to the embodiments of the present invention as described above, an inspection image obtained from a substrate on which circuit patterns are formed may be compared with a reference image, and thereby at least one defect candidate area may be detected. A part of the defect candidate area of the inspection image and a part of the circuit pattern adjacent thereto may be designated as an analysis area, a standard deviation of the analysis area may be calculated, and the standard deviation may be compared with a preset value to determine the defect candidate area. You can determine whether this is a defect or not.

As described above, the gray level scatter diagram of the analysis area can be confirmed by calculating the standard deviation of the analysis area including a part of the defect candidate area and a part of the circuit pattern adjacent thereto, and through this, a defect is determined for the defect candidate area. Because this is achieved, defects on the substrate can be detected more easily and accurately. As a result, reliability in the inspection process for defects on the substrate can be greatly improved.

1 is a flowchart for explaining a substrate inspection method according to an embodiment of the present invention.
FIG. 2 is a flowchart for explaining the step of detecting the defect candidate area shown in FIG. 1.
FIG. 3 is a flowchart for explaining the steps of designating an analysis area shown in FIG. 1.
Figure 4 is a schematic diagram illustrating an inspection image obtained from a substrate on which circuit patterns are formed.
FIG. 5 is a schematic diagram illustrating a first binary image obtained from the inspection image shown in FIG. 4.
Figure 6 is a schematic diagram for explaining a reference image.
FIG. 7 is a schematic diagram illustrating a second binary image including defect candidate areas.
FIG. 8 is a schematic diagram illustrating numbers assigned to the defect candidate areas shown in FIG. 7 .
FIG. 9 is a schematic diagram illustrating a second binary image in which relatively small defect candidate areas have been removed.
Figure 10 is a schematic diagram to explain the state in which numbers are assigned to the remaining defect candidate areas.
Figure 11 is a schematic diagram for explaining the outline and feature points of a defect candidate area.
FIG. 12 is a schematic diagram for explaining a feature point selected from among the feature points shown in FIG. 11.
FIG. 13 is a schematic diagram illustrating a region of interest including a feature point selected in FIG. 12.
Figures 14 and 15 are schematic diagrams for explaining the analysis area designated in the inspection image.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention does not have to be configured as limited to the embodiments described below and may be embodied in various other forms. The following examples are not provided to fully complete the present invention, but rather are provided to fully convey the scope of the present invention to those skilled in the art.

In embodiments of the present invention, when one element is described as being disposed or connected to another element, the element may be directly disposed or connected to the other element, and other elements may be interposed between them. It could be. Alternatively, if one element is described as being placed directly on or connected to another element, there cannot be another element between them. The terms first, second, third, etc. may be used to describe various items such as various elements, compositions, regions, layers and/or parts, but the items are not limited by these terms. won't

Technical terms used in the embodiments of the present invention are merely used for the purpose of describing specific embodiments and are not intended to limit the present invention. Additionally, unless otherwise limited, all terms, including technical and scientific terms, have the same meaning that can be understood by a person skilled in the art. The above terms, as defined in common dictionaries, will be construed to have meanings consistent with their meanings in the context of the relevant art and description of the invention, and unless explicitly defined, ideally or excessively by superficial intuition. It will not be interpreted.

Embodiments of the invention are described with reference to schematic illustrations of ideal embodiments of the invention. Accordingly, changes from the shapes of the illustrations, for example changes in manufacturing methods and/or tolerances, are fully to be expected. Accordingly, the embodiments of the present invention are not intended to be described as limited to the specific shapes of the regions illustrated but are intended to include deviations in the shapes, and the elements depicted in the drawings are entirely schematic and represent their shapes. is not intended to describe the exact shape of the elements nor is it intended to limit the scope of the present invention.

FIG. 1 is a flowchart for explaining a substrate inspection method according to an embodiment of the present invention, FIG. 2 is a flowchart for explaining steps for detecting a defect candidate area shown in FIG. 1 , and FIG. 3 is shown in FIG. 1 This is a flowchart to explain the steps for specifying an analysis area.

The substrate inspection method according to an embodiment of the present invention can be used to detect defects such as opens, shorts, scratches, foreign substances, etc. on substrates such as semiconductor wafers, display substrates, printed circuit boards, etc. on which circuit patterns are formed.

FIG. 4 is a schematic diagram for explaining an inspection image obtained from a substrate on which circuit patterns are formed, FIG. 5 is a schematic diagram for explaining a first binary image obtained from the inspection image shown in FIG. 4, and FIG. 6 is a reference image. This is a schematic diagram for explanation.

Referring to FIGS. 1 to 6, first, in step S100, an inspection image 10 as shown in FIG. 4 is obtained from the substrate. The inspection image 10 may be acquired using an inspection camera placed on top of the substrate.

The inspection image 10 may be compared with the reference image 20 as shown in FIG. 6 in step S110, and through this, at least one defect candidate area may be detected.

According to one embodiment of the present invention, the defect candidate area may be detected through binarization processing of the inspection image 10. Referring to FIG. 2, the inspection image 10 can be binarized using a preset threshold in step S112, and through this, the first binary image 12 as shown in FIG. 5 can be obtained. At this time, the threshold value is preferably set to have sufficient margin to prevent defects on the substrate from being missed.

The first binary image 12 may be compared with the reference image 20 in step S114, and through this, a second binary image 14 including at least one defect candidate area may be obtained. In particular, since the threshold is set to have sufficient margin in step S112, more defect candidate areas than defects actually existing on the substrate may be detected in step S114. Subsequently, a blob labeling operation that assigns numbers to the detected defect candidate areas may be performed in step S115.

FIG. 7 is a schematic diagram illustrating a second binary image including defect candidate areas, and FIG. 8 is a schematic diagram illustrating a state in which numbers are assigned to the defect candidate regions shown in FIG. 7 .

Meanwhile, the reference image 20 may be prepared in advance using design data of the circuit patterns.

According to an embodiment of the present invention, when a plurality of defect candidate areas are detected as described above, the defect candidate areas having a relatively small size can be removed to shorten the inspection time. For example, defect candidate areas smaller than the preset size may be removed in step S117, and new numbers may be assigned to the remaining defect candidate areas in step S118.

FIG. 9 is a schematic diagram illustrating a second binary image in which relatively small-sized defect candidate regions have been removed, and FIG. 10 is a schematic diagram illustrating a state in which numbers are assigned to the remaining defect candidate regions.

After the defect candidate area is detected as described above, the standard deviation can be detected for the analysis area including a part of the defect candidate area. At this time, the analysis area may include a portion of the outline of the defect candidate area.

According to one embodiment of the present invention, as shown in FIG. 1, in step S120, an analysis area is designated in the inspection image 10 to correspond to at least a portion of the defect candidate area of the second binary image 14, and , In step S130, the standard deviation can be calculated for the gray levels of the pixels in the analysis area.

FIG. 11 is a schematic diagram for explaining the outline and feature points of a defect candidate area, FIG. 12 is a schematic diagram for explaining a feature point selected from among the feature points shown in FIG. 11, and FIG. 13 is a region of interest including the feature point selected in FIG. 12. This is a schematic diagram for explaining, and FIGS. 14 and 15 are schematic diagrams for explaining the analysis area designated in the inspection image.

Referring to Figure 3 and Figures 11 to 14, the outline of the defect candidate area 30 can be detected in step S122, and feature points on the outline can be detected in step S124.

Subsequently, in step S126, the region of interest 34 may be designated to include one 32 selected from among the feature points. At this time, the selected feature point 32 may be located at the outermost part of the defect candidate area 30 in the X-axis direction or the Y-axis direction. Meanwhile, as shown in FIG. 13, two regions of interest 34 may be designated, in which case the feature points included in each region of interest 34 are located in opposite directions in the X-axis direction or the Y-axis direction. can be located

Subsequently, in step S128, the analysis area includes a point corresponding to the selected feature point 32 within a partial region of the inspection image 10 corresponding to the region of interest 34 of the second binary image 14. (42) can be specified.

The analysis area 42 may include a portion of the circuit pattern 50 to which the point corresponding to the selected feature point among the circuit patterns belongs. For example, among the circuit patterns located within the region of interest 34, the circuit pattern 50 to which the point corresponding to the selected feature point 32 belongs may be designated as the analysis region 42. As a result, a part of the defect candidate area 40 of the inspection image corresponding to the defect candidate area 30 of the second binary image 14 and a part of the circuit pattern 50 adjacent thereto are in the analysis area 42. ) can be specified.

Unlike the above, when a plurality of circuit patterns are included in the analysis area 42, the standard deviation of the analysis area 42 can be calculated to be relatively large due to differences in gray levels of the circuit patterns, and thus Errors may occur in subsequent defect determination.

Referring again to FIG. 1, in step S140, it is possible to determine whether the defect candidate area 40 is a defect by comparing the calculated standard deviation with a preset value. The analysis area 42 may include a part of the defect candidate area 40 and a part of the circuit pattern 50 to which the feature point 32 belongs, and the defect candidate area 42 and the circuit pattern ( The standard deviation may be changed by the difference in gray level of 50).

Therefore, if the standard deviation is calculated to be greater than the preset value, it means that the gray level difference between the defect candidate area 40 and the circuit pattern 50 is relatively large, and therefore the defect candidate area 40 is a defect. It can be judged as On the contrary, if the standard deviation is calculated to be smaller than the preset value, it means that the gray level difference between the defect candidate area 40 and the circuit pattern 50 is relatively small, so the defect candidate area 40 is It may be judged not to be a defect.

According to the embodiments of the present invention as described above, the inspection image 10 obtained from the substrate on which the circuit patterns are formed can be compared with the reference image 20, and thereby at least one defect candidate area can be detected. there is. A part of the defect candidate area 40 of the inspection image 10 and a part of the circuit pattern 50 adjacent thereto are designated as the analysis area 42, and the standard deviation of the analysis area 42 can be calculated. , it is possible to determine whether the defect candidate area 40 is a defect by comparing the standard deviation with a preset value.

As described above, the gray level scatter diagram of the analysis area 42 can be confirmed by calculating the standard deviation of the analysis area 42 including a part of the defect candidate area 40 and a part of the circuit pattern 50 adjacent thereto. Through this, defect determination is made for the defect candidate area 40, so defects on the substrate can be detected more easily and accurately. As a result, reliability in the inspection process for defects on the substrate can be greatly improved.

Although the present invention has been described above with reference to preferred embodiments, those skilled in the art may make various modifications and changes to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. You will be able to understand that it exists.

10: Inspection image
12: first binary image
14: second binary image
20: Reference image
30: Defect candidate area of the second binary image
32: Feature point
34: Area of interest
40: Defect candidate area of inspection image
42: analysis area
50: Circuit pattern adjacent to analysis area

Claims (17)

delete delete delete delete delete delete delete Obtaining an inspection image from a substrate on which circuit patterns are formed;
Obtaining a first binary image from the inspection image using a preset threshold;
Comparing the first binary image with a reference image to obtain a second binary image including at least one defect candidate area;
designating an analysis area in the inspection image to correspond to at least a portion of a defect candidate area of the second binary image;
calculating a standard deviation for the gray levels of pixels in the analysis area; and
A substrate inspection method comprising comparing the standard deviation with a preset value to determine whether the defect candidate area is a defect. The method of claim 8, wherein the reference image is prepared using design data of the circuit patterns. The method of claim 8, wherein a portion of the defect candidate region includes a portion of an outline of the defect candidate region. The method of claim 8, wherein the step of designating the analysis area includes:
detecting an outline of the defect candidate area;
detecting feature points on the outline;
designating a region of interest to include one selected from the feature points; and
Specifying the analysis area to include a point corresponding to the selected feature point within a partial area of the inspection image corresponding to the region of interest in the second binary image. The method of claim 11, wherein the selected feature point is located at the outermost part of the defect candidate area in the X-axis direction or the Y-axis direction. The method of claim 11, wherein the analysis area includes at least a portion of a circuit pattern among the circuit patterns to which the point belongs. The method of claim 8, further comprising removing a defect candidate area smaller than a preset size when a plurality of defect candidate areas are detected. The method of claim 14, further comprising assigning numbers to the detected defect candidate areas. The method of claim 14, further comprising assigning numbers to the remaining defect candidate areas among the detected defect candidate areas. The method of claim 8, wherein the defect candidate area is determined to be a defect when the standard deviation is greater than the preset value.

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