KR20080060327A - Method for fabricating plug in semiconductor device - Google Patents

Method for fabricating plug in semiconductor device Download PDF

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Publication number
KR20080060327A
KR20080060327A KR1020060134277A KR20060134277A KR20080060327A KR 20080060327 A KR20080060327 A KR 20080060327A KR 1020060134277 A KR1020060134277 A KR 1020060134277A KR 20060134277 A KR20060134277 A KR 20060134277A KR 20080060327 A KR20080060327 A KR 20080060327A
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South Korea
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plug
semiconductor device
manufacturing
etch back
gas
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KR1020060134277A
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Korean (ko)
Inventor
김석기
최익수
김은미
김래현
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주식회사 하이닉스반도체
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Priority to KR1020060134277A priority Critical patent/KR20080060327A/en
Publication of KR20080060327A publication Critical patent/KR20080060327A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method for manufacturing a plug of a semiconductor device is provided to prevent defects of a self aligned process by removing a step caused by a seam through a double etch-back process. An interlayer dielectric(37) is formed on a substrate(31). A contact hole is formed by etching the interlayer dielectric. A plug conductive layer for filling up the contact hole is formed on the entire surface of the substrate. A step is removed by performing a first etch-back. A second etch-back is performed to the plug conductive layer. A plug which is buried into the contact hole is formed by flattening the plug conductive layer processed with the second etch-back.

Description

반도체 소자의 플러그 제조 방법{METHOD FOR FABRICATING PLUG IN SEMICONDUCTOR DEVICE}Method for manufacturing plug of semiconductor device {METHOD FOR FABRICATING PLUG IN SEMICONDUCTOR DEVICE}

도 1a은 종래 기술에 따른 반도체 소자의 랜딩플러그 제조 방법을 간략히 도시한 도면.Figure 1a is a simplified view showing a landing plug manufacturing method of a semiconductor device according to the prior art.

도 1b는 랜딩플러그가 형성된 상태의 평면도.Figure 1b is a plan view of the landing plug is formed.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 플러그 제조 방법을 도시한 공정 단면도.2A to 2C are cross-sectional views illustrating a method of manufacturing a plug according to an exemplary embodiment of the present invention.

도 3a 내지 도 3c는 본 발명의 실시예에 따른 반도체 소자의 랜딩플러그 제조 방법을 도시한 공정단면도.3A to 3C are cross-sectional views illustrating a method of manufacturing a landing plug of a semiconductor device according to an exemplary embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

31 : 기판 32 : 소자분리막31 substrate 32 device isolation film

33 : 게이트 절연막 34 : 게이트 전도막33: gate insulating film 34: gate conductive film

35 : 게이트 하드마스크 36 : 게이트스페이서35: gate hard mask 36: gate spacer

37 : 층간절연막 38 : 폴리실리콘막37: interlayer insulating film 38: polysilicon film

38B, 38C : 랜딩플러그38B, 38C: Landing Plug

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자의 플러그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a plug of a semiconductor device.

반도체 소자의 고집적화에 따라 비트라인 또는 캐패시터의 스토리지노드콘택플러그 공정시 충분한 공정 마진(Margin)을 확보하기 위해, 콘택 공정 전에 랜딩 플러그(Landing Plug) 공정을 실시하고 있다.In order to secure sufficient process margin during the storage node contact plug process of the bit line or capacitor according to the high integration of semiconductor devices, a landing plug process is performed before the contact process.

도 1a은 종래 기술에 따른 반도체 소자의 랜딩플러그 제조 방법을 간략히 도시한 도면이고, 도 1b는 랜딩플러그가 형성된 상태의 평면도이다.1A is a view schematically illustrating a method for manufacturing a landing plug of a semiconductor device according to the related art, and FIG. 1B is a plan view of a state in which a landing plug is formed.

도 1a에 도시된 바와 같이, 소자분리막(12)이 형성된 기판(11) 상에 게이트 절연막(13), 게이트 전도막(14) 및 게이트 하드마스크(15)가 적층된 게이트 라인(G)을 형성한다. 도시하지 않았지만, 게이트라인의 측벽에 게이트스페이서가 형성될 수 있다.As shown in FIG. 1A, a gate line G on which a gate insulating layer 13, a gate conductive layer 14, and a gate hard mask 15 are stacked is formed on a substrate 11 on which an isolation layer 12 is formed. do. Although not shown, a gate spacer may be formed on the sidewall of the gate line.

이어서, 게이트 라인(G)이 형성된 기판(11)의 전면에 층간절연막(16)을 증착하고 게이트 라인의 게이트 하드마스크(15)가 드러나는 타겟으로 평탄화한 다음, 랜딩플러그콘택(Landing Plug Contact) 식각 공정을 실시하여 콘택홀을 형성한다.Subsequently, the interlayer insulating layer 16 is deposited on the entire surface of the substrate 11 on which the gate line G is formed, and the planarization is performed by planarizing the target with the gate hard mask 15 of the gate line exposed, and then etching the landing plug contact. The process is performed to form contact holes.

이어서, 기판(11)의 전면에 폴리실리콘막을 증착하여 콘택홀을 매립한 후, 에치백(Etch back) 공정 및 화학적기계적연마(Chemical Mechanical Polishing; CMP)를 순차적으로 진행하여 즉, 플러그분리공정을 수행하여 로 분리되는 랜딩플러 그(17A, 17B)를 형성한다. Subsequently, the contact hole is filled by depositing a polysilicon film on the entire surface of the substrate 11, and then an etch back process and a chemical mechanical polishing (CMP) are sequentially performed, that is, a plug separation process is performed. To form landing plugs 17A and 17B that are separated by.

도 1b를 살펴보면, 소자분리막(12)에 의해 정의된 활성영역(A) 상부에 복수의 게이트라인(G)이 형성되며, 게이트라인(G) 사이의 활성영역(A) 상에는 랜딩플러그(17A, 17B)가 형성되어 있다. 여기서, 활성영역(A)은 비트라인콘택노드(BLC) 지역과 스토리지노드콘택노드(SNC) 지역으로 구분되고, 랜딩플러그 중 하나(17A)는 비트라인콘택노드(BLC) 지역에 연결되고, 다른 하나(17B)는 스토리지노드콘택노드(SNC) 지역에 연결된다.Referring to FIG. 1B, a plurality of gate lines G are formed on the active region A defined by the device isolation layer 12, and the landing plugs 17A, are formed on the active region A between the gate lines G. Referring to FIG. 17B) is formed. Here, the active area A is divided into a bit line contact node (BLC) region and a storage node contact node (SNC) region, and one of the landing plugs 17A is connected to the bit line contact node (BLC) region and the other. One 17B is connected to a storage node contact node (SNC) region.

그러나, 상술한 종래 기술은 랜딩플러그(17A, 17B) 형성을 위해 폴리실리콘막을 증착할 때 유발되는 균열(seam)로 인해 후속 에치백공정을 진행할 때, 균열이 더욱 심화되는 현상이 발생한다.However, in the above-described prior art, when the subsequent etch back process is performed due to a crack caused when the polysilicon film is deposited to form the landing plugs 17A and 17B, the crack is further intensified.

특히, 이러한 균열은 콘택홀의 오픈면적이 큰 비트라인콘택노드(BLC) 지역에서 에치백공정시 더욱 아래로 꺼지게 되어 심한 단차를 유발시킨다. 도 1b를 보면, 비트라인콘택노드지역에 형성되는 랜딩플러그(17A)가 스토리지노드콘택노드지역에 형성되는 랜딩플러그(17B)보다 더 크게 형성되고 있으므로, 비트라인콘택노드지역에 형성되는 콘택홀은 더욱 큰 오픈면적을 갖는다.In particular, these cracks are turned down further during the etch back process in the bit line contact node (BLC) area where the contact hole has a large open area, causing a severe step. 1B, since the landing plug 17A formed in the bit line contact node region is formed larger than the landing plug 17B formed in the storage node contact node region, the contact hole formed in the bit line contact node region is formed. It has a larger open area.

이렇게 형성된 균열에 의한 단차는 후속 화학적기계적연마(CMP) 공정을 진행하는 과정중에 생성되는 각종 파티클결함(Particle defect, 도 1a의 도면부호 'D' 참조)들이 제거되지 않고 균열에 의한 단차 내부에 남아있게 만들고, 랜딩플러그 공정이 완료된 후 잔류하는 파티클결함들은 자기정렬콘택공정(Self Aligned Contact; SAC)의 페일(Fail)로 작용하게 되어 수율을 저하시키게 된다.The step caused by the cracks thus formed remains inside the step due to cracks without removing various particle defects (Particle defect (see 'D' in FIG. 1A)) generated during the subsequent chemical mechanical polishing (CMP) process. Particle defects remaining after the landing plug process is completed will act as a fail of the Self Aligned Contact (SAC), thereby lowering the yield.

위와 같은 문제점들은 랜딩플러그 공정은 물론 콘택홀 내부에 플러그를 매립시키는 반도체소자의 모든 공정에서 발생할 수 있다.The above problems may occur in all processes of a semiconductor device that embeds a plug inside a contact hole as well as a landing plug process.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 플러그 분리 공정을 수행하면서 동시에 균열(Seam)에 의한 단차를 제거하는데 적합한 반도체 소자의 플러그 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a plug of a semiconductor device suitable for removing a step caused by a crack while performing a plug separation process.

상기 목적을 달성하기 위한 본 발명의 반도체 소자의 플러그 제조 방법은 기판 상에 층간절연막을 형성하는 단계; 상기 층간절연막을 식각하여 콘택홀을 형성하는 단계; 상기 기판의 전면에 상기 콘택홀을 매립하는 플러그도전층을 형성하는 단계; 1차 에치백을 수행하여 상기 플러그도전층 형성시 발생된 균열에 의한 단차를 제거하는 단계; 상기 단차가 제거된 플러그도전층에 대해 2차 에치백을 진행하는 단계; 및 상기 2차 에치백이 진행된 플러그도전층을 평탄화하여 상기 콘택홀에 매립된 플러그를 형성하는 단계를 포함하는 것을 특징으로 한다.A plug manufacturing method of a semiconductor device of the present invention for achieving the above object comprises the steps of forming an interlayer insulating film on a substrate; Etching the interlayer insulating layer to form a contact hole; Forming a plug conductive layer filling the contact hole on the front surface of the substrate; Performing a first etch back to remove the step caused by the crack generated when the plug conductive layer is formed; Performing a second etch back on the plug conductive layer from which the step is removed; And forming a plug embedded in the contact hole by planarizing the plug conductive layer on which the secondary etchback has been progressed.

바람직하게, 상기 플러그도전층은 폴리실리콘막으로 형성하는 것을 특징으로 하며, 상기 1차 에치백은 ECR 형태의 플라즈마소스에서 진행하고, 상기 2차 에치백은 TCP 형태의 플라즈마소스에서 진행하는 것을 특징으로 하며, 상기 1차 에치백은 불소계 가스와 산소(O2) 가스의 혼합가스를 사용하여 진행하고, 상기 2차 에치백은 Cl2 가스와 HBr 가스를 혼합하여 진행하는 것을 특징으로 한다.Preferably, the plug conductive layer is formed of a polysilicon film, wherein the primary etch back is carried out in the plasma source of the ECR type, the secondary etch back is characterized in that it proceeds in the plasma source of TCP type The primary etchback is performed by using a mixed gas of fluorine-based gas and oxygen (O 2 ) gas, and the secondary etchback is characterized by advancing by mixing Cl 2 gas and HBr gas.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

도 2a 내지 도 2c는 본 발명의 실시예에 따른 플러그 제조 방법을 도시한 공정 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a plug according to an exemplary embodiment of the present invention.

도 2a에 도시된 바와 같이, 기판(21) 상에 층간절연막(22)을 형성한 후, 층간절연막(22)을 식각하여 콘택홀(23)을 형성한다.As shown in FIG. 2A, after forming the interlayer insulating film 22 on the substrate 21, the interlayer insulating film 22 is etched to form the contact hole 23.

이어서, 콘택홀(23)을 내부를 채울때까지 전면에 플러그도전층(24)을 증착한다. 이때, 플러그도전층(24)은 폴리실리콘막, 텅스텐막이 적용가능하고, 콘택홀(23)의 오픈 면적에 의해 균열(S)이 발생될 수 있다.Subsequently, the plug conductive layer 24 is deposited on the entire surface until the contact hole 23 is filled. In this case, the plug conductive layer 24 may be a polysilicon film or a tungsten film, and a crack S may be generated by the open area of the contact hole 23.

도 2b에 도시된 바와 같이, 플러그도전층(24)을 건식 에치백(Dry etch back)한다. 이때, 건식에치백은 2스텝으로 진행하는데 첫번째 스텝은 ECR(Electron Cyclotron Rresonance) 형태의 플라즈마소스에서 에치백하고, 두번째 스텝은 TCP(Transformer Coupled Plasma) 형태의 플라즈마소스에서 에치백한다.As shown in FIG. 2B, the plug conductive layer 24 is dry etched back. At this time, the dry etch back is performed in two steps. The first step is etched back from the ECR (Electron Cyclotron Rresonance) type plasma source, and the second step is etched back from the TCP (Transformer Coupled Plasma) type plasma source.

이하, 플러그도전층(24)이 폴리실리콘막인 경우로 가정하여 설명한다.Hereinafter, it is assumed that the plug conductive layer 24 is a polysilicon film.

첫번째 스텝은, SF6와 CHF3 가스의 혼합가스와 같은 불소계 가스(F base gas)를 이용하여 측면(Lateral) 방향으로 건식에치백을 유도하여 플러그도전층(24) 의 상부에 발생된 균열(S)을 제거하면서 에치백이 진행되도록 한다. 이로써, 첫번째 스텝은 층간절연막(22)의 표면 상부에서 플러그도전층(24A)이 일정 두께(D1)가 잔류할때까지 진행한다. 예를 들어, 두께 'D1'은 300∼400Å 타겟이며, 이러한 타겟은 균열(S)에 의한 단차를 제거할 수 있는 충분한 식각타겟이다. 한편, 첫번째 스텝에 의해 단차를 제거되지만 균열(S1)은 일부 잔류할 수 있다.The first step is to use a fluorine-based gas (F base gas) such as a mixture of SF 6 and CHF 3 gas to induce a dry etch back in the direction of the side (Lateral) to cause cracks generated on the top of the plug conductive layer 24 ( Allow the etchback to proceed while removing S). Thus, the first step proceeds until the plug conductive layer 24A remains on the surface of the interlayer insulating film 22 until the predetermined thickness D1 remains. For example, the thickness 'D1' is a 300 to 400 GPa target, and this target is a sufficient etching target to remove the step caused by the crack S. On the other hand, although the step is removed by the first step, some cracks S1 may remain.

이어서, 두번째 스텝을 진행한다. 도 2c에 도시된 바와 같이, 두번째 스텝은 Cl2 또는 HBr 가스를 베이스로 이용하여 건식에치백을 진행한다. 이처럼, 두번째 스텝을 진행하면 첫번째 스텝후 잔류하던 균열(S1)은 더이상 존재하지 않아 단차없이 에치백이 완료되어 플러그(24B)가 형성된다.Then proceed to the second step. As shown in FIG. 2C, the second step is a dry etch back using Cl 2 or HBr gas as a base. As such, when the second step proceeds, the crack S1 remaining after the first step no longer exists, so that the etch back is completed without a step, thereby forming the plug 24B.

바람직하게, 첫번째 스텝은 SF6와 CHF3 가스를 주식각가스로 이용하면서, O2 가스를 첨가한다. SF6 가스와 CHF3 가스는 각각 10∼100sccm, O2 가스는 1∼10sccm의 유량을 플로우하고, 바텀파워(Bottom power)는 50∼400Ｗ를 인가하며, 압력은 3∼50mT의 조건에서 진행한다. 이때, CHF3 가스와 SF6는 9:1의 비율을 가지도록 유량을 조절하는데, 이처럼 CHF3 가스와 SF6 가스의 유량비율을 9:1로 조절하면, 측면방향으로 에치백이 발생하도록 하여 균열에 의한 단차를 제거할 수 있다.Preferably, the first step adds O 2 gas while using SF 6 and CHF 3 gas as stock angle gas. The SF 6 gas and the CHF 3 gas flow 10 to 100 sccm, the O 2 gas to 1 to 10 sccm, respectively, and the bottom power is 50 to 400 kPa, and the pressure is 3 to 50 mT. . In this case, CHF 3 gas and SF 6 is 9: to adjust the flow rate so as to have a ratio of 1: 1, thus the flow rate ratio of CHF 3 gas and SF 6 gas 9: Adjust to 1, the crack so as to generate an etch-back in the lateral direction Step by step can be eliminated.

두번째스텝은, TCP(Transfomer Coupled Plasma) 형태의 플라즈마소스를 이용하는 플라즈마 장비에서 Cl2 가스와 HBr 가스를 혼합하여 에치백한다. In the second step, Cl 2 gas and HBr gas are mixed and etched back in a plasma apparatus using a TCP (Transfomer Coupled Plasma) type plasma source.

도 3a 내지 도 3c는 본 발명의 실시예에 따른 랜딩플러그의 제조 방법을 도 시한 단면도이다.3A to 3C are cross-sectional views illustrating a method of manufacturing a landing plug according to an embodiment of the present invention.

도 3a에 도시된 바와 같이, 소자분리(Isolation) 공정을 실시하여 기판(31)에 소자분리막(32)을 형성하여 활성 영역을 정의한다. 이때, 활성영역은 비트라인콘택노드(BLC) 지역과 스토리지노드콘택노드(SNC) 지역이 정의되고, 채널길이 증가를 위한 리세스채널이 형성될 수 있다.As shown in FIG. 3A, an isolation region 32 is formed on the substrate 31 by performing an isolation process to define an active region. In this case, a bit line contact node (BLC) region and a storage node contact node (SNC) region are defined in the active region, and a recess channel for increasing the channel length may be formed.

이어서, 기판(31) 상에 게이트 절연막(33), 게이트 전도막(34) 및 게이트 하드마스크(35)가 순차적으로 적층된 게이트라인을 형성한다. 게이트라인을 형성한 후 게이트 스페이서 공정을 실시하여 게이트라인의 측벽에 게이트 스페이서(36)를 형성한다. 게이트 스페이서(36)는 통상 질화막 또는 질화막과 산화막의 적층 구조를 사용한다.Subsequently, a gate line in which the gate insulating film 33, the gate conductive film 34, and the gate hard mask 35 are sequentially stacked is formed on the substrate 31. After forming the gate line, a gate spacer process is performed to form the gate spacers 36 on the sidewalls of the gate lines. The gate spacer 36 generally uses a nitride film or a stacked structure of a nitride film and an oxide film.

계속해서, 기판(31)의 전면에 층간절연막(37)을 증착한다. 그리고 나서, 게이트라인의 게이트 하드마스크(35)가 드러나는 타겟으로 평탄화 공정을 실시한다.Subsequently, an interlayer insulating film 37 is deposited on the entire surface of the substrate 31. Then, a planarization process is performed on the target on which the gate hard mask 35 of the gate line is exposed.

이어서, 랜딩플러그콘택 공정을 실시하여 기판(31)의 활성 영역을 노출시키는 콘택홀(도시 생략)을 형성한다. 다음으로, 기판(31)의 전면에 플러그용 폴리실리콘막(38)을 증착하여 콘택홀을 완전히 매립한다. 이때, 비트라인콘택노드(BLC) 지역 상부에서는 스토리지노드콘택노드(SNC) 지역에 비해 콘택홀의 오픈면적이 넓으므로, 폴리실리콘막(38) 증착시 균열(S10)이 발생할 수 있다.Next, a landing plug contact process is performed to form a contact hole (not shown) that exposes the active region of the substrate 31. Next, the plug polysilicon film 38 is deposited on the entire surface of the substrate 31 to completely fill the contact hole. In this case, since the open area of the contact hole is wider than that of the storage node contact node SNC, the crack S10 may occur when the polysilicon layer 38 is deposited.

이어서, 플러그분리공정을 진행한다. 즉, 폴리실리콘막(38)을 건식 에치백(Dry etch back)한다. 2스텝(Two step)으로 나누어 진행한다. Subsequently, the plug separation process is performed. That is, the polysilicon film 38 is dry etched back. Proceed by dividing into two steps.

도 3b에 도시된 바와 같이, 첫번째 스텝은, ECR 형태의 플라즈마소스에서 SF6와 CHF3 가스의 혼합가스와 같은 불소계 가스(F base gas)를 이용하여 측면(Lateral) 방향으로 건식에치백을 유도하여 폴리실리콘막(38)의 상부에 발생된 균열(S)을 제거하면서 에치백이 진행되도록 한다. 이로써, 첫번째 스텝은 게이트라인의 표면 상부에서 폴리실리콘막(38A)이 일정 두께가 잔류할때까지 진행한다. 예를 들어, 잔류하는 두께는은 300∼400Å 타겟이며, 이러한 타겟은 균열(S10)에 의한 단차를 제거할 수 있는 충분한 식각타겟이다. 한편, 첫번째 스텝에 의해 단차를 제거되지만 균열(S11)은 일부 잔류할 수 있다.As shown in FIG. 3B, the first step is to induce dry etch back in the lateral direction by using a fluorine-based gas such as a mixture of SF 6 and CHF 3 gas in an ECR type plasma source. By removing the crack (S) generated on the upper portion of the polysilicon film 38 to proceed the etch back. Thus, the first step proceeds until the polysilicon film 38A remains a certain thickness over the surface of the gate line. For example, the remaining thickness is 300 to 400 Pa target, and this target is a sufficient etching target to remove the step caused by the crack S10. On the other hand, although the step is removed by the first step, some cracks S11 may remain.

이어서, 두번째 스텝을 진행한다. 도 3c에 도시된 바와 같이, 두번째 스텝은 Cl2 또는 HBr 가스를 베이스로 이용하여 건식에치백을 진행한다. 이처럼, 두번째 스텝을 진행하면 첫번째 스텝후 잔류하던 균열(S11)은 더이상 존재하지 않아 단차없이 에치백이 완료된다.Then proceed to the second step. As shown in FIG. 3C, the second step performs a dry etch back using Cl 2 or HBr gas as a base. As such, when the second step proceeds, the crack S11 remaining after the first step no longer exists, and the etch back is completed without a step.

후속 공정으로, 게이트 하드마스크(35)가 드러나는 타겟으로 화학적기계적연마(CMP)를 실시하여 랜딩플러그(38B, 38C)를 형성한다. 그 결과를 살펴보면, 비트라인콘택노드(BLC) 지역에 형성되는 랜딩플러그(38B)와 스토리지노드콘택노드(SNC)지역에 형성되는 랜딩플러그(38C) 모두 균열 및 균열에 의한 단차가 없음을 알 수 있다.In a subsequent process, chemical mechanical polishing (CMP) is performed with the target on which the gate hard mask 35 is exposed to form landing plugs 38B and 38C. As a result, it can be seen that both the landing plug 38B formed in the bit line contact node (BLC) region and the landing plug 38C formed in the storage node contact node (SNC) region have no crack and crack step. have.

바람직하게, 첫번째 스텝은 SF6와 CHF3 가스를 주식각가스로 이용하면서, O2 가스를 첨가한다. SF6 가스와 CHF3 가스는 각각 10∼100sccm, O2 가스는 1∼10sccm의 유량을 플로우하고, 바텀파워(Bottom power)는 50∼400Ｗ를 인가하며, 압력은 3 ∼50mT의 조건에서 진행한다. 이때, CHF3 가스와 SF6는 9:1의 비율을 가지도록 유량을 조절하는데, 이처럼 CHF3 가스와 SF6 가스의 유량비율을 9:1로 조절하면, 측면방향으로 에치백이 발생하도록 하여 균열에 의한 단차를 제거할 수 있다. 또한, ECR 형태의 플라즈마소스를 사용하면 측면방향의 에치백이 더 잘 일어난다.Preferably, the first step adds O 2 gas while using SF 6 and CHF 3 gas as stock angle gas. The SF 6 gas and the CHF 3 gas flow 10 to 100 sccm, the O 2 gas to 1 to 10 sccm, respectively, and the bottom power is 50 to 400 kPa, and the pressure is 3 to 50 mT. . In this case, CHF 3 gas and SF 6 is 9: to adjust the flow rate so as to have a ratio of 1: 1, thus the flow rate ratio of CHF 3 gas and SF 6 gas 9: Adjust to 1, the crack so as to generate an etch-back in the lateral direction Step by step can be eliminated. In addition, the use of ECR-type plasma sources provides better lateral etch back.

두번째스텝은, TCP(Transfomer Coupled Plasma) 형태의 플라즈마소스를 이용하는 플라즈마 장비에서 Cl2 가스와 HBr 가스를 혼합하여 에치백한다. In the second step, Cl 2 gas and HBr gas are mixed and etched back in a plasma apparatus using a TCP (Transfomer Coupled Plasma) type plasma source.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 플러그 분리 공정에서 에치백을 두 번에 나누어 수행하여 균열 및 균열에 의한 단차를 제거하므로써 자기정렬콘택공정의 불량을 방지하여 소자의 자기정렬콘택 수율 향상 및 제조 수율 향상에 기여하는 효과가 있다.The present invention described above is performed by dividing the etch back in two steps in the plug separation process, thereby preventing the defect of the self-aligned contact process by eliminating the step due to the cracks and cracks, thereby contributing to the improvement of the self-aligned contact yield and the manufacturing yield of the device. It works.

Claims (14)

기판 상에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the substrate; 상기 층간절연막을 식각하여 콘택홀을 형성하는 단계;Etching the interlayer insulating layer to form a contact hole; 상기 기판의 전면에 상기 콘택홀을 매립하는 플러그도전층을 형성하는 단계;Forming a plug conductive layer filling the contact hole on the front surface of the substrate; 1차 에치백을 수행하여 상기 플러그도전층 형성시 발생된 균열에 의한 단차를 제거하는 단계;Performing a first etch back to remove the step caused by the crack generated when the plug conductive layer is formed; 상기 단차가 제거된 플러그도전층에 대해 2차 에치백을 진행하는 단계; 및Performing a second etch back on the plug conductive layer from which the step is removed; And 상기 2차 에치백이 진행된 플러그도전층을 평탄화하여 상기 콘택홀에 매립된 플러그를 형성하는 단계Forming a plug embedded in the contact hole by planarizing the plug conductive layer subjected to the second etch back 를 포함하는 반도체 소자의 플러그 제조 방법.Plug manufacturing method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 1차 에치백은 측면방향으로 건식에치백이 유도되도록 하여 진행하는 반도체 소자의 플러그 제조 방법.The first etch back is a method of manufacturing a plug of the semiconductor device proceeds by causing the dry etch back in the lateral direction. 제2항에 있어서,The method of claim 2, 상기 1차 에치백은, 상기 층간절연막의 표면 상부에서 상기 플러그도전층이 일정 두께로 잔류할때까지 진행하는 반도체소자의 플러그 제조 방법.The first etch back is a method of manufacturing a plug of a semiconductor device to proceed until the plug conductive layer remains a predetermined thickness on the upper surface of the interlayer insulating film. 제3항에 있어서,The method of claim 3, 상기 잔류두께는 300∼400Å 타겟으로 하는 반도체소자의 플러그 제조 방법.A method for manufacturing a plug of a semiconductor device, wherein the residual thickness is a 300 to 400 GPa target. 제1항 내지 제4항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 상기 플러그도전층은 폴리실리콘막으로 형성하는 반도체소자의 플러그 제조 방법.The plug conductive layer is a plug manufacturing method of a semiconductor device formed of a polysilicon film. 제5항에 있어서,The method of claim 5, 상기 1차 에치백은 ECR(Electron Cyclotron Rresonance) 형태의 플라즈마소스를 사용하는 플라즈마장비에서 에치백하고, 상기 2차 에치백은 TCP(Transformer Coupled Plasma)형태의 플라즈마소스를 사용하는 플라즈마장비에서 진행하는 반도체소자의 플러그 제조 방법.The primary etch back is etched back in a plasma apparatus using an ECR (Electron Cyclotron Rresonance) type plasma source, and the secondary etch back is carried out in a plasma apparatus using a TCP (Transformer Coupled Plasma) type plasma source. Method for manufacturing plug of semiconductor device. 제6항에 있어서,The method of claim 6, 상기 1차 에치백은 불소계 가스와 산소(O2) 가스의 혼합가스를 사용하여 진행하는 반도체소자의 플러그 제조 방법.The first etch back is a method of manufacturing a plug of a semiconductor device to proceed using a mixed gas of fluorine-based gas and oxygen (O 2 ) gas. 제7항에 있어서,The method of claim 7, wherein 상기 불소계 가스는 CHF3와 SF6의 혼합가스를 이용하되, 그 유량비율을 9:1로 하는 반도체소자의 플러그 제조 방법.The fluorine-based gas using a mixed gas of CHF 3 and SF 6 , the flow rate ratio of 9: 1 plug manufacturing method of a semiconductor device. 제8항에 있어서,The method of claim 8, 상기 불소계 가스는 그 유량을 10∼100sccm으로 하고, 상기 산소가스는 유량을 1∼10sccm으로 하는 반도체소자의 플러그 제조 방법.The fluorine-based gas has a flow rate of 10 to 100 sccm, and the oxygen gas has a flow rate of 1 to 10 sccm. 제6항에 있어서,The method of claim 6, 상기 1차 에치백시 바텀 파워는 50∼400Ｗ를 인가하고, 압력은 3∼50mTorr으로 하는 반도체 소자의 플러그 제조 방법. The method for manufacturing a plug of a semiconductor device wherein bottom power is applied at 50 to 400 kW and the pressure is 3 to 50 mTorr during the first etch back. 제5항에 있어서,The method of claim 5, 상기 2차 에치백은,The secondary etch back, Cl2 가스와 HBr 가스를 혼합하여 진행하는 반도체소자의 플러그 제조방법.A method of manufacturing a plug of a semiconductor device which proceeds by mixing Cl 2 gas and HBr gas. 제1항에 있어서,The method of claim 1, 상기 평탄화는, 화학적기계적연마(CMP)로 진행하는 반도체 소자의 플러그 제조 방법.The planarization method is a plug manufacturing method of a semiconductor device which progresses by chemical mechanical polishing (CMP). 제1항에 있어서,The method of claim 1, 상기 플러그는 적어도 비트라인콘택노드 지역에 형성되는 랜딩플러그인 반도체소자의 플러그 제조 방법.And the plug is a landing plug formed at least in the bit line contact node region. 제1항에 있어서,The method of claim 1, 상기 콘택홀은, 오픈면적이 서로 다른 복수개가 형성되는 반도체소자의 플러그 제조 방법.The contact hole is a plug manufacturing method of a semiconductor device in which a plurality of different open areas are formed.
KR1020060134277A 2006-12-27 2006-12-27 Method for fabricating plug in semiconductor device KR20080060327A (en)

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