KR20110022267A - Method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A semiconductor device manufacturing method is provided to prevent the damage of the substrate under the contact hole by exposing the substrate under the contact hole by etching through the triple etching process on a first insulation layer, a second insulation layer, and a gate insulation layer. CONSTITUTION: A plurality of recess gates(36) is formed on a substrate(31). A first insulating layer(37) is formed according to the surface of the structure including the recess gate. An interlayer insulating film(38) filling the gap between the recess gates is formed on the first insulating layer. A contact hole(39) which opens the top of the substrate between the recess gates is formed by selectively etching the interlayer insulation layer.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a method of manufacturing a contact hole in a semiconductor device having a recess gate (RG).

Recently, a recess gate having a channel having a three-dimensional structure has been introduced and applied to prevent deterioration of operating characteristics due to a decrease in the degree of integration of semiconductor devices. In general, the recess gate refers to a gate structure having a part or all of the gate electrodes embedded in a recess pattern formed by selectively etching a substrate.

On the other hand, as the degree of integration of semiconductor devices increases, the gaps between gates become narrower, and accordingly, contact process margins also decrease. Landing Plug Contact (LPC) structures are widely used to secure such contact process margins. The landing plug contact process is a technique of securing an overlay margin in a subsequent contact process by filling a conductive material in a space between a gate where a bit line contact and a storage node contact are to be formed in advance.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate according to the prior art, and FIG. 2 is a cross-sectional view illustrating a problem of a semiconductor device having a recess gate according to the prior art. .

As shown in FIG. 1A, after the substrate 11 is selectively etched to form the recess pattern 12, the recess 11 having the recess pattern 12 embedded therein and partially protruding from the substrate 11 is formed. The access gate 16 is formed. In this case, the recess gate 16 is a stacked structure in which the gate insulating film 13, the gate electrode 14, and the gate hard mask film 15 are sequentially stacked.

Next, after the first insulating layer 17 is formed along the surface of the structure including the recess gate 16, the interlayer insulating layer 18 may be interposed between the recess gates 16 on the first insulating layer 17. Form.

Next, after forming a self-aligned contact mask (not shown) on the interlayer insulating film 18, the interlayer insulating film 18 to stop the etching in the first insulating film 17 by using the self-aligned contact mask as an etch barrier (etch barrier). ) Is formed to form a contact hole 19 exposing the upper portion of the substrate 11 between the recess gates 16.

Next, a second insulating film 20 is formed along the surface of the structure including the contact hole 19.

As shown in FIG. 1B, a gate spacer having a structure in which the first and second insulating layers 17 and 20 are selectively etched to stack the first and second insulating layers 17 and 20 on the sidewall of the recess gate 16. And at the same time expose the surface of the substrate 11 under the contact hole 19.

As illustrated in FIG. 1C, the contact hole 19 is filled with a conductive material to form a plug 21.

However, in the prior art, since the first and second insulating layers 17 and 20 are etched at the same time, that is, at the same time, during the etching process for exposing the surface of the substrate 11 under the contact hole 19, the contact hole is simultaneously. (19) A problem arises in which the lower substrate 11 is lost (see reference numeral 'A' in Fig. 1B).

If the junction region is formed in the substrate 11 between the recess gates 16 before the contact hole 19 is formed, the resistance of the junction region increases due to the loss of the substrate 11, or the junction region and the plug ( There arises a problem that the contact resistance between 21) increases. In addition, in the case where the junction region is formed in the substrate 11 between the recess gates 16 after the contact hole 19 is formed, the junction depth of the junction region is increased than the preset junction depth to decrease the channel length. Will cause problems.

In addition, as shown in FIG. 2, when a misalignment occurs in the process of forming the recess gate 16, a short may occur between the gate electrode 14 and the plug 21 due to the loss of the substrate 11. (See symbol 'B' in FIG. 2).

The present invention has been proposed to solve the above-mentioned problems of the prior art, and provides a semiconductor device manufacturing method that can prevent a substrate from being lost under a contact hole during a contact hole forming process in a semiconductor device having a recess gate. The purpose is.

In addition, another object of the present invention is to provide a method of manufacturing a semiconductor device that can prevent a short from occurring between a recess gate and a plug.

In accordance with an aspect of the present invention, a method of manufacturing a semiconductor device includes: forming a plurality of recess gates such that a gate insulating film remains on a substrate; Forming a first insulating layer along a surface of the structure including the recess gate; Forming an interlayer insulating film filling the gap between the recess gates on the first insulating film; Selectively etching the interlayer insulating layer to stop etching in the first insulating layer to form a contact hole for opening an upper portion of the substrate between the recess gates; Forming a second insulating layer along a surface of the contact hole; A first etching step of etching the second insulating layer under the contact hole and subsequently partially etching the first insulating layer; A secondary etching step of etching the remaining first insulating layer under the contact hole to stop etching in the gate insulating layer; A third etching step of exposing the surface of the substrate by etching the gate insulating layer under the contact hole; And embedding a conductive material in the contact hole to form a plug.

The present invention based on the above-described problem solving means, by etching the second insulating film, the first insulating film and the gate insulating film under the contact hole through three etching processes to expose the substrate surface under the contact hole, There is an effect to prevent the loss.

Accordingly, the present invention has the effect of preventing the deterioration of characteristics of the semiconductor device due to the loss of the substrate under the contact hole, and in particular, the short circuit between the recess gate and the plug can be prevented.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The present invention will be described later to prevent the loss of the substrate under the contact hole during the contact hole forming process in a semiconductor device having a recess gate (RG), even if misalignment occurs in the recess gate forming process Provided is a method of manufacturing a semiconductor device that can prevent shorts from occurring between plugs.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate according to an embodiment of the present invention.

As shown in FIG. 3A, a recess pattern 32 is formed by selectively etching a substrate 31, for example, a silicon substrate. The recess pattern 32 is provided to provide a channel having a three-dimensional structure, and may be formed in any one form selected from the group consisting of a rectangle, a polygon, a bulb type, and a saddle fin type.

Next, the recess pattern 32 is embedded to form a recess gate 36 in which a portion of the recess pattern 32 protrudes. The recess gate 36 may be formed as a stacked structure in which the gate insulating layer 33, the gate electrode 34, and the gate hard mask layer 35 are sequentially stacked. In this case, the recess gate 36 according to the exemplary embodiment of the present invention is formed such that the gate insulating layer 33 remains on the substrate 31. Hereinafter, a method of forming the recess gate 36 will be described in detail.

First, the gate insulating layer 33 is formed on the surface of the structure including the recess pattern 32. The gate insulating film 33 may be formed of an oxide film, for example, silicon oxide film (SiO ₂ ), and the silicon oxide film for the gate insulating film 33 may be formed using thermal oxidation. In this case, the gate insulating film 33 may be formed to have a thickness in the range of 10 kV to 20 kV.

Next, the recess pattern 32 is embedded on the gate insulating film 33 and a gate conductive film is formed to cover the upper portion of the substrate 31. The gate conductive film is formed of a laminated film in which a silicon film such as a polysilicon film (poly Si) or a silicon germanium film (SiGe) and a metal film such as tungsten (W), tungsten silicide (WS), or titanium nitride film (TiN) are laminated. can do.

Next, a gate hard mask film 35 is formed on the gate conductive film. The gate hard mask film 35 may be formed of any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride, or a laminated film in which these are stacked.

Next, after forming a photoresist pattern (not shown) on the gate hard mask layer 35, the gate hard mask layer 35 and the gate conductive layer are sequentially etched using the photoresist pattern as an etch barrier.

Through the above-described process, the gate insulating layer 33 remains on the substrate 11, and the recess gate having the structure in which the gate insulating layer 33, the gate electrode 34, and the gate hard mask layer 35 are sequentially stacked. 36 can be formed.

Next, a first insulating layer 37 is formed along the surface of the structure including the recess gate 36. In this case, the first insulating layer 37 protects the surface of the substrate 31 between the inter-process recess gate 36 and the recess gate 36, and serves as an etch stop layer in a subsequent contact hole forming process. In addition, the first insulating layer 37 serves as a spacer remaining on the sidewall of the recess gate 36.

The first insulating layer 37 may be formed of a material having an etching selectivity with the gate insulating layer 33. Therefore, the first insulating film 37 may be formed of a nitride film, and a silicon nitride film (Si ₃ N ₄ ) may be used as the nitride film. The first insulating layer 37 may be formed to have a thickness in the range of 20 kV to 70 kV.

Although not shown in the drawing, before the first insulating layer 37 is formed, the step of forming a spacer on the sidewall of the recess gate 36 may be additionally performed, and the substrate 31 between the recess gates 36 may be further formed. It is also possible to proceed with the step of forming a junction region by implanting impurities.

As shown in FIG. 3B, an interlayer insulating layer 38 is formed on the first insulating layer 37 to fill the gap between the recess gates 36 and cover the upper portion of the recess gate 36. In this case, the interlayer insulating film 38 is preferably formed of a material having an etching selectivity with respect to the first insulating film 37. Accordingly, the first insulating layer 38 may be formed of an oxide film, and BPSG (Boron Phosphorus Silicate Glass) having excellent buried characteristics may be used as the oxide film.

Next, after forming a self-aligned contact mask (not shown) on the interlayer insulating film 38, a self-aligned contact etching is performed to etch the interlayer insulating film 38 by using the self-aligned contact mask as an etch barrier. A contact hole 39 exposing the upper portion of the substrate 31 between the 36 is formed. At this time, since the first insulating layer 37 acts as an etch stop layer during the self-aligned contact etching, the etching is stopped in the first insulating layer 37. Therefore, the contact hole 39 has a structure that exposes the first insulating layer 37 on the substrate 31 between the recess gates 36 and is formed by the first insulating layer 37 during the process of forming the contact hole 39. It is possible to prevent the substrate 31 under the contact hole 39 from being damaged (or lost).

An etching process for forming the contact hole 39 may be performed using an anisotropic dry etch using high density plasma. At this time, the dry etching using the high-density plasma has an advantage of improving the etching characteristics because it can generate a large amount of radicals (radical) having excellent reactivity from the etching gas.

In the case where the interlayer insulating film 38 is formed of an oxide film, an etching process for forming the contact hole 39 includes carbon fluoride gas (C _x F _y , x and y are natural water except 0) and oxygen gas (O). ₂ ) can be carried out using a mixed gas (C _x F _y / O ₂ , x, y is a natural number except 0). In this case, CF ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₄ F ₈ , C ₆ F ₆ and the like can be used as the fluorocarbon gas.

Here, the mixed gas in which the fluorocarbon gas and the oxygen gas are mixed may have a mixing ratio of carbon fluoride gas: oxygen gas in a range of 40: 1 to 100: 1. For example, when the mixing ratio of carbon fluoride gas: oxygen gas is 40: 1, it means that the fluorocarbon gas and oxygen gas are supplied to the etching chamber at a flow rate of 400 sccm and 10 sccm, respectively.

Anisotropic dry etching using high density plasma uses any type of etching equipment selected from the group consisting of Inductively Coupled Plasma (ICP), Transformer Coupled Plasma (TCP), and Magnetically Enhanced Reactive Ion Beam Etching (MERIE). It can be carried out.

Next, a second insulating layer 40 is formed along the surface of the structure including the contact hole 39. The second insulating film 40 protects the surface of the substrate 31 between the recess gate 36 and the recess gate 36 along with the first insulating film 37 during the subsequent process, and is formed on the sidewalls of the recess gate 36. It acts as a remaining spacer. In this case, the second insulating layer 40 may be formed to have a thickness in the range of 30 kV to 80 kV.

The second insulating film 40 may be formed of the same material as the first insulating film 37. Accordingly, the second insulating film 40 may be formed of a nitride film, and a silicon nitride film may be used as the nitride film.

Hereinafter, the second insulating layer 40, the first insulating layer 37, and the gate insulating layer 33 are sequentially etched under the contact hole 39 to remove the substrate 31 below the contact hole 39 without losing the substrate 31. An etching process for exposing is described in detail with reference to FIGS. 3C to 3E.

As shown in FIG. 3C, a first etching process is performed to etch the second insulating layer 40 under the contact hole 39 and subsequently partially etch the first insulating layer 37. Specifically, a first etching process of selectively etching the first and second insulating layers 37 and 40 is performed to stack the first and second insulating layers 37 and 40 on the sidewalls of the recess gate 36. While forming the spacer, the first insulating layer 37 is left on the contact hole 39 lower gate insulating layer 33 by a predetermined thickness T.

Here, the sum of the thicknesses of the first and second insulating layers 37 and 40 remaining on the substrate 31 under the contact hole 39 before the first etching process is in the range of 50 μs to 150 μs, and the primary etching is performed. The thickness T of the first insulating layer 37 remaining after the process is in a range of 10% of the sum of the thicknesses of the first and second insulating layers 37 and 40, that is, the first insulating layer remaining on the gate insulating layer 33 ( 37) is preferably formed to have a thickness (T) in the range of 5 kPa to 15 kPa. For reference, when the first etching process is performed by targeting the thickness of the first insulating layer 37 remaining in the first etching process to less than 10%, the gate insulating film 33 may be damaged (or lost) during the first etching process. If the first etching process is performed by targeting the thickness of the remaining first insulating film 37 to be greater than 10%, the burden on the second etching process for removing the remaining first insulating film 37 is removed. There is a risk of increasing.

As the first and second insulating layers 37 and 40 are formed of the same material (eg, silicon nitride), as the etching gas in the first etching process, carbon fluoride gas (C _x F _y , x and y are natural numbers except 0). , Mixed gas mixed with methane fluoride gas (C _l H _m F _n , where l, m, n is natural water except 0) and oxygen gas (O ₂ ) (C _x F _y / C _l H _m F _n / O ₂ , x, y, l, m, n can be implemented using a natural number except 0). In this case, CF ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₄ F ₈ , C ₆ F ₆ and the like can be used as the fluorocarbon gas, CHF ₃ , CH ₂ F ₂ Etc. can be used.

Here, the mixed gas of the fluorocarbon gas, the fluorinated methane gas and the oxygen gas may have a mixing ratio of fluorocarbon gas: methane fluoride gas: oxygen gas in a range of 9: 3: 1 to 3: 9: 1. For example, when the mixing ratio of carbon fluoride gas: methane fluoride gas: oxygen gas is 9: 3: 1, it means that carbon fluoride gas, fluoride methane gas, and oxygen gas are supplied to the chamber at a flow rate of 90 sccm, 30 sccm, and 10 sccm, respectively. .

In addition, the primary etching process may be performed using an anisotropic dry etching method using a high density plasma. Therefore, the primary etching process may be performed using etching equipment of ICP type, TCP type or MERIE type. Here, in the first etching process, the second and first insulating layers 40 and 37 are 5 s / sec to leave the first insulating layer 37 on the gate insulating layer 33 under the contact hole 39 by a predetermined thickness (T). It is preferable to etch the etching rate in the range of ˜20 dB / sec. If the etching rates of the second and first insulating layers 40 and 37 are less than 5 μs / sec, the first etching process time may be increased, and thus the structure may be damaged by the high density plasma, and the etching rate may be 20 μs / sec. If it exceeds, it is difficult to adjust the thickness T of the remaining first insulating film 37.

As shown in FIG. 3D, a second etching process of etching the first insulating layer 37 remaining on the gate insulating layer 33 under the contact hole 39 is performed. That is, in the secondary etching process, the first insulating layer 37 remaining under the contact hole 39 is etched to stop the etching in the gate insulating layer 33.

The secondary etching process may be performed using anisotropic dry etching using high density plasma. Therefore, the secondary etching process may be performed using etching equipment of the ICP type, the TCP type, or the MERIE type, and may be performed in-situ in the same chamber as the primary etching process.

In addition, in order to selectively etch only the first insulating layer 37 remaining under the contact hole 39, that is, the nitride layer, without losing the gate insulating layer 33 made of an oxide layer during the secondary etching process, hydrogen bromide gas (HBr) is used as an etching gas. ), Preferably using a mixed gas (HBr / O ₂ / He) in which oxygen gas (O ₂ ) and helium gas (He) are mixed. In this case, the hydrogen bromide serves to etch the first insulating layer 37 (that is, to etch the nitride layer), and oxygen provides an etching selectivity between the gate insulating layer 33 and the first insulating layer 37. Plays a role (i.e., provides an etch selectivity between oxide and nitride), and helium plays a role in plasma generation and maintenance.

Here, in order to more effectively secure the etching selectivity between the gate insulating film 33 and the first insulating film 37 during the secondary etching process, the mixed gas including hydrogen bromide gas, oxygen gas, and helium gas, which is an etching gas, is hydrogen bromide. The mixing ratio of gas: oxygen gas: helium gas may be in the range of 30: 1: 30 to 10: 1: 5. For example, when the mixing ratio of hydrogen bromide gas: oxygen gas: helium gas is 30: 1: 30, it means that hydrogen bromide gas, oxygen gas, and helium gas are supplied to the etching chamber at a flow rate of 300sccm, 10sccm, and 300sccm, respectively.

On the other hand, argon (Ar) is commonly used for plasma generation and maintenance, but since argon is a material having a larger atomic weight than helium, when argon is used instead of helium during the secondary etching process, the gate is formed by argon sputtering. The insulating film 33 may be damaged. For reference, etching by helium and argon sputtering does not have a selectivity to the etching target film.

In addition, the secondary etching process includes source power in the range of 200 W to 500 W and 100 W to 300 W to selectively etch only the first insulating layer 37 remaining under the contact hole 39 without losing the gate insulating layer 33. This can be done using a bias power in the range.

As shown in FIG. 3E, a third etching process is performed to expose the surface of the substrate 31 by etching the gate insulating layer 33 under the contact hole 39. In this case, the tertiary etching process may be performed by using an anisotropic dry etching method using a high density plasma, or by using a wet etching method.

Hereinafter, a case where the third etching process is performed by using an anisotropic dry etching method using high density plasma will be described in detail.

Carbon fluoride gas (C _x F _y ) is used as an etching gas for etching only the gate insulating film 33 made of an oxide film without any loss of the substrate 31 by using any one of ICP type, TCP type or MERIE type high density plasma etching equipment. , x, y is natural water except 0), methane fluoride gas (C _l H _m F _n , l, m, n is natural water except 0), oxygen gas (O ₂ ) and argon gas (Ar) mixed Gas can be used. At this time, in order to more effectively etch only the gate insulating film 33 without losing the substrate 31, the mixed gas in which carbon fluoride gas, methane fluoride gas, oxygen gas, and argon gas is mixed is fluorocarbon gas: fluorine methane gas: oxygen gas: The mixing ratio of argon gas may range from 3: 3: 1: 5 to 5: 5: 1: 20. For example, when the mixing ratio of carbon fluoride gas: methane fluoride gas: oxygen gas: argon gas is 3: 3: 1: 5, the carbon fluoride gas, the fluorine methane gas, the oxygen gas, and the argon gas are respectively 30 sccm and 30 sccm in the etching chamber. , Means supplying at a flow rate of 10sccm and 50sccm.

In addition, in order to prevent the loss of the substrate 31 during the third etching process, it is preferable to use the source power in the range of 200W to 600W and the bias power in the range of 100W to 300W.

As such, when the tertiary etching process is performed using anisotropic dry etching method using high density plasma, the tertiary etching process may be performed in situ in the same chamber continuously with the first and second etching processes. There is an advantage that can improve the productivity of the semiconductor device.

Hereinafter, a case where the third etching process is performed by using the wet etching method will be described in detail.

In order to selectively etch only the gate insulating layer 33 including the oxide layer without losing the substrate 31, a third etching process may be performed using a buffered oxide etchant (BOE) or a hydrofluoric acid solution (HF).

As such, when the third etching process is performed using the wet etching method, the by-products generated between the first and second etching processes may be stably removed while the gate insulating layer 33 is selectively removed without loss of the substrate 31. byproduct) can be removed at the same time.

As shown in FIG. 3F, a plug 41 is formed by filling a conductive material in the contact hole 39. The plug 41 may be formed of a silicon film or a metal film, and after the conductive material is deposited on the entire surface of the substrate to sufficiently fill the contact hole 39, the interlayer insulating film 38 or the gate hard mask film 35 may be exposed. It can be formed through a series of process steps to perform a planarization process under the conditions. In this case, the planarization process may be performed using chemical mechanical polishing.

Meanwhile, when the tertiary etching process is performed by using a dry etching method, a cleaning process for removing by-products generated between processes may be additionally performed before the plug 41 is formed. Although not shown in the drawings, before the plug 41 is formed, impurities are implanted into the substrate 31 under the contact hole 39 to form a junction region, or after the plug 41 is formed, the plug ( Impurities contained in 41 may be diffused into the substrate 31 to form a junction region.

As described above, according to the present invention, the second insulating layer 40, the first insulating layer 37, and the gate insulating layer 33 are etched three times under the contact hole 39, and the substrate 31 under the contact hole 39 is etched. ), The substrate 31 can be prevented from being lost (or damaged) during the contact hole 39 forming process.

As a result, the present invention can increase the physical distance between the recess gate 36 and the plug 41 to prevent the short from occurring. In addition, it is possible to prevent deterioration of characteristics of the semiconductor device, such as loss of a junction region due to the loss of the substrate 31 under the contact hole, an increase in contact resistance between the junction region and the plug 41, and an increase in the junction depth of the junction region.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate according to the prior art.

2 is a cross-sectional view showing a problem of a semiconductor device having a recess gate according to the prior art.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate in accordance with an embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

31 substrate 32 recess pattern

33: gate insulating film 34: gate electrode

35 gate hard mask layer 36 recess gate

37: first insulating film 38: interlayer insulating film

39: contact hole 40: second insulating film

41: plug

Claims (20)

Forming a plurality of recess gates such that a gate insulating film remains on the substrate; Forming a first insulating layer along a surface of the structure including the recess gate; Forming an interlayer insulating film filling the gap between the recess gates on the first insulating film; Selectively etching the interlayer insulating layer to stop etching in the first insulating layer to form a contact hole for opening an upper portion of the substrate between the recess gates; Forming a second insulating layer along a surface of the contact hole; A first etching step of etching the second insulating layer under the contact hole and subsequently partially etching the first insulating layer; A secondary etching step of etching the remaining first insulating layer under the contact hole to stop etching in the gate insulating layer; A third etching step of exposing the surface of the substrate by etching the gate insulating layer under the contact hole; And Filling a conductive material in the contact hole to form a plug Semiconductor device manufacturing method comprising a. The method of claim 1, The first, second and third etching process is a semiconductor device manufacturing method using an anisotropic dry etching method using a high density plasma. The method of claim 2, The first, second and third etching process is performed in-situ in the same chamber. The method of claim 1, The first and second etching processes are performed using anisotropic dry etching using high density plasma, and the third etching process using a wet etching method. The method of claim 4, wherein The first and second etching process is performed in-situ in the same chamber. The method of claim 1, And the first etching is performed such that the first insulating layer, which is 10% thick compared to the sum of the thicknesses of the second and first insulating layers below the contact hole before the first etching process, remains under the contact hole. The method of claim 1, In the first etching process, the second and first insulating layers are etched at an etching rate in the range of 5 kW / sec to 20 kW / sec. The method according to claim 2 or 4, The second etching process is a semiconductor device manufacturing method using a source power in the range of 200W ~ 500W and bias power in the range of 100W ~ 300W. The method of claim 2, The third etching process is performed using a source power in the range of 200 to 600 and a bias power in the range of 100 to 300. The method of claim 1, And the gate insulating film and the gate insulating film are formed of a material having an etch selectivity with respect to the first insulating film. The method of claim 1, And the first and second insulating layers are formed of the same material. The method of claim 1, And said first and second insulating films comprise a nitride film, and said interlayer insulating film and said gate insulating film comprise an oxide film. The method according to claim 1 or 12, wherein The first etching process is a semiconductor device manufacturing method using a mixed gas mixed with carbon fluoride gas, methane fluoride gas and oxygen gas. The method of claim 13, The mixed gas may have a mixing ratio of carbon fluoride gas: methane fluoride gas: oxygen gas in a range of 9: 3: 1 to 3: 9: 1. The method according to claim 1 or 12, wherein The second etching process is a semiconductor device manufacturing method using a mixed gas of hydrogen bromide gas, oxygen gas and helium gas. The method of claim 15, The mixed gas has a mixing ratio of hydrogen bromide gas: oxygen gas: helium gas in the range of 30: 1: 30 ~ 10: 1: 5. The method according to claim 1 or 12, wherein The third etching process is a semiconductor device manufacturing method using a mixed gas mixed with carbon fluoride gas, methane fluoride gas, oxygen gas and argon gas. The method of claim 17, The mixed gas has a mixing ratio of carbon fluoride gas: methane fluoride gas: oxygen gas: argon gas in a range of 3: 3: 1: 5 to 5: 5: 1: 20. The method according to claim 1 or 12, wherein The third etching process is performed using a buffered oxide etchant (BOE) or hydrofluoric acid solution (HF). The method of claim 1, Forming the recess gate, Selectively etching the substrate to form a recess pattern; Forming a gate insulating film on an entire surface of the substrate including the recess pattern; Filling the recess pattern on the gate insulating layer and forming a gate conductive layer covering the substrate; Forming a gate hard mask layer on the gate conductive layer; And Selectively etching the gate hard mask layer and the gate conductive layer Semiconductor device manufacturing method comprising a.

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