KR20080060100A - A liquide crystal display device and a method for driving the same - Google Patents

Abstract

An LCD and a driving method thereof are provided to discharge electrons charged within an LC panel quickly when power voltage supplied from the outside is suddenly stopped while an LCD is normally driven, thereby improving the screen quality of the LCD. A DC(Direct Current)-DC converter(101) converts power voltage into voltage that each part of an LCD(Liquid Crystal Display) needs, and outputs the converted voltage. A gate driver(103) selectively outputs gate high voltage and gate low voltage received from the DC-DC converter. In an LC panel(107), plural pixels where data lines and gate lines cross each other are formed. The LC panel is sequentially driven according as the gate lines receive the gate high voltage or the gate low voltage. A discharge voltage supply unit(109) is charged by gate high voltage when power voltage is supplied. If the power voltage is cut off, the discharge voltage supply unit discharges an electric charge, charged in the LC panel, by supplying the charged voltage to a gate low voltage input terminal of the gate driver.

Description

Liquid crystal display and driving method thereof {A LIQUIDE CRYSTAL DISPLAY DEVICE AND A METHOD FOR DRIVING THE SAME}

1 is a block diagram schematically illustrating a general liquid crystal display device.

2 is a block diagram illustrating a liquid crystal display according to a preferred embodiment of the present invention.

3 is a block diagram illustrating region A of FIG. 2 in detail;

4 is a circuit diagram of the discharge voltage supply unit of FIGS. 2 and 3.

** Description of the symbols for the main parts of the drawings **

101: DC-DC converter

103: gate driver

103a: shift register section

103b: level shifter

103c: buffer section

107: liquid crystal panel

109: discharge voltage supply unit

SW1, SW2: first and second switching elements

C1, C2, C3: first, second and third capacitor

D1: diode

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a discharge voltage supply unit for quickly discharging charges charged in the liquid crystal panel to eliminate afterimages on the screen when the power supply voltage supplied to the liquid crystal display device is suddenly removed. It is about.

In general, a liquid crystal display device includes a liquid crystal panel in which a color filter substrate as an upper substrate and a thin film transistor array substrate as a lower substrate are opposed to each other, and a liquid crystal layer is filled between the two substrates, a scan signal is supplied to the liquid crystal panel, and image information is supplied. It includes a driving unit for performing the operation of the liquid crystal panel.

The conventional liquid crystal display will be described with reference to the drawings.

1 is a block diagram schematically illustrating a general liquid crystal display device.

As shown in FIG. 1, a general liquid crystal display device includes: a DC-DC converter 1 for converting a power supply voltage VCC to a level required by each part of the liquid crystal display device and outputting the same; A gate driver (3) for selectively outputting a gate high voltage (VGH) and a gate low voltage (VGL) received from the DC-DC converter (1); A plurality of pixels in which the data lines DL1 to DLn and the gate lines GL1 to GLn intersect are formed, and each of the gate lines GL1 to GLn is the gate high voltage VGH or the gate low voltage VGL. It is configured to include a liquid crystal panel 7 that is sequentially driven to receive.

The liquid crystal panel 7, more particularly, the thin film transistor array substrate, which is a lower substrate of the liquid crystal panel 7, may include gate lines GL1 to GLn spaced apart from each other at regular intervals as shown in FIG. 1. The data lines DL1 to DLn that are regularly spaced apart from each other intersect with each other, and the thin film transistors are formed for each pixel defined by the crossing of the gate lines GL1 to GLn and the data lines DL1 to GLn. Transistors (hereinafter referred to as TFTs) are formed, and pixel electrodes are provided. Here, the gate terminal of the TFT is connected to the gate lines GL1 to GLn, the source terminal is connected to the data lines DL1 to DLn, and the drain terminal is connected to the pixel electrode.

Although not shown, the color filter substrate, which is the upper substrate of the liquid crystal panel 7, has R, G, and B color filter layers and a common electrode formed thereon. The pixel electrode and the common electrode face each other with the liquid crystal layer interposed therebetween, and the light transmittance of the liquid crystal layer is controlled by the magnitude of the electric field generated between the two electrodes. In this case, the pixel electrode and the common electrode facing each other with the liquid crystal layer interposed therebetween function as a liquid crystal capacitor Clc having the liquid crystal layer as a dielectric.

The TFT is turned on when the scan signal from the gate lines GL1 to GLn, that is, the gate high voltage VGH is supplied, and the liquid crystal capacitor Clc is connected to the data lines DL1 to DLn. The pixel signal inputted through is charged. The TFT is turned off when the gate low voltage VGL is input through the gate lines GL1 to GLn, and the pixel signal charged in the liquid crystal capacitor Clc is maintained.

The liquid crystal capacitor Clc includes a storage capacitor Cst so that the charged pixel signal is stably maintained until the next pixel signal is charged.

On the other hand, in the liquid crystal display according to the related art as described above, when the power supply voltage VCC supplied from the outside is blocked through the normal path, the LCD device follows a predetermined sequence and thus does not leave an afterimage on the screen.

However, when the power supply voltage supplied from the outside is suddenly cut off while the LCD is being driven, it does not follow a predetermined sequence, and the afterimage remains on the screen due to the charges charged in the liquid crystal capacitor and the auxiliary capacitor of the liquid crystal panel. There is this.

Accordingly, an object of the present invention is to supply a voltage equal to the gate high voltage to the liquid crystal panel when the power supply voltage supplied to the liquid crystal display device is suddenly removed, thereby rapidly discharging the charges charged in the liquid crystal panel to eliminate afterimages on the screen. A liquid crystal display device having a supply unit is provided.

The present invention for achieving the above object, the DC-DC converter for converting the power supply voltage to the voltage required by each part of the liquid crystal display device for outputting; A gate driver for selectively outputting a gate high voltage and a gate low voltage received from the DC-DC converter; A liquid crystal panel in which a plurality of pixels in which data lines intersect gate lines are formed, and each gate line is sequentially driven by receiving the gate high voltage or the gate low voltage; And a discharge voltage supply unit configured to discharge the charged charge to the liquid crystal panel by supplying the charged voltage to the gate low voltage input terminal of the gate driver when the power supply voltage is supplied and charged by the gate high voltage. It is characterized by.

The voltage supplied with the power supply voltage and charged to the discharge voltage supply part is the same voltage as the gate high voltage.

The discharge voltage supply unit may include: a first capacitor charged by a gate high voltage supplied as a power supply voltage is supplied, and discharged when the supply of the gate high voltage is stopped as the supply of the power supply voltage is stopped; A second capacitor charged by a gate high voltage supplied as a power supply voltage is supplied; A diode which prevents the voltage charged in the second capacitor from being discharged into the charging path of the second capacitor when the power supply voltage is stopped; A first switching element which is turned on as the first capacitor is discharged when the power supply voltage is cut off, and supplies a voltage charged in the second capacitor to a gate low voltage input terminal of the gate driver; And when the power supply voltage is supplied, the voltage is turned on to block the path in which the voltage charged in the second capacitor is input to the gate low voltage input terminal of the gate driver, and when the power supply voltage is cut off, the voltage charged in the second capacitor is turned off. And a second switching device providing a path to be input to the gate low voltage input terminal.

The voltage charged in the first and second capacitors is the same voltage as the gate high voltage.

The first switching element is a PMOS transistor, and the second switching element is characterized in that the NMOS transistor.

And the diode is a Schottky diode.

The discharge voltage supply unit may further include a third capacitor connected to the drain terminal of the first switching device to perform a voltage buffering function.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a liquid crystal display according to a preferred embodiment of the present invention.

3 is a block diagram illustrating region A of FIG. 2 in detail, and illustrates in detail a relationship between a discharge voltage supply unit and a peripheral element thereof.

4 is a circuit diagram of the discharge voltage supply unit of FIGS. 2 and 3.

As shown in FIG. 2, a liquid crystal display according to an exemplary embodiment of the present invention includes a DC-DC converter 101 for converting a power supply voltage VCC to a level required by each unit of the liquid crystal display; A gate driver 103 for selectively outputting a gate high voltage VGH and a gate low voltage VGL received from the DC-DC converter 101; A plurality of pixels in which the data lines DL1 to DLn and the gate lines GL1 to GLn intersect are formed, and each of the gate lines GL1 to GLn is the gate high voltage VGH or the gate low voltage VGL. A liquid crystal panel 107 sequentially driven; And when the power supply voltage VCC is supplied, is charged by the gate high voltage VGH, and when the power supply voltage VCC is cut off, the charged voltage is supplied to the gate low voltage input terminal of the gate driver 103 to supply the liquid crystal panel. And a discharge voltage supply unit 109 for discharging the electric charge charged in 107.

In addition, a control signal for driving the liquid crystal panel 107 using signals input from the outside (Gate Start Pulse; GSP, Gate Shift Clock; GSC, Gate Output Enable; GOE, Sourse Start Pulse; SSP, Sourse Output Enable) And a timing controller 111 for generating SOE, Data Reverse; REV, Polarity; POL), and rearranging and outputting pixel data from the outside.

The data driver 105 also includes a data driver 105 for appropriately converting pixel data from the timing controller 111 and supplying the data to the data lines DL1 to DLn.

The DC-DC converter 101 boosts or depresses a power supply voltage VCC input from the outside to a level required by each part of the liquid crystal display, and the voltage is a gate high voltage VGH and a gate low. Voltage VGL.

The gate driver 103 selectively outputs the gate high voltage VGH and the gate low voltage VGL received from the DC-DC converter 101 in response to a control signal from the timing controller 111. The gate lines are sequentially supplied to the gate lines GL1 to GLn.

That is, the gate driver 103 shifts the gate start pulse GSP from the timing controller 111 according to the gate shift clock GSC to sequentially turn the gate high voltage VGH on the gate lines GL1 to GLn. The gate low voltage VGL is supplied to the gate lines in a period where the gate high voltage VGH is not supplied to the gate lines GL1 to GLn.

The data driver 105 properly converts the pixel data from the timing controller 111 and supplies the data lines DL1 to DLn line by line in response to a control signal from the timing controller 111.

The discharge voltage supply unit 109 charges the gate high voltage VGH when the liquid crystal display is normally driven, and the charged voltage when the power supply voltage VCC is suddenly cut off from the outside. Is supplied to the gate low voltage input terminal. Therefore, the same voltage as the gate high voltage VGH is applied to the entire gate lines GL1 to GLn, thereby discharging the charges charged in the liquid crystal panel 107.

The relationship between the discharge voltage supply unit 109 and components around the discharge voltage supply unit 109 will be described in more detail with reference to FIG. 3.

The DC-DC converter 101 converts an external power supply voltage VCC to generate a gate high voltage VGH and a gate low voltage VGL to generate a level shift unit 103b of the gate driver 103. To supply.

The gate driver 103 includes a shift register section 103a, a level shifter section 103b, and a buffer section 103c.

The shift register section 103a shifts and outputs the gate start pulse GSP from the timing control section 111 in accordance with the gate shift clock GSC, and supplies it to the level shifter section 103b.

The level shifter 103b outputs any one of a gate high voltage VGH and a gate low voltage VGL in response to the signal received from the shift register 103a to the buffer 103C. Supply. In more detail, the level shifter 103b may include one of a gate high voltage input terminal and a gate low voltage input terminal of the level shifter 103b and the buffer unit 103c in response to the signal received from the shift register unit 103a. The gate high voltage VGH and the gate low voltage VGL are supplied to the buffer unit 103c by the connection therebetween.

That is, when the level shifter 103b receives a signal from the shift register 103a, the level shifter 103b connects the gate high voltage input terminal and the buffer 103c to the gate line GL1 to GLn through the buffer 103c. In order to supply the high voltage VGH and to receive no signal, the gate low voltage input terminal and the buffer unit 103c are connected to the gate low voltage VGL through the buffer unit 103c to the gate lines GL1 to GLn. To be supplied.

The buffer unit 103c buffers and outputs the output signal from the level shifter unit 103b and supplies the same to the gate lines GL1 to GLn.

The discharge voltage supply unit 109 is charged by the gate high voltage VGH from the gate high voltage output terminal of the DC-DC converter 101 when the liquid crystal display is normally driven. Here, the voltage charged in the discharge voltage supply unit 109 is the same voltage as the gate high voltage (VGH).

In addition, the discharge voltage supply unit 109 suddenly cuts off the power supply voltage VCC supplied from the outside, and thus the gate high voltage VGH and the gate low voltage VGL from the DC-DC converter 101 to the gate driver 103. ) Is stopped, the same voltage as that stored when the LCD is normally driven, that is, the same voltage as the gate high voltage VGH is supplied to the gate low voltage input terminal of the gate driver 103.

That is, when the power supply voltage VCC suddenly shuts off from the outside, most of the level shifter 103b is connected to the gate low voltage input terminal of the level shifter 103b and the buffer 103c. The level shifter 103b supplies the same voltage as the gate high voltage VGH to the buffer 103c.

Accordingly, since the same voltage as that of the gate high voltage VGH is applied to most of the gate lines GL1 to GLn, most of the gate lines GL1 to GLn are driven, so that the charges charged in the liquid crystal panel 107 are quickly increased. Discharged.

An internal configuration of the discharge voltage supply unit 109 will be described in more detail with reference to FIG. 4 as follows.

As shown in FIG. 4, the discharge voltage supply unit 109 is charged by the gate high voltage VGH supplied as the power supply voltage VCC is supplied, and as the supply of the power supply voltage VCC is stopped, the gate is discharged. A first capacitor C1 that discharges when the supply of the high voltage VGH is stopped; A second capacitor C2 charged by the gate high voltage VGH supplied as the power supply voltage VCC is supplied; A diode (D1) for preventing the voltage charged in the second capacitor (C2) from being discharged to the charging path of the second capacitor (C2); And a first voltage that is turned on as the first capacitor C1 is discharged when the power supply voltage VCC is cut off, and supplies a voltage charged in the second capacitor C2 to the gate low voltage input terminal of the gate driver 103. Switching element SW1; And turns off when the power supply voltage VCC is supplied to block a path in which the voltage charged in the second capacitor C2 is input to the gate low voltage input terminal of the gate driver 103, and turns off when the power supply voltage VCC is blocked. And a second switching device SW2 providing a path so that the voltage charged in the second capacitor C2 is input to the gate low voltage input terminal of the gate driver 103.

In addition, the discharge voltage supply unit 109 further includes a third capacitor C3 connected to the drain terminal of the first switching element SW1 to perform a voltage buffering function.

The first switching element SW1 is a PMOS transistor, the second switching element SW2 is an NMOS transistor, and the diode D1 is a Schottky diode.

In addition, the points where the discharge voltage supply unit 109 is connected to a path where the DC-DC converter 101 and the gate driver 103 are connected are referred to as first and second nodes n1 and n2. That is, the first node n1 is a point where the discharge voltage supply unit 109 is connected to a path where the gate high voltage output terminal of the DC-DC converter 101 and the gate high voltage input terminal of the level shifter 103b are connected. The second node n2 is a point where the discharge voltage supply unit 109 is connected to a path between the gate low voltage output terminal of the DC-DC converter 101 and the gate low voltage input terminal of the level shifter 103b.

In addition, a resistor R1 is further provided between the diode D1 and the source terminal of the first switching device SW1 to transfer an appropriate voltage value to the first switching device SW1.

An operation of the discharge voltage supply unit having such a configuration will be described below with reference to FIGS. 3 and 4.

First, when the power supply voltage VCC is normally supplied and the gate high voltage VGH and the gate low voltage VGL are also normally supplied, the first switching is performed by supplying the gate high voltage VGH from the first node n1. Element SW1 is turned off. In addition, when the power supply voltage VCC is normally supplied from the outside and the liquid crystal display device operates normally, the second switching element SW2 is turned on by supplying the power supply voltage VCC.

Accordingly, the first and second capacitors C1 and C2 are charged by the gate high voltage VGH input from the first node n1.

The voltage charged in the first capacitor C1 and the second capacitor C2 is equal to the gate high voltage VGH.

Subsequently, when the supply of the gate high voltage VGH and the gate low voltage VGL is stopped due to the non-supply of the power supply voltage VCC, the voltage charged in the first capacitor C1 is discharged and the first switching device SW1 is discharged. ), That is, the PMOS transistor is turned on. Here, the voltage charged in the second capacitor C2 is limited in the discharge path toward the first node n1 by the diode D1 disposed between the second capacitor C2 and the first node n1. do. When the power supply voltage VCC supplied from the outside is cut off, the second switching element SW2, that is, the NMOS transistor, is turned off by not supplying the power supply voltage VCC.

Accordingly, the voltage charged in the second capacitor C2 is output to the second node n2 through the first switching element SW1. More specifically, the voltage charged in the second capacitor C2 is passed through the resistor R1 and the first switching element SW1 and then buffered by the third capacitor C3 and output to the second node n2. Becomes

Therefore, the gate high voltage VGH and the gate low voltage VGL are not supplied from the DC-DC converter 101 to the gate driver 103 due to the supply interruption of the power supply voltage VCC, but the discharge voltage supply unit 109 The same voltage as that of the gate high voltage VGH charged in the second capacitor C2 is supplied to the gate low voltage input terminal of the gate driver 103.

That is, most of the level shifter 103b in which a signal is not input from the shift register 103b is connected to the gate low voltage input terminal and the buffer 103c at a time when the power supply voltage VCC suddenly stopped from the outside. Thus, as described above, the discharge voltage supply unit 109 supplies the same voltage as the gate high voltage VGH to the gate low voltage input terminal of the level shifter 103b to the gate lines GL1 to GLn. There is an effect of applying the gate high voltage VGH.

Therefore, when the power supply voltage VCC is suddenly stopped, the charges charged in the liquid crystal panel 107 are quickly discharged.

As described in detail above, the present invention has the following advantages.

The present invention includes a discharge voltage supply unit connected to a gate high voltage output terminal and a gate low voltage output terminal of the DC-DC converter, and a path connected to the gate high voltage input terminal and the gate low voltage input terminal of the gate driver. When the power supply voltage supplied from the outside is suddenly interrupted, the charges charged in the liquid crystal panel are quickly discharged, thereby increasing the screen quality of the liquid crystal display.

Claims (8)

A DC-DC converter for converting a power supply voltage into a voltage required by each unit of the liquid crystal display and outputting the voltage; A gate driver for selectively outputting a gate high voltage and a gate low voltage received from the DC-DC converter; A liquid crystal panel in which a plurality of pixels in which data lines intersect gate lines are formed, and each gate line is sequentially driven by receiving the gate high voltage or the gate low voltage; And A discharge voltage supply unit configured to charge by a gate high voltage when a power supply voltage is supplied, and supply a charged voltage to a gate low voltage input terminal of the gate driver to discharge charges charged in the liquid crystal panel when the power supply voltage is blocked; Liquid crystal display device comprising a. The liquid crystal display device according to claim 1, wherein a voltage supplied with a power supply voltage and charged to the discharge voltage supply part is equal to a gate high voltage. The method of claim 1, wherein the discharge voltage supply unit, A first capacitor charged by the gate high voltage supplied as the power supply voltage is supplied, and discharged when the supply of the gate high voltage is stopped as the supply of the power supply voltage is stopped; A second capacitor charged by a gate high voltage supplied as a power supply voltage is supplied; A diode which prevents the voltage charged in the second capacitor from being discharged into the charging path of the second capacitor when the power supply voltage is stopped; A first switching element which is turned on as the first capacitor is discharged when the power supply voltage is cut off, and supplies a voltage charged in the second capacitor to a gate low voltage input terminal of the gate driver; And When the power supply voltage is turned on, the voltage charged in the second capacitor cuts off the path where the voltage is input to the gate low voltage input terminal of the gate driver. A second switching element providing a path to be input to a low voltage input terminal; Liquid crystal display device comprising a. 4. The liquid crystal display of claim 3, wherein the voltages charged in the first and second capacitors are the same as the gate high voltages. 4. The liquid crystal display device according to claim 3, wherein the first switching element is a PMOS transistor. 4. The liquid crystal display device according to claim 3, wherein the second switching element is an NMOS transistor. 4. The liquid crystal display device according to claim 3, wherein the diode is a Schottky diode. The method of claim 3, wherein the discharge voltage supply unit, And a third capacitor connected to the drain terminal of the first switching element, the voltage capacitor acting as a voltage buffer.

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