KR20080056862A - Display apparatus - Google Patents

Abstract

A display apparatus is provided to enhance the data charge rates of a pixel unit by ensuring margins according to an eight-division operation on a gate signal. A display apparatus includes a display panel(100), a data driver, and first, second, third, fourth, fifth, sixth, seventh, and eighth gate circuits. The display panel includes display areas having plural pixel units which are defined by data and data lines. The data driver outputs data voltages to the data lines. The first, second, third, fourth, fifth, sixth, seventh, and eighth gate circuits output gate signals to (8k-7)-th, (8k-6)-th, (8k-5)-th, (8k-4)-th, (8k-3)-th, (8k-2)-th, (8k-1)-th, and 8k-th gate lines, respectively.

Description

Display device {DISPLAY APPARATUS}

1 is a schematic plan view of a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram illustrating the driving unit illustrated in FIG. 1.

3A to 3D are block diagrams illustrating the first gate driver illustrated in FIG. 1.

4 is a diagram conceptually illustrating a configuration of a stage that forms the first and second gate drivers.

5 is a signal waveform diagram illustrating an operation of the first and second gate drivers.

<Description of the symbols for the main parts of the drawings>

100: display panel 110: array substrate

120: opposing substrate 130: flexible circuit board

200: driver 310: first gate driver

320: second gate driver DA: display area

PA1 ~ PA3: Peripheral TFT: Thin Film Transistor

CLC: Liquid Crystal Capacitor CST: Storage Capacitor

GL1 to GLn: Gate Wirings DL1 to DL: Data Wiring

The present invention relates to a liquid crystal display device, and more particularly, to a display device for improving driving reliability at high resolution.

2. Description of the Related Art Generally, a liquid crystal display device includes a display panel including an array substrate and an opposite substrate facing each other with a liquid crystal having an anisotropic dielectric constant therebetween, and a driving circuit unit for driving the display panel. Gate lines extend in one direction, data lines extend in a direction crossing the gate lines, and a plurality of pixel parts defined in the gate lines and the data lines are formed in the display panel.

The driving circuit unit includes a gate driver sequentially supplying a gate signal to the gate lines, and a data driver supplying an image data signal to the data lines, and the gate driver is attracting attention as a method of forming an integrated circuit in the display panel. have.

In recent years, the liquid crystal display has become increasingly high resolution and large in size. As a result, the load of the display panel increases, resulting in an increase in the RC delay, while increasing the number of gate wirings, thereby shortening the pulse width of the gate signal. have. Therefore, as the pulse width of the gate signal is shortened, the charging time for charging the data voltage is relatively shortened, causing a problem that the charging rate of the data voltage is lowered.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a display device for improving driving reliability at high resolution by securing a margin of a gate signal.

A display device according to an exemplary embodiment of the present invention includes a display panel, a data driver, and first to eighth gate circuits. The display panel includes a display area in which a plurality of pixel parts are formed by gate lines and data lines. The data driver outputs a data voltage to the data lines. The first gate circuit unit outputs a gate signal to the 8k-7 gate wiring, and the second gate circuit unit outputs a gate signal to the 8k-6 gate wiring. The third gate circuit unit outputs a gate signal to the 8k-5 gate wire, and the fourth gate circuit unit outputs a gate signal to the 8k-4 gate wire. The fifth gate circuit part outputs a gate signal to the eighth-k-3 gate wire, and the sixth gate circuit part outputs a gate signal to the eighth-k-2 gate wire. The seventh gate circuit part outputs a gate signal to the eighth k-1 gate wiring, and the eighth gate circuit part outputs a gate signal to the eighth k gate wiring.

According to such a display device, driving reliability can be improved by securing a margin by dividing the gate signal to improve the data charge rate.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a schematic plan view of a display device according to an exemplary embodiment of the present invention, and FIG. 2 is a block diagram illustrating the driving unit illustrated in FIG. 1.

1 and 2, a display device according to an exemplary embodiment of the present invention includes a display panel 100, a driving circuit unit, and a flexible circuit board 130. The driving circuit unit includes a driving unit 200, a first gate driving unit 310, and a second gate driving unit 320, and a flexible printed circuit board (FPC) electrically connects the external system and the driving circuit unit. .

The display panel 100 includes an array substrate 110, an opposite substrate 120 facing the array substrate 110 at a predetermined interval, and a liquid crystal layer (not shown) interposed between the two substrates 110 and 120. The display device is divided into a display area DA in which an image is displayed and peripheral areas PA1, PA2, and PA3 surrounding the display area DA.

Gate lines GL1 to GL2n extend in one direction in the display area DA, data lines DL1 to DLm extend in a direction crossing the gate lines GL1 to GL2n, and gate lines GL1. A plurality of pixel portions defined by ˜GL2n and data lines DL1 ˜ DLm are formed. Each pixel unit includes a thin film transistor TFT as a switching element, a liquid crystal capacitor CLC and a storage capacitor CST electrically connected to the thin film transistor TFT. Specifically, the gate electrode and the source electrode of the thin film transistor TFT are electrically connected to one gate line GL and one data line DL, respectively, and the liquid crystal capacitor CLC and the storage capacitor CST are respectively connected to the drain electrode. ) Is electrically connected.

The peripheral areas PA1, PA2, and PA3 include the first peripheral area PA1, the second peripheral area PA2, and the third peripheral area PA3, and the first peripheral area PA1 includes the gate lines GL1. The second peripheral area PA2 is positioned at one end of the GL2n, the second peripheral area PA2 is located at the other end of the gate lines GL1 to GL2n, and the third peripheral area PA3 is one end of the data wires DL1 to DLm. Located in wealth.

The driving unit 200 is formed in a single chip shape and mounted in the third peripheral area PA3, and the raw image data 210a and the synchronization signals (eg, from an external graphic device through the flexible circuit board 130) 210b).

The driver 200 includes a controller 210, a first gate controller 220, a second gate controller 230, a voltage generator 240, and a data driver 250.

The controller 210 receives the raw image data 210a and the synchronization signals 210b through the flexible circuit board 130, and the synchronization signals 210b include the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync. , A main clock signal MCLK and a data enable signal DE. The control unit 210 generates the first gate control signals 210c, the second gate control signals 210d and the data control signals 210e based on the received synchronization signals 210b, respectively. The data driver 250 is provided to the gate controller 220, the second gate controller 230, and the data driver 250, and the image data 210f based on the raw image data 210a together with the data control signal 210e. To provide.

In addition, the controller 210 generates and provides a voltage control signal 210g for controlling the voltage generator 240.

The voltage generator 240 generates and supplies driving voltages required by each unit using a power supply voltage applied from the outside. That is, the gate voltage 240a including the off voltage VOFF is generated and provided to the first and second gate controllers 220 and 230, and the gamma reference voltage 240b is generated to provide the data driver 250 to the data driver 250. The common voltage 240c is generated and provided to the common electrode (not shown) formed on the counter substrate 120.

The first gate controller 220 provides the first gate control signals 210c and the gate voltage 240a to the first gate driver 310. The first gate control signals 210c may include the first vertical start signal STV1, the third vertical start signal STV3, the fifth vertical start signal STV5, the seventh vertical start signal STV7, and the first vertical start signal STV1. Clock signal CLK1, third clock signal CLK3, fifth clock signal CLK5, seventh clock signal CLK7, ninth clock signal CLK9, eleventh clock signal CLK11, and thirteenth clock signal CLK13 and a fifteenth clock signal CLK15.

The second gate controller 230 provides the provided second gate control signals 210d and the gate voltage 240a to the second gate driver 320. The second gate control signals 210d may include the second vertical start signal STV2, the fourth vertical start signal STV4, the sixth vertical start signal STV6, the eighth vertical start signal STV8, and the second vertical start signal STV2. Clock signal CLK2, fourth clock signal CLK4, sixth clock signal CLK6, eighth clock signal CLK8, tenth clock signal CLK10, twelfth clock signal CLK12, and fourteenth clock signal CLK14 and a sixteenth clock signal CLK16.

The data driver 250 converts the image data 210f into a corresponding analog data voltage based on the provided gamma reference voltage 240b, and then synchronizes the data lines DL1 ˜ in synchronization with the timing of the data control signal 210e. Output to DLm).

As such, the driver 200 outputs a data voltage to the data lines DL1 to DLm and provides control signals to drive the first gate driver 310 and the second gate driver 320.

The first gate driver 310 is formed in the first peripheral area PA1 in the form of an integrated circuit, and has an odd number based on the first gate control signals 210c and the gate voltage 240a provided from the driver 200. The gate signal is output to the gate lines. The first gate driver 310 is composed of a plurality of stages, and is divided into first to fourth gate circuit units.

The second gate driver 320 is formed in the second peripheral area PA2 in the form of an integrated circuit and is even-numbered based on the second gate control signals 210d and the gate voltage 240a provided from the driver 200. The gate signal is output to the gate lines. The second gate driver 320 includes a plurality of stages, and is divided into fifth to eighth gate circuit units.

3A to 3D are block diagrams for explaining the first gate driver shown in FIG. 1, and FIGS. 3A to 3D are block diagrams for the first to fourth gate circuits, respectively.

The first gate driver 310 according to an exemplary embodiment of the present invention includes first to n + 4th stages SRC1 to SRCn + 4, and the first to nth stages SRC1 to SRCn are defined as driving stages. N + 1 to + 4th stages are defined as dummy stages. A first gate including first to eighth clock signals CLK1 to CLK8 and first to fourth vertical start signals STV1 to STV4 at one side of the first to n + 4th stages SRC1 to SRCn + 4. A plurality of wires to which the control signals 210c and the off voltage VOFF are applied are formed, and are electrically connected to the stage through the connection wires.

Here, for convenience of description, although illustrated for each of the first to fourth gate circuit units 310a, 310b, 310c, and 310d, the n + 4 stages SRC1 to SRCn + 4 correspond to one-to-one corresponding odd-numbered gate wirings. Are arranged in sequence according to. That is, the first to nth + 4th stages SRC1 to SRCn + 4 are arranged in order.

Referring to FIG. 3A, the first gate circuit 310a is 4t-3 (t is a natural number) that is connected to each other independently among the first to n + 4 stages SRC1 to SRCn + 4 of the first gate driver 310. The last stage is defined as the nth stage, and the last stage is the n + 1 stage (SRCn + 1), which is a dummy stage.

Each stage of the first gate circuit unit 310a includes a first input terminal IN1, a second input terminal IN2, a first clock terminal CK1, a second clock terminal CK2, a power supply terminal VSS, and an output. A terminal OUT is included, and an off voltage VOFF is input to the power supply terminal VSS.

The first clock signal CK1 and the second clock terminal CK2 are alternately provided with a first clock signal CLK1 and a ninth clock signal CLK9 having opposite phases. That is, the first clock signal CLK1 and the ninth clock signal CLK9 are provided to the first clock terminal CK1 and the second clock terminal CK2 of the odd stage, and the first clock terminal of the even stage ( In contrast, the CK1 and the second clock terminal CK2 are provided with the ninth clock signal CLK9 and the first clock signal CLK1.

The output terminal OUT outputs a gate signal (eg, a gate on signal) based on the first clock terminal CK1 signal. That is, the output terminal OUT of the odd stage outputs the gate signal based on the first clock signal CLK1 provided to the first clock terminal CK1, and the output terminal OUT of the even stage outputs the second output terminal OUT. The gate signal is output based on the ninth clock signal CLK9 provided to the clock terminal CK2. Here, the output terminals OUT of the driving stages are connected in one-to-one correspondence with the eighth-k-1 (k is a natural number) gate lines among the gate lines GL1 to GL2n formed in the display panel 100.

The first input terminal IN1 receives an output signal of the preceding stage, and the second input terminal IN2 receives an output signal of the next stage. That is, the gate signal output from the output terminal OUT of the front stage is provided to the first input terminal IN1, and the gate signal output from the output terminal OUT of the next stage stage is provided to the second input terminal IN2. Is provided. Here, the first vertical start signal STV1 is provided to the first input terminal IN1 of the first stage SRC1 and the second input terminal IN2 of the last stage SRCn + 1.

As described above, the first gate circuit 310a includes a plurality of stages, and is connected to the first clock signal CLK1, the ninth clock signal CLK9, the first vertical start signal STV1, and the off voltage VOFF. The gate signal is output to the 8k-1 gate wiring based on this.

Meanwhile, the stages of the second to fourth gate circuit parts 310b, 310c, and 310d have the same structure and have different differences in the control signals compared to the first gate circuit part 310a. A brief description will be given of the differences from the one-gate circuit unit 310a.

Referring to FIG. 3B, the second gate circuit 310b is defined as the 4t-2th stages connected to each other among the first to n + 4 stages SRC1 to SRCn + 4 of the first gate driver 310. The last stage is an n + 2th stage (SRCn + 2) which is a dummy stage.

The second gate circuit 310b is formed in the display panel 100 based on the third clock signal CLK3, the eleventh clock signal CLK11, the third vertical start signal STV3, and the off voltage VOFF. The gate signal is output to the 8K-5 gate wiring among the gate wirings GL1 to GL2n. Here, the third clock signal CLK3 and the eleventh clock signal CLK11 are opposite in phase to each other.

Referring to FIG. 3C, the third gate circuit 310c is defined as 4t−1 th stages connected to each other among the first to n + 4 stages SRC1 to SRCn + 4 of the first gate driver 310. The last stage is the n + 3th stage (SRCn + 3) which is a dummy stage.

The third gate circuit 310c is formed in the display panel 100 based on the fifth clock signal CLK5, the thirteenth clock signal CLK13, the fifth vertical start signal STV5, and the off voltage VOFF. The gate signal is output to the eighth-k-3 gate wire among the gate wires GL1 to GL2n. Here, the fifth clock signal CLK5 and the thirteenth clock signal CLK13 are opposite in phase.

Referring to FIG. 3D, the fourth gate circuit unit 310d is defined as 4t-th stages that are connected to each other independently among the first to n + 4 stages SRC1 to SRCn + 4 of the first gate driver 310. The last stage is the n + 4th stage (SRCn + 4) which is a dummy stage.

The fourth gate circuit 310d may be connected to the display panel 100 based on the seventh clock signal CLK7, the fifteenth clock signal CLK15, the seventh vertical start signal STV7, and the off voltage VOFF. The gate signal is output to the 8k-1 gate line among the formed gate lines GL1 to GL2n. Here, the seventh clock signal CLK7 and the fifteenth clock signal CLK15 are opposite in phase.

Although not shown, the second gate driver 320 according to an exemplary embodiment of the present invention includes first to nth + 4 stages, and the first to nth stages are defined as driving stages, and n + 1 to The n + 4th stage is defined as a dummy stage.

The second gate driver 320 includes fifth to eighth gate circuit parts and has a basic configuration with the first gate driver 310 including first to fourth gate circuit parts 310a, 310b, 310c, and 310d. Since similar in, it will be briefly described with a focus on differences for convenience of description.

The configuration of the fifth to eighth gate drivers is the same as that of the first to fourth gate circuits 310a, 310b, 310c, and 310d described above.

The fifth gate circuit part includes the eighth-k among the gate lines GL1 to GL2n based on the second clock signal CLK2, the tenth clock signal CLK10, the second vertical start signal STV2, and the off voltage VOFF. 6 A gate signal is output to the gate wiring. Here, the second clock signal CLK2 and the tenth clock signal CLK10 are opposite in phase.

The sixth gate circuit part includes the eighth-k among the gate lines GL1 to GL2n based on the fourth clock signal CLK4, the twelfth clock signal CLK12, the fourth vertical start signal STV4, and the off voltage VOFF. 4 Output a gate signal to the gate wiring. The fourth clock signal CLK4 and the twelfth clock signal CLK12 are opposite in phase to each other.

The seventh gate circuit part includes the eighth-k among the gate lines GL1 to GL2n based on the sixth clock signal CLK6, the fourteenth clock signal CLK14, the sixth vertical start signal STV6, and the off voltage VOFF. A gate signal is output to the two gate wirings. Here, the sixth clock signal CLK6 and the fourteenth clock signal CLK14 are opposite in phase to each other.

Finally, the eighth gate circuit part may include the eighth gate circuit part among the gate lines GL1 to GL2n based on the eighth clock signal CLK8, the sixteenth clock signal CLK16, the eighth vertical start signal STV8, and the off voltage VOFF. The gate signal is output to the 8k gate lines. Here, the eighth clock signal CLK8 and the sixteenth clock signal CLK16 are opposite in phase to each other.

4 is a diagram conceptually illustrating a configuration of a stage that constitutes the first and second gate drivers, and FIG. 5 is a signal waveform diagram for describing an operation of the first and second gate drivers.

Here, since the stages of the first to eighth gate circuit units have the same configuration, the first and ninth clock terminals CK1 and CK2 are respectively provided to the first and second clock terminals CK1 and CK2 among the stages of the first gate circuit unit 310a for convenience of description. An arbitrary stage (e.g., odd-numbered stage) that receives and drives the clock signals CLK1 and CLK9 will be described as a representative example.

3A, 4, and 5, the stage SRC includes a pull-up part 311, a pull-down part 312, a pull-up driving part 313, a ripple prevention part 314, and a pull-down control part 315. .

The pull-up unit 311 outputs a high section of the first clock terminal CK1 signal, that is, the first clock signal CLK1 provided to the first clock terminal CK1 to the output terminal OUT, thereby providing a gate. Pull up the signal.

In detail, the pull-up unit 311 includes a first transistor TR1 having an input electrode connected to the first clock terminal CK1 and an output electrode connected to the output terminal OUT. The pull-up unit 311 further includes a charging capacitor C1 formed between the control electrode and the output electrode of the first transistor TR1. The charging capacitor C1 is provided to the first input terminal IN1 to store the high value of the output signal (or the first vertical start signal) of the front stage applied to the control electrode of the first transistor TR1 to store the first transistor. Turn on (TR1). The first capacitor C1 may be defined by an overlap region of the control electrode and the output electrode of the first transistor TR1.

The pull-down unit 312 includes a first pull-down unit 312a and a second pull-down unit 312b, and the first pull-down unit 312a is connected to the ninth clock signal CLK9, which is a second clock terminal CK2 signal. In response, the gate signal output to the output terminal OUT is switched to the off voltage (VOFF, low value) to pull-down. The second pull-down unit 312b maintains the gate signal output to the output terminal OUT at the off voltage VOFF in response to the first clock signal CLK1, which is the first clock terminal CK1, to pull-down ( pull-down). Here, the first clock signal CLK1 for turning on the second pull-down part 312b is a signal charged in the switching capacitor C2 which will be described later.

Specifically, in the first pull-down unit 312a, the input electrode is connected to the voltage terminal VSS to receive the off voltage VOFF, and the control electrode is connected to the second clock terminal CK2 to supply the ninth clock signal CLK9. ), The output electrode is composed of a second transistor (TR2) connected to the output terminal (OUT). The second pull-down unit 312b has an input electrode connected to the voltage terminal VSS to receive the off voltage VOFF, a control electrode connected to the switching capacitor C2, and an output electrode connected to the output terminal OUT. Consisting of a third transistor TR3.

The pull-up driving unit 313 turns on the pull-up unit 311 in response to the high value of the output signal of the previous stage, which is the first input terminal IN1, and the second stage of the next stage, which is the second input terminal IN2. The pull-up unit 311 is turned off in response to the high value of the output signal.

In detail, the pull-up driving unit 313 includes a first pull-up driving unit 313a and a second pull-up driving unit 313b. In the first pull-up driving unit 313a, an input electrode and a control electrode are commonly connected to the first input terminal IN1, and an output electrode is connected to the control electrode of the first transistor TR1 to form a first node T1. 4th transistor TR4. In this case, the control electrode of the first transistor TR1 may be defined as a control electrode for switching on / off of the pull-up part 311. In the second pull-up driving unit 313b, an input electrode is connected to the voltage terminal VSS, an output electrode is connected to a control electrode of the first transistor TR1, and forms a first node T1, and the control electrode is a second input. The fifth transistor TR5 is connected to the terminal IN2.

When the fourth transistor TR4 is turned on in response to the high value of the output signal of the front stage, the pull-up driving unit 313 is applied with the high value of the output signal of the front stage to the first node to charge the capacitor C1. Is charged. The charge capacitor C1 is charged with a charge equal to or greater than the threshold voltage of the first transistor TR1, and the second switching element TR2 bootstraps as the first clock signal CLK1, which is a low value, is inverted (converted) to a high value. (Bootstrap) to output the high value of the first clock signal CK to the output terminal OUT.

Thereafter, when the fifth transistor TR5 is turned on in response to the high value of the output signal of the next stage, the charge charged in the charging capacitor C1 is discharged to the off voltage VOFF of the voltage terminal VSS. . The first node T1 is switched to a low value due to the discharge of the charging capacitor C1, and the first transistor TR1 is turned off to stop the output of the first clock signal CLK1.

When the second transistor TR2 is turned on in response to the high value of the ninth clock signal CLK9 together with the turn-off of the first transistor TR1, the gate signal output to the output terminal OUT is turned off. Switch to voltage VOFF. In addition, the third transistor TR3 is turned on in response to the high value of the first clock signal CLK1 charged in the charging capacitor C2, and the signal output to the output terminal OUT continues to the low value. maintain. That is, the second transistor T2 and the third transistor TR3 are alternately turned on to pull down the gate signal output to the output terminal OUT to a low value.

The ripple prevention unit 314 maintains the first node T1 at the off voltage VOFF to prevent ripple of the first node T1 caused by the coupling of the first clock signal CLK1. do.

In detail, the ripple prevention unit 314 is connected to the voltage terminal VSS to receive the off voltage VOFF, and the control electrode is connected to the switching capacitor C2 to input the first clock signal CLK1. The output electrode includes a sixth transistor TR6 connected to the first node T1. The ripple prevention unit 314 turns off the pull-up unit 311 by keeping the first node T1 at a low value after the gate signal is converted to a low value by the pull-down unit 312. Coupling by the one clock signal CLK1 prevents a ripple generated in the first node T1. That is, when the sixth transistor TR6 is turned on in response to the high value of the first clock signal CLK1 charged in the switching capacitor C2, the ripple prevention unit 314 may turn off the first voltage VOFF. It is applied to and maintained at the node T1.

The pull-down control unit 315 turns off the ripple prevention unit 314 in response to the signal of the first node T1.

In detail, the pull-down control unit 315 is connected to the voltage terminal VSS to receive the off voltage VOFF, the output electrode is connected to the second node T2, and the control electrode is connected to the first node T1. ) Is connected to the seventh transistor TR7). When the high value of the first clock signal CLK1 is applied to the second node T2 through the pull-down control unit 315 switching capacitor C2, when the signal of the first node T1 is high, the seventh Transistor TR7 is turned on to switch second node T2 to a low value. Therefore, even when the first clock signal CLK1 becomes high in the period when the first node T1 becomes high and the pull-up unit 310 is turned on, the second ripple prevention part 314 is turned off. do.

The switching capacitor C2 has one electrode connected to the first clock terminal CK1 and the other electrode connected to the control electrode of the third and sixth transistors TR3 and TR6 and the output electrode of the seventh transistor TR7. A second node T2 is formed. The switching capacitor C2 receives and stores the first clock signal CLK1 and turns on the third and sixth transistors TR3 and TR6 by applying the stored first clock signal CLK1 to the second node T2. Turn it on / off.

Here, the first and ninth clock signals CLK1 and CLK9 are inverted every 8H (H is a horizontal section), and the phases are opposite to each other. Accordingly, the first gate circuit 310a, in which the output of the gate signal is started by the first vertical start signal STV1, sequentially outputs a gate signal having a pulse width of 8H to the 8k-7 gate wiring.

Meanwhile, control signals provided to the first to eighth gate circuits will be described with reference to FIG. 5.

The first to eighth vertical start signals STV1 to STV8 have pulse widths corresponding to 8H sections, and are sequentially delayed and applied by 1H sections. Accordingly, the first, fifth, second, sixth, third, seventh, fourth, and eighth gate circuits are sequentially delayed by 1H sections to start the output operation of the gate signal.

The first to sixteenth clock signals CLK1 to CLK16 are inverted every 8H section. That is, the first to sixteenth clock signals CLK1 to CLK16 have a pulse width corresponding to the 8H section and a period corresponding to the 16H section. The first to eighth clock signals CLK1 to CLK8 are sequentially delayed and applied by 1H section. The first to eighth clock signals CLK1 to CLK8 are applied starting with a low value in synchronization with the first to eighth vertical start signals STV1 to STV8, respectively, and the ninth to sixteenth clock signals CLK9 to CLK16. Is opposite in phase to the first to eighth clock signals CLK1 to CLK8.

The first to eighth gate circuits receiving these signals output gate signals to corresponding gate lines, and the first to eighth gate circuits are synchronized with the first to eighth vertical start signals STV1 to STV8, respectively. The output of the gate signal is started, and the gate signal is output based on the two clock signals that are out of phase with each other. Therefore, a gate signal having a pulse width corresponding to the 8H section is sequentially output to the gate lines, thereby securing a margin of the gate signal.

In addition, the data driver outputs the data voltage D01 for one horizontal pixel column to the data lines DL1 to DLm in synchronization with the output gate signals, and outputs the data voltage in synchronization with the last 1H section of the gate signals. . Here, the initial 7H section of each gate signal may be defined as a precharging section of the previously output data voltage, and the charging rate may be improved by such precharging.

As described above, according to the present invention, a margin is secured through eight-division driving of the gate signal to improve the data filling rate of the pixel portion, thereby improving driving reliability at high resolution.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (9)

A display panel including a display area in which a plurality of pixel portions are formed by gate lines and data lines; A data driver outputting a data voltage to the data lines; A first gate circuit unit configured to output a gate signal to the eighth-k-7 gate wire; A second gate circuit unit configured to output a gate signal to the eighth-6th gate line; A third gate circuit unit configured to output a gate signal to the eighth-5th gate line; A fourth gate circuit part configured to output a gate signal to the eighth-k-4 gate wire; A fifth gate circuit part configured to output a gate signal to the eighth-k-3 gate wire; A sixth gate circuit part configured to output a gate signal to the eighth-k-2 gate wire; A seventh gate circuit part configured to output a gate signal to the eighth-k-1 gate wire; And And a eighth gate circuit unit configured to output a gate signal to the eighth gate line (k is a natural number). The gate driving circuit of claim 1, wherein each of the first to eighth gate circuit units includes a plurality of stages connected to each other independently. Each stage A pull-up unit configured to output a high value of the first clock terminal signal to an output terminal in response to a high value of the first input terminal signal; A pull-up driving unit turning off the pull-up unit by switching a control electrode of the pull-up unit to a low value in response to a high value of a second input terminal signal; A first pull-down unit which converts a signal output to the output terminal to a low value in response to a high value of a second clock terminal signal; A second pull-down unit configured to maintain a signal output to the output terminal at a low value in response to a high value of the first clock terminal signal; A ripple prevention unit configured to maintain a control electrode of the pull-up unit at a low value in response to a high value of the first clock terminal signal; And And a pull-down control unit which turns off the second pull-down unit and the ripple prevention unit when the control electrode signal of the pull-up unit has a high value. 3. The first clock terminal signal of claim 2, wherein the first clock terminal signal of the first to eighth gate circuits is a first to eighth clock signal inverted every 8H (H is a horizontal section). And a ninth through a sixteenth clock signals having a phase opposite to that of the first through the eighth clock signals, respectively. The display device of claim 3, wherein the first to eighth clock signals are sequentially delayed and applied in 1H intervals. The display device of claim 4, wherein the first to eighth clock signals and the ninth to sixteenth clock signals are inputted opposite to an odd stage and an even stage. The display device of claim 4, wherein the first input terminal signal is an output signal of a previous stage, and the second input terminal signal is an output signal of a next stage. The method of claim 6, wherein the first input terminal signal of the first stage and the second input terminal signal of the last stage are first to eighth vertical start signals, respectively. And the first to eighth vertical start signals have a pulse width of 8H section and are sequentially delayed for each 1H section. The display device of claim 7, wherein the display panel further comprises a peripheral area surrounding the display area. The first, third, fifth and seventh gate circuits are defined as first gate drivers and are formed in the peripheral region located at one end of the gate lines; And wherein the second, fourth, sixth, and eighth gate circuits are defined as second gate drivers and formed in the peripheral region located at the other end of the gate lines. The method of claim 8, A plurality of stages constituting the first, third, fifth and seventh gate circuits are sequentially arranged in the order of the corresponding gate wirings, And a plurality of stages constituting the second, fourth, sixth, and eighth gate circuit parts are sequentially arranged in the order of the corresponding gate wirings.

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