KR20080052733A - Display panel and display apparatus having the same - Google Patents

Abstract

A display panel and a display apparatus having the same are provided to reduce delay of a gate signal increasing in a direction of a gate wiring line by forming a short gate wiring line. A display panel(100) includes a display substrate(110), a plurality of gate wiring lines, a first gate driving circuit(210), and a second gate driving circuit(220). The display substrate has a display area and a surrounding area which surrounds the display area. The plurality of gate wiring lines extends to the display area in one direction and shorts in the center part. The first gate driving circuit is electrically connected to the gate wiring lines to output a gate signal. The second gate driving circuit is electrically connected to another end of the gate wiring lines to output the gate signal.

Description

DISPLAY PANEL AND DISPLAY APPARATUS HAVING THE SAME}

1 is a plan view illustrating a display device according to an exemplary embodiment of the present invention.

FIG. 2 is an internal configuration diagram illustrating an example of the first and second gate driving circuits illustrated in FIG. 1.

3 illustrates a gate signal waveform diagram of a display device according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100: display panel 110; Array board

120: opposing substrate 210: first gate driving circuit

220; Second gate driving circuit 300: data driver

400: flexible printed circuit board DA: display area

CLC: liquid crystal capacitor CST: storage capacitor

TFT: thin film transistor DA1, DA2: first and second display regions

PA1, PA2, PA3: Peripheral Area GL11 to GL1n: First Gate Wirings

GL21 to GL2n: second gate wires

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display panel and a display device having the same, and more particularly, to a display panel and a display device having the same to improve a flicker phenomenon and luminance variation caused by a delay of a gate signal.

In general, a liquid crystal display device artificially applies an electric field to a liquid crystal layer having an anisotropic dielectric constant interposed between two substrates, and adjusts the amount of light transmitted by changing the arrangement angle of liquid crystal molecules according to the intensity of the applied electric field. It is a flat panel display device that displays.

The liquid crystal display includes a display panel in which a plurality of pixel parts are defined by gate lines and data lines to display an image, a gate driver to output a gate signal to the gate lines, and a data driver to output a data voltage to the data lines. It includes. In the operation of the liquid crystal display, when the data voltage applied to the data line is transferred to the pixel portion by the gate signal applied to the gate lines, the arrangement direction of the liquid crystal molecules of the pixel portion is changed in accordance with the data voltage, thereby improving light transmittance. Adjust to display the desired image.

Here, a signal delay is generated due to a parasitic cap, etc. while the gate signal output from the gate driver passes along the gate wiring, and the delay of the gate signal causes a poor charging rate of the data voltage or a different data voltage is applied. This happens. For this reason, there exists a problem that a flicker phenomenon and a brightness deviation generate | occur | produce according to the advancing direction of a gate wiring.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a display panel for improving the flicker and luminance deviation caused by the delay of the gate signal while traveling in the gate wiring direction. .

Another object of the present invention is to provide a display device for improving the flicker and luminance deviation caused by the delay of the gate signal in the direction of the gate wiring.

A display panel according to an embodiment for realizing the object of the present invention includes a display substrate, gate wirings, a first gate driving circuit, and a second gate driving circuit. The display substrate includes a display area and a peripheral area surrounding the display area. The gate lines extend in one direction to the display area and are disconnected at the center portion. The first gate driving circuit is electrically connected to one end of the gate lines to output a gate signal. The second gate driving circuit is electrically connected to the other ends of the gate lines to output the gate signal.

According to another exemplary embodiment of the present invention, a display device includes a display panel, gate lines, data lines, a first gate driver circuit, a second gate driver circuit, and a data driver. The display panel includes a display area and a peripheral area surrounding the display area. The gate lines extend in one direction to the display area and are disconnected at the center portion. The data lines extend in a direction crossing the gate lines in the display area. The first gate driving circuit is electrically connected to one end of the gate wires to output a gate signal, and the second gate driving circuit is electrically connected to the other end of the gate wires to output the gate signal. The data driver outputs a data voltage to the data lines.

According to such a display device, by shortening the length of the gate wiring and reducing the delay amount of the gate signal that increases while proceeding in the direction of the gate wiring, the flicker and the luminance variation caused by the decrease in the charge rate of the data voltage due to the delay of the gate signal are eliminated. It can be improved.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display panel 100, a driving circuit unit, and a flexible printed circuit board 300. The driving circuit unit includes a first gate driving circuit 210, a second gate driving circuit 220, and a data driver 300.

The display panel 100 includes an array substrate 110 and a counter substrate 120 (for example, a color filter substrate) and a liquid crystal layer (not shown) having an anisotropic dielectric constant interposed between the array substrate 110 and the counter substrate 120. do. The display panel 100 includes a display area DA and a peripheral area PA surrounding the display area DA.

In the display area DA of the array substrate 110, the plurality of gate lines GL1 to GLn extend in parallel in one direction, and the gate lines GL1 to GLn are disconnected at the center portion. That is, the gate lines GL1 to GLn are disconnected from each other by being disconnected from the center area of the display area DA, and are not electrically connected to each other. In addition, a plurality of data lines DL1 to DLm extend in the display area DA in a direction crossing the gate lines GL1 to GLn, and the gate lines GL1 to GLn and the data lines DL1 to DLm) define a plurality of pixel portions.

Each pixel unit includes a thin film transistor TFT connected to a gate line GL and a data line DL, a pixel electrode (not shown) and a storage capacitor CST electrically connected to the thin film transistor TFT. The electrode is defined as the first electrode of the liquid crystal capacitor CLC. Specifically, the gate electrode and the source electrode of the thin film transistor TFT are connected to the gate line (eg, the first gate line or the second gate line) and the data line, respectively, and the pixel electrode and the storage capacitor CST are connected to the drain electrode. Electrically connected.

The peripheral areas PA1, PA2, and PA3 are the first peripheral area PA1 located at one end of the gate lines GL1 to GLn and the second peripheral area located at the other end of the gate lines GL1 to GLn. And a third peripheral area PA3 positioned at one end of the data lines DL1 to DLm.

In the first peripheral area PA1 of the array substrate 110, a first gate driving circuit 210 connected to one end of the plurality of gate lines GL11 to GL1n and sequentially outputting a gate signal is formed in an integrated circuit form. Is formed. That is, the first gate driving circuit 210 sequentially outputs a gate signal for activating the gate lines GL1 to GLn to one end of the gate lines GL1 to GLn, so that the first gate driving circuit 210 outputs the gate signal GL1 to GLn. To the gate lines GL1 to GLn).

In the second peripheral area PA2, a second gate driving circuit 220 connected to the other ends of the plurality of gate lines GL1 to GLn and sequentially outputting a gate signal is formed in an integrated circuit form. That is, the second gate driving circuit 220 sequentially outputs a gate signal for activating the gate lines GL1 to Gln to the other end of the gate lines GL1 to GLn, and thus gate gates from the other end to the center part. Activate them (GL1 to GLn).

Here, the gate signals of the first gate driving circuit 210 and the second gate driving circuit 220 are output in the same order. Therefore, the thin film transistor TFT is turned on in units of one horizontal pixel column.

On the opposite substrate 120, color filter patterns are formed corresponding to the pixel portions of the array substrate 110. For example, the color patterns include red, green, and blue patterns. The opposite substrate 120 is provided with a common electrode (not shown) facing the pixel electrode, and the common electrode is defined as a second electrode of the liquid crystal capacitor CLC. That is, the pixel electrode and the common electrode form a liquid crystal capacitor CLC using a liquid crystal layer interposed between the pixel electrode and the common electrode as a dielectric.

The data driver 300 including at least one driving chip is mounted in the third peripheral area PA3 of the array substrate 110, and the data driver 300 is disposed on the gate lines GL1 to GLn. A data voltage corresponding to each of the data lines DL1 to DLm is output in synchronization with an applied gate signal. That is, since the first gate driving circuit 210 and the second gate driving circuit 220 output gate signals one line, the data voltage is output one horizontal pixel column.

The flexible printed circuit board 400 electrically connects the display panel 100 and an external driving circuit board (not shown), and receives a gate control signal from the driving circuit board (not shown) to receive the first gate driving circuit 210. ) And the second gate driver circuit 220, and receives a data control signal and transmits the data control signal to the data driver 300.

FIG. 2 is an internal configuration diagram illustrating an example of the first and second gate driving circuits illustrated in FIG. 1.

Here, since the configurations of the first gate driving circuit 210 and the second gate driving circuit 220 are the same, only the first gate driving circuit 210 will be described.

1 and 2, the first gate driving circuit 210 includes one shift register made up of a plurality of stages SRC1 to SRCn + 1 that are connected to each other independently, and includes n driving stages SRC1 to SRCn. ) And one dummy stage SRCn + 1.

Each stage includes a first input terminal IN1, a second input terminal IN2, a first clock terminal CK, a second clock terminal CKB, a power supply terminal VSS, and an output terminal OUT. The gate-off voltage Voff is input to the power supply terminal VSS.

The first clock terminal CK1 and the second clock terminal CK2 have the first clock signal CK and the second clock signal CK at the first clock terminal CK1 and the second clock terminal CK2 of the odd stage, respectively. CKB) is supplied, and the second clock signal CKB and the first clock signal CK are supplied to the first clock terminal CK1 and the second clock terminal CK2 of the even-numbered stage, respectively.

The output terminal OUT outputs a gate signal synchronized with the first clock signal CK or the second clock signal CKB input to the first clock terminal CK1. Here, the output terminals OUT of the n driving stages SRC1 to SRCn except for the dummy stage SRCn + 1 correspond to the gate wirings GL1 to GLn formed in the first display area DA in one-to-one correspondence. (GL1 to GLn) are connected to one end. In the case of the second gate driving circuit 220, the second gate driving circuit 220 is connected to the other ends of the gate lines GL1 to GLn.

 The gate signal output through the output terminal OUT is supplied to the second input terminal IN2 of the front stage and the first input terminal IN1 of the next stage. Here, the vertical start signal STV is applied to the first input terminal IN1 of the first stage SRC1 without the front stage and the second input terminal IN2 of the n + 1th stage SRCn + 1 without the next stage. ) Is supplied.

Meanwhile, one side of the shift register including n + 1 stages SRC1 to SRCn + 1 has a first clock signal CK, a second clock signal CKB, a vertical start signal STV, and a gate-off voltage Voff. The applied wiring portion is formed and electrically connected to each stage.

As a result, the first gate driving circuit 210 sequentially outputs a gate signal to one end of the gate lines GL1 to GLn, and the second gate driving circuit 220 generates the gate lines GL1 to GLn. The gate signal is sequentially output to the other end of GLn).

3 illustrates a gate signal of a display device according to an exemplary embodiment of the present invention.

1 and 3, an ideal gate signal is defined as a signal corresponding to a signal inlet of the gate lines GL, and has a waveform close to a pulse waveform as shown in the drawing.

The general gate signal is applied to one end of the gate lines GL1 to GLn (for example, a signal inlet) to transfer the gate signal through one gate line GL to the other end, and the gate lines GL1 to GLn. It is defined as a gate signal corresponding to the other end of.

The gate signal of the present invention is applied to one end and the other end of the gate lines and transmitted to the center portion, and is defined as a gate signal corresponding to the center portion of the gate lines GL1 to Gln.

That is, the waveforms of the illustrated general gate signal and the gate signal of the present invention may be defined as waveforms corresponding to where signal delays occur most.

As shown, the display device according to the exemplary embodiment of the present invention applies a gate signal to one end (or the other end) of the gate lines GL1 to GLn and proceeds only to the center part, so that the signal delay is small. In the case of a signal, a signal delay is large because one end of the gate lines GL1 to GLn extends to the other end. Therefore, the transmission period of the gate signal is relatively short, so that the signal delay is improved.

As the delay of the gate signal is improved, a section in which the gate signal has a value greater than or equal to the threshold voltage Vth increases, and the threshold voltage Vth turns on the thin film transistor TFT formed in the pixel portion. Is defined as the voltage for Therefore, the charging time of data is increased, and the data filling rate is improved, and flicker and luminance deviation can be improved due to the improvement of the data filling rate.

As described above, according to the present invention, the gate driver is disposed on both sides of the display area, and the application period of the gate lines to which the gate signal is applied is shortened to half so as to shorten the gate signal. Reduce the amount of delay Therefore, the flicker and the luminance deviation caused by the lowering of the charge rate of the data voltage due to the delay of the gate signal can be improved.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (7)

A display substrate comprising a display area and a peripheral area surrounding the display area; A plurality of gate wires extending in one direction and disconnected at a central portion of the display area; A first gate driving circuit electrically connected to one end of the gate lines to output a gate signal; And And a second gate driving circuit electrically connected to the other ends of the gate lines to output the gate signal. The gate driving circuit of claim 1, wherein the first gate driving circuit is formed in a peripheral area at one end of the gate wires, and the second gate driving circuit is formed in a peripheral area at the other end of the gate wires. Display panel. The display panel of claim 2, further comprising a plurality of data lines extending in a direction crossing the gate lines in the display area. The display panel of claim 3, wherein the first gate driving circuit and the second gate driving circuit include a shift register including a plurality of stages connected to each other, and are integrated in the peripheral area in an integrated circuit form. . A display panel comprising a display area and a peripheral area surrounding the display area; A plurality of gate wires extending in one direction and disconnected at a central portion of the display area; A plurality of data lines extending in a direction crossing the gate lines in the display area; A first gate driving circuit electrically connected to one end of the gate lines to output a gate signal; A second gate driving circuit electrically connected to the other ends of the gate lines to output the gate signal; And And a data driver configured to output data voltages to the data lines. The method of claim 5, wherein the first gate driving circuit is formed in a peripheral area located at one end of the gate wirings, the second gate driving circuit is formed in a peripheral area located at the other end of the gate wirings Display device. The display device of claim 6, wherein the first gate driving circuit and the second gate driving circuit include a shift register including a plurality of stages connected to each other, and are formed in the peripheral area in an integrated circuit form. .

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